JP2867798B2 - Advance control unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a precedence controller, in particular, some software instructions are realized by a program consisting of a software instruction group stored in a main memory, the instructions are prefetched, and the prefetched instructions are decoded. The present invention relates to a precedence control device provided in an information processing device having a pipeline configuration that prefetches operands based on a result.

[0002]

2. Description of the Related Art In this type of prior art control device, when starting a program, a start address of the program is designated in a microprogram started by executing an instruction, or a table is prepared in a main memory. The start address is obtained by indexing the table by the microprogram , and the obtained start address is set in the preceding control device by the microprogram to issue an instruction fetch instruction.

[0003]

In the above-mentioned prior-art control device, when the program start address is specified in the microprogram before the start address is obtained, the table prepared in the main memory is indexed by the microprogram. In either case, time is required. Also, after obtaining the start address of the program, it sets the starting address until the start of the program to the preceding control unit by a microprogram, in order to perform an instruction for extracting the instruction, poor performance would be needed more time There was a problem of doing it.

[0004]

According to the present invention, there is provided an apparatus wherein software instructions are partially stored in a main memory.
Realized by a program consisting of groups , pre-fetching instructions,
In a preceding control device in an information processing device having a pipeline configuration for prefetching an operand based on a result of decoding a prefetched instruction, a program comprising a software instruction group in which the prefetched instruction is stored in the main storage. And an instruction decoder that outputs a start address of a main memory of a program including a software instruction group stored in the main memory when the instruction is realized by the following.

[0005]

Next, embodiments of the present invention will be described with reference to the drawings.

[0006] FIG. 3 is a pipeline diagram to which the present invention is applied.

In FIG. 3, a stage 3-1 is a stage for fetching an instruction. An instruction word is read from an instruction cache and supplied to a stage 3-2 for each instruction. The stage 3-2 is a stage for decoding an instruction and calculating a logical address of a memory address (that is, address syllable expansion) in the case of an instruction having a memory operand.

The stage 3-3 is a whole address calculation stage for converting the logical address obtained in the stage 3-2 into an absolute address, and a stage for indexing the address conversion buffer.

Stage 3-4 is a stage for indexing the operand cache. The operand cache is indexed based on the entire address output from stage 3-3, and memory operands are read.

The stage 3-5 is a stage for executing an instruction, and performs an operation by using the memory operand and the register operand obtained in the stage 3-4 as inputs. The control of this operation is controlled by a microprogram. The microprogram of each instruction is stored in the control storage. The address of the control storage is obtained by the instruction decoding of the stage 3-2, read from the control storage of the stage 3-4, and executed in the stage 3-5. Stage 3-
Reference numeral 6 denotes a stage for writing the operation result executed in the stage 3-5 to a memory or a register.

If the program flows smoothly, the stages 3-1 → 3-2 → 3-3 → 3-4 → 3-5 → 3-6 are executed in order, and if there is a branch instruction in the program, , The absolute address of the branch destination obtained in the stage 3-3 is returned to the stage 3-1 and the programs of the branch destination are sequentially executed from the stage 3-1.

If the program or task is started, or the address space of the program or task is switched and the switched address can be known only by executing the microprogram in stage 3-5, the stage is controlled by the instruction of the microprogram. The logical address is input to the stage 3-2 from the stage 3-5 and the stage 3-2
It is executed in the order of → 3-3 → 3-1, and then enters a normal processing flow.

FIG. 1 shows a first embodiment of the present invention, and FIG.
3 is a block diagram of a preceding control device that executes a stage 3-2 in FIG.

In FIG. 1, an instruction register 1-1 is an instruction register for holding an instruction word supplied by the stage 3-1. The instruction decoder 1-2 is an instruction decoder composed of a RAM. Among instruction words held in the instruction register 1-1, an instruction code portion is given as an address, and an output of the instruction decoder 1-2 is a register. 1-3
And registers 1-4.

A portion indicating the address of the operand of the instruction word of the instruction register 1-1, that is, of the fields of the address syllable, the fields specifying the base register and the index register are respectively stored in the register file 1.
-5 and a read address of the register file 1-6, and the respective outputs are input to a three-input adder 1-7. The remaining one input of the three-input adder 1-7 is provided with a displacement field in the address syllable.

The result added by the three-input adder 1-7 becomes the logical address of the operand, is set in the register 1-8, and sent to the stage 3-3 via the selector 1-9. Request type request decoder 1-10 to perform a prefetch operands (read / write / branching, etc.), i.e., the decoder consists of RAM to hold the request decoders, its address, register 1-
The output of the request code 3 is given via the selector 1-11, and the read request code is sent to the stage 3-3 together with the logical address described above.

[0017] When instructed by the instruction fetch start the stage 3 -5 microprogram of the selection of the address signal lines 1-12 at the logical address to the selector 1-9 from address signal lines 1-12, The selector 1-11 selects a fixed address for reading the request code of the branch from the request decoder 1-10, so that the start address of the instruction and the request for the branch which means the fetch of the instruction are transmitted to the stage 3-3.
To send to.

The contents stored in the instruction decoder 1-2 are as follows:
Apart from the address of the request decoder 1-10, when the instruction to be decoded is an instruction realized by a software instruction program stored in the main memory, there is also a start address of the program in the main memory, and the register 1-4 is ,
This is a register that holds the start address.

At the start of the program, the instruction is processed in each stage of the pipeline, and when the instruction reaches the stage 3-5 , the select signal line 1-
13, the selector 1-9 selects the register 1-4, and the selector 1-11 selects a fixed value, so that the start address of the program for realizing the instruction is set as a branch request code. , Stage 3-3.

FIG. 2 shows a second embodiment of the present invention, and FIG.
3 is a block diagram of a preceding control device that executes a stage 3-2 in FIG. Components common to those in FIG. 1 are denoted by common numbers.

In this embodiment, the instruction decoder 2-2
Is defined as a content that is an instruction realized by a software instruction program. This bit is read by the instruction decoder 2-2 and then held in the flip-flop 2-100.

Then, the logical address held by the register 2-8 for prefetching the operand and the corresponding request code are indexed by the request decoder 2-10 and sent to the stage 3-3. receives an output of 2-100 to the logic circuit 2-10 2 select signal of the selector 2-9,2-11 2-102,2-
According to 103, the register 2-4 holding the program start address is selected as the logical address and the fixed value is selected as the address of the request decoder 2-10, so that the program start instruction is not performed via the control of the microprogram. To do.

According to this embodiment, following the prefetching of the operands, the next instruction is fetched at the start address of the stored program, so that the time for issuing the instruction to start fetching the next instruction by the microprogram is reduced. be able to.

[0024]

As described above, according to the present invention, when an instruction realized by a program consisting of a software instruction group stored in the main memory is decoded, the start address of the program is output and held, whereby the This has the effect of shortening the time required to find the program start address in the program and improving the performance.

[Brief description of the drawings]

FIG. 1 is a pipeline configuration diagram of an information processing apparatus to which the present invention is applied.

FIG. 2 is a block diagram of a preceding control device showing a first embodiment of the present invention.

FIG. 3 is a block diagram of a preceding control device showing a second embodiment of the present invention.

[Explanation of symbols]

 1-1 Instruction Register 1-2 Instruction Decoder 1-3 Register 1-4 Register 1-5 Register File 1-6 Register File 1-7 3-Input Adder 1-8 Register 1-9 Selector 1-10 Request Code Decoder 1 -11 Selector 1-12 Address signal line 1-13 Select signal line 2-1 Instruction register 2-2 Instruction decoder 2-3 Register 2-4 Register 2-5 Register file 2-6 Register file 2-7 3-input adder 2-8 Register 2-9 Selector 2-10 Request Code Decoder 2-11 Selector 2-12 Address Signal Line 2-13 Select Signal 2-100 Flip-flop 2-101 Logic Circuit 2-102, 2-103 Select Signal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38 G06F 9/30

Claims (2)

(57) [Claims] 1. A pipe for realizing a part of software instructions by a program consisting of a software instruction group stored in a main memory, prefetching instructions, and prefetching operands based on a result of decoding the prefetched instructions. In the preceding control device of the line-structured information processing device, if the prefetched instruction is an instruction realized by a program consisting of a software instruction group stored in the main memory, the instruction is stored in the main memory. A predecessor control device having an instruction decoder for outputting a start address of a main storage of a program comprising a group of software instructions. 2. The apparatus according to claim 1, further comprising means for starting prefetching of a next instruction based on a start address of a main memory output by the instruction decoding, following prefetching of operands of the fetched instruction. 2. The preceding control device according to 1.