JP2861379B2 - Image data encoding method and circuit thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

 The present invention relates to an image data encoding circuit.

Summary of the Invention

According to the present invention, in an image data encoding circuit, by transmitting, as an additional code, a median value of pixel data and data having a dynamic range of し た obtained by removing high-order bits, an additional code to be transmitted must be transmitted. The number of bits is reduced.

[Prior art]

As a highly efficient encoding method for video signals, the present inventors have
Adaptive dynamic range coding (hereinafter referred to as "ADRC method")
(December 11, 1986 IEICE presentation)
MR86-43). The ADRC method is an encoding method that utilizes a strong temporal and spatial correlation of a video signal. That is, when an image is divided into blocks, each block often has only a small dynamic range due to local correlation. Therefore, in the ADRC method, for example, as shown in FIG. 5, an image is divided into blocks, and a minimum value MIN and a dynamic range DR are obtained for each block. Then, for each block, each pixel data and the minimum value MI
A difference ΔD from N is obtained, and the difference ΔD is adaptively re-encoded to compress each pixel data into a smaller number of bits than the original number of bits. Then, the minimum value MIN and the dynamic range DR of each block are transmitted in units of blocks, and the re-encoded pixel data is transmitted in units of pixels. In this case, as a method of dividing the image into blocks, a method of dividing the image only in the horizontal direction (one-dimensional ADRC method), a method of dividing the image into horizontal and vertical rectangular regions (two-dimensional ADRC method), a spatial region covering a plurality of frames (3D ADRC method) has been proposed.
JP-A-61-144990, JP-A-62-92620, etc.). And in the three-dimensional ADRC method, 2
A motion between frames is detected, and pixel data of, for example, a subsequent block is not sent in a still block. In this method, 1-bit motion information data is required for each block. However, for a still block, 1/2 data compression can be performed. When a new number of bits is allocated for re-encoding, the number of bits is fixed in each block and the quantization step width is changed for each block according to the dynamic range (fixed-length ADRC method). Method to change the number of bits corresponding to the dynamic range for each and to keep the quantization step width constant (variable length ADRC
(Japanese Patent Application Laid-Open No. 61-147689, etc.). FIG. 6 shows an example of an encoding circuit using the fixed-length ADRC method. That is, the video signal is supplied to the A / D converter 12 through the input terminal 11 and A / D-converted into pixel data with a quantization bit number of, for example, 8 bits. This pixel data is supplied to the block division circuit 13 and It is divided into blocks for each two-dimensional area of 4 pixels × 4 lines. Then, the pixel data of each block is supplied to the maximum / minimum value detection circuit 14, and the maximum value MAX and the minimum value MIN of the pixel data of each block are detected. Then, the maximum value MAX and the minimum value MIN are supplied to the subtraction circuit 15 to calculate the dynamic range DR. The dynamic range DR and the minimum value MIN from the detection circuit 14 are supplied to the framing circuit 16. Further, the pixel data from the dividing circuit 13 is
Is supplied to a subtraction circuit 22 through a delay circuit 21 for compensating the time delay of the data, and the minimum value MIN from the detection circuit 14 is supplied to a subtraction circuit 22 to calculate difference data ΔD. DR is supplied to the adaptive encoder 23 and, for example, 4-bit pixel data DT
Are re-encoded (re-quantized), and the re-encoded pixel data DT is supplied to the framing circuit 16. Then, in the framing circuit 16, the minimum value MIN and the dynamic range DR for each block, and the re-encoded pixel data DT are combined into a signal of a predetermined format, and this signal is output to the image output terminal 17. The data is supplied to a transmission path (not shown) such as a file device. In the case of the variable length ADRC method, the dynamic range
The number of bits of the pixel data DT is changed in accordance with DR, and data indicating the number of bits is transmitted in block units. FIG. 7 shows an example of a decoding circuit based on the fixed-length ADRC method. That is, the signal from the transmission path is supplied to the frame decomposition circuit 32 through the input terminal 31 and is decomposed into the pixel data DT, the minimum value MIN, and the dynamic range DR, and the pixel data DT and the dynamic range DR are adaptive. decoder
33, the difference data ΔD is decoded, and this data ΔD is supplied to the addition circuit 34,
The minimum value MIN from 32 is supplied to the adding circuit 34 and
The bit pixel data is reproduced. Then, the pixel data is rearranged into pixel data in the order of the original time axis when supplied to the block decomposition circuit 35, and the rearranged pixel data is converted into a D / A converter 36.
The video signal is then D / A converted to the original video signal, and the video signal is taken out to the output terminal 37.

As described above, in the ADRC method, the minimum value MIN and the dynamic range DR are transmitted as an additional code for each block, but in the above case, the original video signal is When the data is A / D converted, the minimum value MIN and the dynamic range DR also become 8-bit data because they are quantized by 8 bits. Therefore, the minimum value MIN and the dynamic range DR
Therefore, it is necessary to transmit a total of 16 bits of data for each block. However, as described above, if the block size is 4 pixels × 4 lines and the number of bits of the re-encoded pixel data DT is 4 bits, the ratio of the additional code in one block is 16 bits / ( (4 pixels × 4 lines × 4 bits) = 25%, which is very large. Then, as the size of the block becomes smaller or the number of bits of the re-encoded pixel data DT becomes smaller, the ratio occupied by the additional codes becomes larger, and the compression ratio becomes lower. An object of the present invention is to reduce the number of bits of an additional code in the ADRC method.

[Means for Solving the Problems]

Now, assuming that A = (MAX + MIN) / 2 B = (MAX-MIN) / 2 as the values A and B as shown in FIG. That is, the value A is a median of the maximum value MAX and the minimum value MIN, and the value B is a half value of the dynamic range DR. When the maximum value MAX and the minimum value MIN are 8 bits, the sum (MAX + MIN) of these bits is 9 bits, but since the half thereof is the value A, the value A can be represented by 8 bits. it can. In addition, since 0 ≦ (MAX−MIN) ≦ 255, the relationship between the value A and the value B is established in the left column and the middle column of FIG. Then, if the value B is as large as the middle column, the value B can be represented by the number of bits as shown in the right column of FIG. The present invention reduces the number of bits when transmitting an additional code by focusing on the above points. That is, in the encoding circuit according to the present invention, when the maximum value MAX and the minimum value MIN are 8 bits, the value A is transmitted as 8 bits as an additional code, and the value B is transmitted as the value A.
Is transmitted in 0 to 7 bits corresponding to the size of. In the decoding circuit, the transmitted value B is 2
If it is multiplied, the dynamic range DR can be obtained, and if the difference (AB) between the values A and B is obtained, the minimum value MIN can be obtained.

[Action]

The number of bits of the additional code is changed according to the combination of the maximum value MAX and the minimum value MIN, and the number of transmitted bits is reduced by at least one bit for each block.

【Example】

FIG. 1 shows an example of an encoding circuit according to the present invention. The maximum value MAX and the minimum value MIN from the detection circuit 14 are supplied to an addition circuit 41 to extract a sum (MAX + MIN). The data A having the value A is supplied and taken out, and the data A is supplied to the framing circuit 16 as an additional code. Further, the maximum value MAX and the minimum value MIN from the detection circuit 14 are supplied to the subtraction circuit 43, and the dynamic range DR (= MAX−M
IN) is taken out, and the dynamic range DR is supplied to the dividing circuit 44 to take out the data B of the value B. Then, the data B is supplied to the conversion circuit 45, and the data A from the division circuit 42 is supplied to the conversion circuit 45. The number of bits from the data B corresponds to the size of the data A in FIG. Are compressed to the number of bits shown in FIG. in this case,
For example, B = “00000100” (= 4) B = “00000011” (= 3) B = “00000010” (= 2) B = “00000001” (= 1) Becomes smaller, the data B becomes “0” in the direction from the upper bit to the lower bit.
Since the number of bits increases (because they are arranged side by side), the higher-order “0” bit may be removed. Also, in this case,
Instead of using the value A, the higher-order "0" bits can be removed from the value B itself. Then, the compressed data B of this bit number is supplied to the framing circuit 16 as an additional code. Also, the re-encoded pixel data from the encoder 23
DT is also supplied to the framing circuit 16. Then, in the framing circuit 16, the data A and B for each block and the re-encoded pixel data DT for each pixel are combined into a signal of a predetermined format, and this signal is transmitted through the output terminal 17. Supplied to the road. FIG. 2 shows an example of a decoding circuit paired with the above-mentioned encoding circuit. That is, in FIG. 2, the data A, the data B, and the pixel data DT are separated and taken out from the frame decomposing circuit 32, and the data B is supplied to the multiplication circuit 51 and doubled, so that the dynamic range DR is obtained. It is said. And
This dynamic range DR is supplied to the decoder 33, and the pixel data DT from the frame decomposition circuit 32 is supplied to the encoder 33 to decode the difference data ΔD.
This data ΔD is supplied to the adding circuit 34. Further, the data A and B from the frame decomposition circuit 32 are supplied to the subtraction circuit 52 to extract the minimum value MIN, and the minimum value MIN is supplied to the addition circuit 34. Therefore, the original pixel data is extracted from the adding circuit 34, and this pixel data is
The video signal is sequentially supplied to the D / A converter 36 and the original video signal is taken out at a terminal 37.

【The invention's effect】

Thus, according to the present invention, the maximum value MAX and the minimum value M
Since the median value A of IN and the value B of 1/2 of the dynamic range DR are transmitted as additional codes, even if the minimum value MIN and the dynamic range DR are each 8 bits,
The number of bits of the additional code is only up to 15 bits,
Alternatively, it is reduced to 8 bits corresponding to the maximum value MAX and the minimum value MIN. Therefore, the ratio of the additional code to the data to be transmitted can be reduced. Moreover,
In that case, there is almost no deterioration in image quality due to compression of the number of bits of the additional code. Actually, the divisions of the division circuits 42 and 44 are performed by adding circuits.
It is only necessary to shift the data A and DR from the 41 and the subtraction circuit 43 rightward by one bit and supply them to the framing circuit 16 and the conversion circuit 45, and no specific components or circuits are required. Further, the multiplication of the multiplication circuit 51 is also performed by dividing the input data B by one.
What is necessary is just to shift the bit left and supply it to the decoder 33, and no specific parts or circuits are required.

[Brief description of the drawings]

1 is a system diagram showing an example of the present invention, FIG. 2 is a system diagram showing an example of a decoding circuit, FIG. 3 is a characteristic diagram for explaining the present invention, and FIG. 4 is a diagram for explaining the present invention. FIG. 5 is a diagram for explaining the ADRC method, and FIGS. 6 and 7 are system diagrams of a conventional example. 12; A / D converter 13; block division circuit 14; maximum / minimum value detection circuit 16; framing circuit 23; adaptive encoder 41; addition circuits 42 and 44; division circuit 43; subtraction circuit 45; conversion circuit

Claims (2)

(57) [Claims] 1. A digital video signal is decomposed into blocks for each predetermined number of pixel data, and the maximum value and the minimum value of the pixel data of the block are obtained for each block. A difference between the maximum value and the maximum value is obtained by re-encoding the difference into pixel data having a smaller number of bits than the number of bits of the pixel data corresponding to the dynamic range between the maximum value and the minimum value. Find the median value of the minimum value, find the value of 1/2 of the difference, remove the high-order "0" bits of this 1/2 value, and calculate the median value data and the "0" bit. An encoding method for outputting the removed data for each of the blocks and outputting the re-encoded pixel data. 2. A circuit for decomposing a digital video signal into blocks for each of a predetermined number of pixel data, a circuit for obtaining a maximum value and a minimum value of pixel data of the block for each block, the maximum value or the minimum value And a circuit for calculating a difference between the pixel data and a pixel data having a smaller number of bits than the number of bits of the pixel data corresponding to the dynamic range between the maximum value and the minimum value. A circuit that calculates a median between the maximum value and the minimum value; a circuit that calculates a half value of the difference; and a circuit that removes a high-order “0” bit of the half value An encoding circuit that outputs the median value data and the data from which the “0” bits have been removed for each block, and outputs the re-encoded image data.