JP2861373B2 - Apparatus and method for receiving encoded data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to decoding by orthogonal transform and encoding in which coefficient data generated by this encoding is quantized collectively for a plurality of blocks. The present invention relates to an apparatus and a method for receiving encoded data.

[Summary of the Invention]

According to the present invention, encoding is performed in which a digital image signal is blocked, and coefficient data obtained by orthogonally transforming the blocked digital image signal is quantized collectively for a plurality of blocks. In a receiving apparatus adapted to receive and decode, a decoding circuit for decoding quantized data by using an average value of original coefficient data represented by quantized data in a predetermined period as a decoding representative value, and a decoding circuit And a transform circuit for performing inverse orthogonal transform on the output coefficient data of (i).

[Conventional technology]

The present applicant has proposed an adaptive dynamic range coding (ADRC) as an encoding method for compressing the transmission data amount of image data.
g) is proposed. ADRC calculates a dynamic range, which is the difference between the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Laid-Open No. This is the encoding that performs the conversion. Further, as described in Japanese Patent Application Laid-Open No. 62-92620, an adaptive coding apparatus that performs coding adaptive to a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames is proposed. Have been. Further, as described in Japanese Patent Application Laid-Open No. 62-128621, a variable length encoding method in which the number of bits changes according to a dynamic range so that the maximum distortion generated when quantization is performed is constant. Proposed.

In these ADRCs, a code signal (quantization code) corresponding to each pixel included in a block and an additional code having the dynamic range information of the block, such as a minimum value MIN and a dynamic range DR, are generated. The code is transmitted. When transmitting the encoded data of ADRC, the data of one block is composed of the additional codes DR and MIN and the code signal of each pixel in the block. The length of the code signal of one block is constant when the number of allocated bits for quantization is fixed,
If this is variable, it is not constant.

Further, the applicant of the present application has proposed hybrid coding combining orthogonal transform coding such as cosine transform and the above-mentioned ADRC (Japanese Patent Application Nos. 62-270564 and 63-24).
No. 5227). In this hybrid coding, ADRC is applied by blocking each of the DC component coefficient data obtained by the cosine transform and the AC component coefficient data of the same order. Therefore, for each block of coefficient data,
An additional code of the dynamic range DR and the minimum value MIN is generated. The encoding is different between the DC component coefficient data and the AC component coefficient data. That is, the coefficient data of the DC component is coded in the same manner as ADRC, and the coefficient data of the AC component determines the number of bits to be allocated for quantization in accordance with the dynamic range DR, and the minimum value MIN is regarded as 0. , And the bit number data indicating the allocated bit number and the code signal are transmitted. A proposal on compression of additional codes in such hybrid coding has been made by the present applicant (see Japanese Patent Application No. 2-10364).

A decoding device that receives coded data generated by hybrid coding including such DCT and ADRC is configured to perform decoding on each of a DC component and an AC component. For the DC component, decoding is performed using the dynamic range DR, the minimum value MIN, and the code signal obtained by quantizing the coefficient data. The AC component is decoded using the bit number data, the quantization code, and the quantization table. For example, when the existence range of the coefficient data obtained from the quantization code and the table is 10 to 20, the decoding side decodes the quantization code using the median value of 15.

[Problems to be solved by the invention]

By the way, coefficient data generated by DCT tends to be strongly concentrated on 0 for any order component, as shown in FIG. In such a distribution, 10 and
If the average value of the coefficient between 20 is found, that value is almost certainly less than 15. Further, the difference between the average value and the median value often becomes considerably large depending on the component. Therefore, the receiving device that always decodes the median of the existence range as the decoding representative value is not optimal.

Accordingly, an object of the present invention is to provide an encoded data receiving apparatus and method capable of implementing encoding with less quantization distortion.

[Means for solving the problem]

According to the present invention, encoding is performed in which a digital image signal is blocked, and coefficient data obtained by orthogonally transforming the blocked digital image signal is quantized collectively for a plurality of blocks. In the receiving device configured to receive and decode, decoding means (41a, 41b, 41c, 46) and a transforming means (48) for inversely transforming coefficient data output from the decoding means (41a, 41b, 41c, 46). is there. The present invention is also a receiving method for decoding received data in this way.

[Action]

An average value of coefficient data for a predetermined period, for example, one frame period, is obtained on the encoder side, and the average value is transmitted.
The average value is calculated for each order of the coefficient data for each quantization table used. Therefore, by using the average value as the decoded value, the quantization distortion can be reduced as compared with the method of always using the median value as the decoded value.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1 showing the configuration on the encoder side,
A digital video signal in which one sample is digitized to 8 bits is supplied to an input terminal indicated by 1. This digital video signal is supplied to the blocking circuit 2, and the order of the input digital video signal is changed to a block configuration for cosine conversion. For example, an image of one frame is divided into (4 × 4) small blocks.

The output signal of the blocking circuit 2 is supplied to a cosine transform circuit 3, where the cosine transform circuit 3 performs a two-dimensional cosine transform. From the cosine transform circuit 3, a (4 × 4) coefficient table corresponding to the block size of the cosine transform is obtained. Of course, the size of the cosine transform block is not limited to this. FIG. 2A shows a (4 × 4) coefficient table obtained from the cosine transform circuit 3. In FIG. 2A, DC indicates a DC component, AC1, AC
2,..., AC15 indicates an AC component. The coefficient table is
Starting from the DC component, the data is transmitted in a sequence in which each coefficient data is arranged in the order of zigzag traveling.

In the two-dimensional cosine transform, the sampled discrete image signal f (j, k) is subjected to processing represented by the following equation by the cosine transform circuit 3. However, as for the original data, one block has two-dimensional data f (j, k) (j, k = 0,
1, ..., N-1).

The coefficient data from the cosine transform circuit 3 is supplied to the hybrid blocking circuit 4. As shown in FIG. 2B, the hybrid blocking circuit 4 includes (4 × 4 = 16) DCT coefficient blocks (DCT1, DCT2,..., DCT16).
To form a hybrid block. Output data from the hybrid blocking circuit 4 is DC (DC
T1), DC (DCT2), ..., DC (DCT16), AC1 (DCT
1), AC1 (DCT2), AC1 (DCT16), AC2 (DCT)
1), ..., AC2 (DCT16), AC3 (DCT1), ..., AC
14 (DCT16), AC15 (DCT1),..., AC15 (DCT16). That is, the same components are collected. Output data of the hybrid blocking circuit 4 is supplied to an absolute value conversion circuit 5 and a timing generation circuit 6, respectively.

The AC coefficient data from the absolute value conversion circuit 5 is supplied to the average value detection circuit 7 and the switch circuit 8, respectively. The switch circuit 8 is switched by a timing pulse T1 from the timing generation circuit 6. In this embodiment, the coefficient data of the AC component is divided into three groups, and different quantization tables are used for each group.

That is, as shown by a broken line in FIG.
The AC component data in the (4 × 4) coefficient data is the first
Group using the quantization table of (AC1, AC2, AC3, A
C4, AC5), a group using the second quantization table (AC6, AC7, AC8, AC9, AC10), and a group using the third quantization table (AC11, AC12, AC13, AC14, AC15).
And divided into The reason why the different quantization tables are used in this way is to make the width of the quantization step different according to the degree of the order and to perform good quantization. From the output terminal a of the switch circuit 8, coefficient data to be quantized by the first quantization table is extracted. From the output terminal b and the output terminal c of the switch circuit 8, coefficient data to be quantized by the second quantization table and the third quantization table, respectively, is extracted.

Although not shown, the coefficient data DC of the DC component is subjected to ADRC encoding separately from the AC component in the same manner as the previously proposed method. That is, the maximum value MAX and the minimum value MIN of the coefficient data of the 16 DC components included in the hybrid block are detected, and the dynamic range DR, which is the difference between them, is obtained.The dynamic range DR is adapted to the dynamic range DR. The coefficient data is quantized.

The output terminal a of the switch circuit 8 is connected to a quantization circuit 9a and a maximum value detection circuit 11a. The other output terminals b and c have quantization circuits 9b and 9c and a maximum value detection circuit 11 respectively.
b and 11c are respectively connected. Quantization tables 10a, 10b, and 10c are provided in association with the quantization circuits 9a, 9b, and 9c, respectively. As shown in FIG. 4, for example, the quantization table 10a shows the correspondence between the range of absolute coefficient data and the output value of quantization. The quantized outputs are 1, 2,
3,... Are integer values in ascending order. The quantization circuit 9a generates a quantization output corresponding to the input data with reference to the quantization table 10a. The other quantization circuits 9b and 9c and the quantization tables 10b and 10c perform quantization in the same manner as the quantization circuit 9a and the quantization table 10a. Quantization circuit 9
The outputs of b and 9c are also integer values in ascending order of 1, 2, 3,.... However, between the quantization tables 10a, 10b, and 10c,
The range of absolute values corresponding to each of the integer values is different.

The maximum value detection circuits 11a, 11b, 11c detect the maximum value during a predetermined period (for example, within one frame period) in the coefficient data divided into groups. The timing pulse T2 from the timing generation circuit 6 resets the maximum value detection circuits 11a, 11b, and 11c every time the maximum value is detected. The detected maximum value is the number of bits determination circuit 13a, 13b, 13
c respectively. Bit number determination circuits 13a, 13b, 1
3c converts the maximum value of the absolute value of the detected coefficient data into a quantized output by using quantization tables 10a, 10b,
See 10c. For example, when the maximum detected quantization output is 3, the bit number determination circuit 13a determines 2 bits as the number of allocated bits.

The outputs of the bit number determination circuits 13a, 13b, 13c are supplied to the input terminal of the switch circuit 14 and the encoding circuits 12a, 12b, 12c, respectively. Output signals of the quantization circuits 9a, 9b, 9c are supplied to the encoding circuits 12a, 12b, 12c, respectively. As in the above example, when the number of bits is 2 bits, the quantized output (integer value) of the coefficient data of the first group is (00, 01,
The data is encoded by the encoding circuit 12a into any one of (10) and (11).

Output data of the encoding circuits 12a, 12b, and 12c are supplied to input terminals of the switch circuit 14, respectively. Switch circuit 14
Is controlled by the timing pulse T1 from the timing generation circuit 6, and is switched according to the group for each quantization table used. At one output terminal 15 of the switch circuit 14, bit number data indicating the number of bits of each group is extracted, and at the other output terminal 16, a quantization code of each group is extracted.

The average value detection circuit 7 is supplied with output signals of the quantization circuits 9a, 9b and 9c together with coefficient data. The average value detection circuit 7 detects an average value of one frame period for each of the first, second, and third groups.

FIG. 5 shows an example of a circuit forming a part of the average value detection circuit 7 and forming an average value of the coefficient data of the first group. This average value detection circuit has a memory 21 for storing the absolute value of coefficient data, and a memory 22 for detecting the frequency of each quantized output in one frame period and storing the frequency. These memories 21 and 22 are cleared by a frame cycle pulse from an input terminal indicated by 23. The address for the memory 21 is supplied via a switch circuit 24, and the address for the memory 22 is supplied via a switch circuit 25.

From an input terminal indicated by reference numeral 26, coefficient data from the absolute value conversion circuit 5 is supplied to the first group,
Given to 27. This addition circuit 27 includes a switch circuit 28
The read output of the memory 21 is supplied via the. The output of the adding circuit 27 is written to the memory 21.

One input terminal of the switch circuit 24 of the memory 21 is supplied with a quantized output from the quantizing circuit 9a associated with the table 10a. Therefore, the absolute value of the coefficient data is written to the address corresponding to the integer value of the quantized output. This operation is performed during a period in which valid data of one frame period exists. In this valid data period, the switch circuit
28 is on. Therefore, at the end of the valid data period, the accumulated value of the coefficient data before quantization is stored in the address corresponding to each quantized output.

The quantization output of the quantization circuit 9a is also supplied to one input terminal of the switch circuit 25 of the memory 22. The read output of the memory 22 is supplied to the adder circuit 29, and the adder circuit 29 adds 1 to the read output. The output signal of the adding circuit 29 is written to the memory 22 via the switch circuit 30. Therefore, by using the value of the quantized output as an address, at the end of the valid data period of one frame period, each address corresponding to the quantized output of the memory 22 includes:
The cumulative value of the frequency of occurrence for one frame period is stored.

In the data absence period after the valid data period in one frame period, the switch circuits 24 and 25 are switched, and the sequential address from the address generation circuit 31 is stored in the memory 21 and
22 and the memories 21 and 22 perform a read operation. Further, the switch circuits 28 and 30 are turned off. In order from the quantization output value 1 in the first table,
The addresses are changed to 2, 3,... The read outputs of the memories 21 and 22 are supplied to a division circuit 32,
(Ie, the cumulative value of the quantized output 1) is divided by the read output of the memory 22 (ie, its cumulative frequency). Therefore, at the output terminal 33 of the dividing circuit 32, an average value relating to the quantized output 1 of the first table is generated. Similarly, an output terminal 33 outputs another integer value 2,
An average value is generated for each of 3,.

For each of the second and third tables, the fifth
An average value detection circuit similar to that shown in the figure is provided, and an average value for each quantized output value of each table is detected. At the end of one frame period, the average value detection operation has been completed, and the contents of the memories 21 and 22 are cleared.

The encoder generates bit number data indicating the number of quantization bits, quantization code, and average value data for each integer value in the table for the coefficient data of the AC component. An encoded output relating to the coefficient data of the AC component and an encoded output relating to the DC component, that is, the additional code and the quantization code are transmitted.

Next, an example of the decoder will be described with reference to FIG. FIG. 6 shows only the configuration for the AC component, and omits the DC component. The DC component is decoded in the same way as a normal ADRC.

The received average data is stored in tables 41a, 41b and
41c. Therefore, the table 41a stores an average value as a decoded value corresponding to each of the integer values 1, 2, 3,... Of the quantized output.
This decoding table is updated every frame period. Further, the bit number data received from the input terminal 42 and the quantization code received from the input terminal 43 are supplied to the frame delay circuit 44. As described above, since the average value data is transmitted during the data absence period after the data valid period, the frame delay circuit 44 adjusts the timing between the bit number data, the quantization code, and the average value data. If the encoder side is controlled and the average value data is transmitted prior to the quantization code,
The frame delay circuit 44 can be omitted.

The bit number data and the quantization code from the frame delay circuit 44 are supplied to the cutout circuit 45. Cutout circuit
Numeral 45 divides a quantization code by bit number data. Each quantization code of the coefficient data from the cutout circuit 45 is supplied to the decoder 46. Tables 41a, 41b, and 41c are connected to the decoder 46, and the quantization code is converted into a decoded value (that is, an average value) based on its own table.

The decoded value from the decoder 46 is supplied to the hybrid block decomposition circuit 47. Hybrid block decomposition circuit 47
Is supplied to the inverse cosine transform circuit 48. The hybrid block decomposition circuit 47 converts the configuration of the hybrid block into a DCT coefficient block, as opposed to the hybrid block generation circuit 4 on the encoder side. The inverse cosine transform circuit 48 obtains a decoded value of (4 × 4) pixels in the DCT block. The decoded value from the inverse cosine transform circuit 48 is supplied to the block decomposing circuit 49, and the beginning of the (4 × 4) block is converted into decoded data in the raster scan order. Therefore, decoded data is obtained at the output terminal 50.

In the above-described embodiment of the present invention, since the average value is formed for each quantization table to be used, the quantization distortion can be reduced as compared with the case where the median value of the quantization range is simply used as the decoded value. . A simple example illustrates this effect. When performing quantization using the first table (see FIG. 4),
Assuming that the absolute value of the coefficient data is (2, 4, 16, 14, 40, 42), the quantized output is (1, 1, 2, 2, 3, 3), which is coded by 2 bits. Transmitted. In the method that does not transmit the average value, the median value of each existence range, that is, (5, 5, 12, 12, 35, 35) is formed as a decoded output.

On the other hand, in one embodiment of the present invention, the average value (3, 15, 4
1), and the resulting decoded value is
(3, 3, 15, 15, 41, 41). Therefore, the quantization distortion can be made extremely small as compared with the method using no average value.

Instead of forming an average value for each quantization table, an average value of coefficient data of the same order generated by cosine transform may be obtained. In the example of a (4 × 4) block, 15
An average value is obtained for each of the coefficients. In this method, fine quantization suitable for the distribution of each coefficient can be performed. However, there is a problem that the amount of average value data to be transmitted increases.

Further, the average value may be transmitted only when the difference between the average value and the median value is large.

Further, for a large number of images, a general quantization table or an average value of each coefficient data is obtained in advance by using a computer, and the general average value is stored in a memory on the decoder side. A suitable average value may be used. This method has the advantage that it is not necessary to transmit the average value data at all.

In the present invention, an orthogonal transform code other than the cosine transform may be used. Further, block coding other than ADRC may be used.

〔The invention's effect〕

According to the present invention, when the coefficient data of the AC component generated by the orthogonal transform coding is compressed and transmitted, the decoded value is obtained by using the average value, so that the quantization of the decoded value of the coefficient data of the AC component is performed. Distortion can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an encoding encoder to which the present invention can be applied, FIG. 2 is a schematic diagram showing an example of a DCT block and a hybrid block, and FIG. 3 is a schematic diagram showing division of a quantization table to be used. FIG. 4 is a schematic diagram illustrating an example of a quantization table; FIG. 5 is a block diagram of an example of an average value detection circuit; FIG. 6 is an example of a decoder to which the present invention is applied; FIG. 7 is a block diagram for explaining the distribution of DCT coefficient data. Explanation of main symbols in the drawings 2: blocking circuit, 3: cosine transform circuit, 7: average value detection circuit, 9a, 9b, 9c: quantization circuit, 10a, 10b, 10c: quantization table, 41a, 41b, 41c: decoding table, 46: decoder, 48: inverse cosine transform circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 7/24-7/68 H04N 1/41-1/419

Claims (2)

(57) [Claims] 1. A digital image signal is encoded into blocks, and coefficient data obtained by orthogonally transforming the block-formed digital image signals are quantized collectively for a plurality of blocks. In a receiving apparatus adapted to receive and decode data, decoding means for decoding the quantized data using, as a decoding representative value, average value data of original coefficient data expressed by the quantized data in a predetermined period. And a transforming means for performing inverse orthogonal transform on coefficient data output from the decoding means. A receiving apparatus for encoded data, comprising: 2. A digital image signal is encoded into blocks, and coefficient data obtained by orthogonally transforming the blocked digital image signals are quantized collectively for a plurality of blocks. A receiving method adapted to receive and decode the data, a step of decoding the quantized data using, as a decoding representative value, average value data of the original coefficient data represented by the quantized data in a predetermined period; And a step of performing an inverse orthogonal transform on the coefficient data output from the decoding means.