JP2831522B2 - LSI test data generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LS for supporting the creation of test data used in a test process in LSI manufacturing.
The present invention relates to an I test data generation device.

[0002]

FIG. 8 is a conceptual diagram showing a conventional LSI test data generating apparatus.

In FIG. 8, reference numeral 51 denotes a logic circuit design editor for creating logic circuit diagram data for a test target LSI, 52 denotes LSI input signal data, and 53 denotes a test target LSI prepared by the logic circuit design editor 51.
Is a logic simulator; 54 is LSI output signal data output from the LSI to be tested; 56 is a tester input data converter for converting LSI output signal data to tester input signal data; 57 is tester input data Tester input signal data converted by the conversion unit 56, output signal expected value data in the tester for the test target LSI 58, and a tester 59 for testing the test target LSI.

Next, the operation will be described.

In this LSI test data generator, a simulation is performed using a logic simulator 54 based on logic circuit diagram data 53 created by a logic circuit design editor 51.

In this simulation, LSI output signal data when the LSI input signal data 52 is given to a logic circuit represented by logic circuit diagram data 53 is created.

Next, a tester input data converter 56 creates tester input signal data from the LSI input signal data 52, and creates tester output signal expected value data 58 from the LSI output signal data. The tester input signal data 57 and the tester output signal expected value data 58 are supplied to a tester 59.

[0008]

A conventional LSI test data generating apparatus is configured as described above, and generates LSI test data by focusing on an LSI input signal and an LSI output signal of an LSI to be tested. And LS
While there is a demand for an LSI test data generation apparatus capable of generating LSI test data capable of detecting short-circuit faults between adjacent wirings inside an LSI that frequently occurs in the course of manufacturing, the conventional LSI test data generation The device cannot create LSI test data for the purpose of detecting short-circuit faults between adjacent wires, and short-circuit faults between adjacent wires cannot be easily detected by conventional LSI test data inside the LSI. There was a point.

SUMMARY OF THE INVENTION An object of the present invention is to provide an LSI test data generation device capable of generating LSI test data for detecting a short circuit fault between adjacent wirings inside an LSI. The aim is to obtain a device.

According to a second aspect of the present invention, an LSI test data for detecting a short-circuit fault between adjacent wirings within an LSI can be created by tracing logic from the adjacent wiring portion in an input direction and an output direction. An object is to obtain a test data generation device.

[0011]

According to the present invention, L
The SI test data generation device extracts adjacent wiring data between signal lines wired at a wiring interval smaller than a predetermined minimum wiring interval, and performs LSI on the extracted adjacent wiring data.
Based on the LSI output signal data obtained by performing a simulation using the logic design data and the LSI input signal data, the signal values between the signal lines wired at wiring intervals smaller than the predetermined minimum wiring interval are mutually determined. An input signal data converting means for judging states of different values and converting the LSI input signal data to the LSI output signal data to the LSI output signal data when the values are different from each other; Output signal data converting means for converting the LSI output signal data into expected value data for LSI tester input.

An LSI test data generating apparatus according to a second aspect of the present invention sets a signal value on an adjacent wiring so that a signal value between adjacent wirings has a different value, and sets the signal value between the adjacent wirings. A tester input data detecting means for obtaining LSI tester input data by tracing the logic from the adjacent wiring to the input side so as to obtain the set signal value, and setting the signal value between the adjacent wirings to the set signal value. By tracing from the adjacent wiring to the output side, LSI
Tester expected value data detecting means for obtaining tester expected value data.

[0013]

According to the first aspect of the present invention, an LSI test data generating apparatus is provided for generating LSI logic design data and an LSI input signal with respect to adjacent wiring data between signal lines wired at wiring intervals smaller than a predetermined minimum wiring interval. A simulation is performed with the data, and based on the LSI output signal data obtained by the simulation, the signal values between the signal lines wired with a smaller wiring interval than the predetermined minimum wiring interval are different from each other. The LSI output signal data and the LSI input signal data corresponding to the LSI output signal data and the expected value data for the LSI tester input, respectively, are determined when it is determined that the values have different values. By converting the test data into LSI test data.

According to the second aspect of the present invention, the LSI test data generating apparatus sets different signal values on adjacent signal lines, and traces logic from the signal line on which the different signal values are set to the input side and the output side, L such that the signal value between the adjacent signal lines becomes the different signal value set above.
The input data for the SI tester and the expected value data for the LSI tester are created.

[0015]

【Example】

Embodiment 1 An embodiment of the first aspect of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram showing a configuration of an LSI test data generation device of this embodiment.

In FIG. 1, reference numeral 1 denotes a logic circuit design circuit editor for creating logic drawing data 3; and 4, a logic simulator for creating LSI output signal data 5 from the LSI input signal data 2 and the logic drawing data 3.

Reference numeral 6 denotes a layout editor for creating layout drawing data 7, 8 denotes minimum wiring interval data between adjacent wirings, and 9 denotes an adjacent wiring for generating adjacent signal line data 10 from the minimum wiring interval data 8 and the layout drawing data 7. It is a data extraction unit. The adjacent wiring data extraction unit 9 describes a signal value for each adjacent signal line pair. Reference numeral 11 denotes a signal line data extraction unit that creates tester input signal data 12 and tester output signal expected value data 13 from the adjacent signal line data 10, LSI output signal data 5, and LSI input signal data 2, and 14 denotes an LSI to be tested. Is a tester that tests against

FIG. 2 is an example of layout drawing data 7 created by the layout editor 6, and is a wiring layout diagram.

In FIG. 2, reference numeral 15 denotes a wiring layout of the signal line A, 16 denotes a wiring layout of the signal line B, and L denotes a wiring interval distance between the signal line A and the signal line B.

FIG. 3 shows a simulation result of the LSI under test on the adjacent wiring A and wiring B shown in FIG. 2 by the logic simulator 4. FIG. 3A shows a signal waveform on the signal line A by simulation. FIG.
(B) is a signal waveform on the signal line B by simulation, and (c) of FIG. 3 is a signal waveform showing an exclusive OR operation result of the signal waveform on the signal line A and the signal waveform on the signal line B. , T indicate portions where the signal waveform of the signal line A is different from the signal waveform of the signal line B.

Next, the operation will be described with reference to FIG.

FIG. 4 is a flowchart for explaining the operation of the LSI test data generation apparatus. First, logic drawing data 3 of the LSI is created by logic circuit design (step ST1).

Next, layout drawing data 7 is created from a layout design performed by the layout editor 6 (step ST2).

Further, LSI output signal data 5 is created from the LSI input signal data 2 and the logic drawing data 3 by the logic simulator 4 (step ST3), and the created L
The SI output signal data 5 is stored (step ST4).

Next, adjacent wiring data 10 having a specified wiring interval or less is created and extracted from the layout drawing data 7 and the minimum wiring interval data 8 (step ST5).

Here, the signal line data extraction unit 11 searches the LSI output signal data 5 for a case where the signal value differs for each adjacent signal line pair described in the adjacent signal line data 10 that is shorter than the specified wiring interval. (Step ST6, Step S
T7, step ST8), find the LSI input signal value and the LSI output signal value corresponding to the adjacent signal line pair when the signal values are different, convert these LSI input signal value and the LSI output signal value into LSI tester input data, The tester input signal data 12 and the tester output signal expected value 13 are created (step ST9).

Embodiment 2 Hereinafter, an embodiment of the second aspect of the present invention will be described with reference to the drawings. FIG. 5 is a conceptual diagram showing the configuration of the LSI test data generation device of this embodiment.

In FIG. 5, parts that are the same as or correspond to those in FIG. 1 are given the same reference numerals, and descriptions thereof will be omitted.

In FIG. 5, reference numeral 26 denotes adjacent signal line data 1
A signal value setting unit that sets different signal values to adjacent signal lines of the logic drawing data 3 based on 0. A signal value setting unit 26 traces logic in the input direction from the adjacent signal lines set with different signal values by the signal value setting unit 26. A logic tracing section 28 in the input direction for tracing the logic is a logic tracing section in the output direction for tracing the logic from the adjacent signal line to which different signal values are set by the signal value setting section 26 in the output direction.

FIG. 6 shows a logic trace section 27 in the input direction.
FIG. 7 is an explanatory diagram for explaining an operation of a logical trace in the logical trace unit 28 in the output trace direction.

In FIG. 6, reference numeral 31 denotes an example of the LSI logic circuit in the logic drawing data 3, and the signal lines C and D are adjacent signal lines in the layout design.

Next, the operation will be described.

First, in the signal value setting section 26, a portion where the signal line in the layout design shown in FIG. 6 is adjacent is obtained from the adjacent signal line data 10 and the logical drawing data 3, and the adjacent portion is determined. When the signal value of the signal line C is "1" for the signal lines C and D, different signal values are set to the signal line D such as the signal value "0".

Next, based on the signal value set in the signal value setting section 26, the logic tracing section 27 in the input direction traces and traces the logic in the LSI input direction from the position where the line is adjacent to the logic line. The signal value is obtained, and finally the tester input signal data 12 is automatically obtained.

Further, the signal value setting section 26 is provided by a logic tracing section 28 in the output direction from the place where the line numbers are adjacent.
Finally, the tester output signal expected value data 13 is automatically obtained by sequentially obtaining signal values by tracing and tracing the logic in the LSI output direction based on the signal values set in (1).

Embodiment 3 Hereinafter, an embodiment of the third aspect of the present invention will be described with reference to the drawings.

FIG. 7 shows an LS according to another embodiment of the present invention.
FIG. 2 is a conceptual diagram illustrating a configuration of an I test data generation device.

7, parts that are the same as or correspond to those in FIG. 5 are given the same reference numerals, and descriptions thereof will be omitted.

In FIG. 7, reference numeral 33 denotes power / ground wiring data describing power wiring and power ground wiring data;
Reference numeral 34 denotes a power supply / power source for generating and extracting the power supply wiring and the adjacent wiring data 10 of the signal line adjacent to the power supply ground wiring from the layout drawing data 7, the power supply / ground wiring data 33, and the minimum wiring interval data 8 prepared by the layout editor 6.
The ground adjacent wiring extraction unit 35 sets a signal value “0” for a signal line adjacent to the power supply wiring, and sets a signal value “1” for a signal line adjacent to the ground wiring. It is a value setting section.

Next, the operation will be described.

First, the power / ground adjacent wiring extraction unit 34
Then, the adjacent wiring data 10 for the signal line adjacent to the power wiring and the power ground wiring is obtained from the layout drawing data 7 using the power / ground wiring data 33 and the minimum wiring interval data 8.

Next, the signal value "0" is set to the signal line adjacent to the power supply line by the power / ground signal value setting unit 35, and the signal value "1" is set to the signal line adjacent to the power supply ground line. I do.

Further, a logic tracing unit 27 in the input direction
Thus, by sequentially tracing and tracing the logic in the LSI input direction from the signal line portion adjacent to the power supply wiring and the power supply ground wiring to sequentially obtain the signal value, the tester input signal data 12 is automatically obtained finally.

The logic tracing unit 28 in the output direction performs logic in the LSI output direction based on the signal value set in the signal value setting unit 26 from the signal line location adjacent to the power supply wiring and the power supply ground wiring. By sequentially obtaining signal values by tracing and tracing, finally, the tester output signal expected value data 13 is automatically obtained.

[0045]

As described above, according to the first aspect of the present invention,
Based on the LSI output signal data obtained by performing the simulation, it is determined whether the signal values between the signal lines wired at a wiring interval smaller than a predetermined minimum wiring interval are different from each other, and different values are determined. Input signal data conversion means for converting the LSI input signal data corresponding to the LSI output signal data to the LSI tester input data, and further converting the LSI output signal data when the values differ from each other to the expected value data for the LSI tester input The output signal data conversion means for converting the data to the output signal data has the effect that LSI test data for detecting a short circuit failure between adjacent wirings inside the LSI without omission can be easily created.

According to the second aspect of the present invention, the signal values between the adjacent wires are set to be different from each other, and between the adjacent wires, the signal value is set from the adjacent wire to the input side so as to have the set signal value. A tester input data detecting means for obtaining input data for an LSI tester by tracing logic, and an output side from the adjacent wiring so that a signal value between the adjacent wirings becomes a signal value of the set different value. Tester expected value data detecting means for obtaining LSI tester expected value data by following the logic
This has the effect of easily creating LSI test data for reliably and without fail detecting a short circuit failure between adjacent wirings inside the SI.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an LSI test data generation device according to an embodiment of the present invention.

FIG. 2 is a wiring layout diagram showing an example of layout drawing data of an LSI test data generation device according to an embodiment of the present invention;

FIG. 3 is a waveform chart showing signal waveforms of adjacent wirings, which are simulation results in the LSI test data generation device according to one embodiment of the present invention;

FIG. 4 is a flowchart showing the operation of the LSI test data generation device according to one embodiment of the present invention;

FIG. 5 is a conceptual diagram showing an LSI test data generation device according to an embodiment of the present invention.

FIG. 6 is an explanatory diagram for explaining an operation of a logic trace in the LSI test data generating device according to one embodiment of the second invention;

FIG. 7 is a conceptual diagram showing an LSI test data generation device according to another embodiment of the present invention.

FIG. 8 is a conceptual diagram showing a conventional LSI test data generation device.

[Explanation of symbols]

2 LSI input signal data 3 Logic drawing data (LSI logic design data) 4 Logic simulator (LSI output signal generating means) 5 LSI output signal data 7 Layout drawing data (LSI layout design data) 9 Adjacent wiring data extraction unit (Adjacent wiring data Extraction means) 10 adjacent signal line data (adjacent wiring data) 11 signal line data extraction unit (signal value difference state determination means,
Input signal data conversion means, output signal data conversion means) 26 signal value setting section (signal value setting means) 27 logic trace section in input direction (input data detection means for tester) 28 logic trace section in output direction (for tester Expected value data detection means)

Claims (2)

(57) [Claims] 1. An adjacent wiring data between signal lines wired at a wiring interval smaller than a predetermined minimum wiring interval is set to an LSI.
Adjacent wiring data extraction means for extracting from the layout design data, and LSI output signal data obtained by performing a simulation on the adjacent wiring data extracted by the adjacent wiring data extraction means based on the LSI logic design data and the LSI input signal data LSI output signal generating means and LSI obtained by the LSI output signal generating means
Signal value difference state determination means for determining a state in which signal values between signal lines wired at wiring intervals smaller than the predetermined minimum wiring interval are different from each other based on output signal data; Input signal data conversion means for converting LSI input signal data corresponding to the LSI output signal data to LSI tester input data when the value difference state determination means determines that the values differ from each other; and the signal value difference state determination. An output signal data conversion unit for converting the LSI output signal data into expected value data for input to an LSI tester when it is determined by the means that the values are different from each other. 2. The method according to claim 1, wherein adjacent wiring data between signal lines wired at a wiring interval smaller than a predetermined minimum wiring interval is stored in an LSI.
An adjacent wiring data extracting means for extracting from the layout design data, and a signal value in the adjacent wiring set from the adjacent wiring data extracted by the adjacent wiring data extracting means so that a signal value between the adjacent wirings becomes a different value. And a tester input data detecting means for obtaining input data for an LSI tester by tracing logic to an input side so that the signal value between the adjacent wirings becomes the signal value set by the signal value setting means. And tester expected value data detection means for obtaining expected value data for an LSI tester by tracing logic to an output side so that the signal value between the adjacent wirings becomes the signal value set by the signal value setting means. LSI test data generation device.