JP2817718B2 - Tunnel transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor utilizing a tunnel phenomenon, which can be highly integrated, operate at high speed, and have multiple functions.

[0002]

2. Description of the Related Art A tunnel transistor is known as a multifunctional transistor utilizing a tunnel phenomenon at a p ⁺ -n ^- junction on a semiconductor surface. The present applicant has proposed, for example, in Japanese Patent Application No. Hei 6-339126, a tunnel transistor which can constitute a functional circuit with a small number of elements and enables high integration. The structure and operation of the tunnel transistor will be briefly described based on the structure diagram.

FIG. 3 is a schematic structural view showing an example of a tunnel transistor described in Japanese Patent Application No. 6-339126. The tunnel transistor is semi-insulating GaAs semiconductor substrate 1, the buffer layer 2 i-Al _0.5 Ga _0.5 As layer (abbreviation i here means a non-doped semiconductor that can be regarded as intrinsic or substantially intrinsic. Forth.) , Buffer layer 13
The p ⁺ -Ga degenerated into the i-GaAs layer and the drain layer 4
As layer, n ⁺ -GaAs layer degenerate source layer 5, n ⁺ -GaAs layer degenerated to the channel layer 6, the gate insulating layer 7
I-Al _0.5 Ga _0.5 As, an Al film on the gate electrode 8, an AuZn / Au film on the drain electrode 9, and an A film on the source electrode 10.
It is configured using a uGe / Au film.

In order to operate this transistor, the source electrode 10 is set to the ground potential, and a voltage is applied between the source and the drain. Since both the source region 5 and the channel layer 6 have the same conductivity type, they are completely conducting.
On the other hand, a junction (tunnel junction) similar to an Ezaki diode (tunnel diode) is formed between the channel layer 6 and the drain region 4, and as a result, a current (tunnel current) flows between the source and the drain due to a tunnel effect. In particular, when a positive voltage is applied to the drain electrode 9, the Esaki diode becomes forward-biased, and a differential negative resistance appears in the current-voltage characteristics. Since the magnitude of the tunnel current depends on the concentration of electrons induced in the channel, the negative resistance is controlled by the voltage applied to the gate electrode, so that the operation of the transistor having various functions can be obtained.

[0005] To increase the tunnel current density, it is necessary to increase the amount of impurities added to the channel region or the drain region. However, the upper limit of the impurity concentration is limited by the crystallinity and the solid solution limit. In some cases, it was not possible.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a tunnel transistor which can operate at a higher current density.

[0007]

According to the present invention, there is provided a semiconductor substrate having a drain layer of a first conductivity type semiconductor, a source layer of a second conductivity type semiconductor, and a channel layer of a second conductivity type semiconductor. In a tunnel transistor in which a layer and a channel layer form an interband tunneling junction, a semiconductor layer having a p-type conductivity of either the drain layer or the channel layer (hereinafter, referred to as a p-type conductivity type layer). Alternatively, the present invention relates to a tunnel transistor provided with a layer having a tensile stress with respect to at least one of the lower surfaces (hereinafter, referred to as a tensile stress layer).

In the tunnel transistor having a pn junction band-to-band tunneling junction according to the present invention, the semiconductor layer (p-type conductivity type layer) of the pn junction exhibiting the p-type conductivity is:
It is in a distorted state under a tensile stress from the lower or upper layer.

When a tensile strain is applied to the p-type conductivity type layer, the energy edge of the valence band based on light holes decreases, and the concentration of light holes increases. Since the smaller the reduced effective mass obtained from the effective mass of electrons and holes, the larger the interband tunnel current, the tunnel current increases with a light increase in hole concentration.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The tensile stress layer of the present invention can be formed of various materials capable of applying tensile strain to a p-type conductivity type layer. For example, an oxide layer such as SiO ₂ can be used for a p-type conductivity type layer of Si.

However, it is particularly preferable that the tensile stress layer is formed of a semiconductor having a lattice constant larger than the lattice constant of the p-type conductivity type layer.

In this case, the lattice constant of the tensile stress layer and p
If the difference between the lattice constants of the p-type conductivity type layers is too small, the tensile strain inside the p-type conductivity type layer is too small and the light hole concentration is not sufficient, and if it is too large, good quality crystals cannot be obtained.
The value of “(lattice constant of tensile stress layer−lattice constant of p-type conductivity type layer) / lattice constant of p-type conductivity type layer” is usually 0.2 to
It is 10%, preferably 1 to 5%.

The combination in which tensile strain is applied is such that a semiconductor layer having a lattice constant in the above-mentioned range is appropriately selected in consideration of insulation properties, crystallinity and the like with respect to the p-type conductivity type layer to be used as a tensile stress layer. Can be used.

For example, for a p-type semiconductor layer of a GaAs compound semiconductor, InGaAs is used as a tensile stress layer.
Although a compound semiconductor of a system can be used, the present invention is not limited to this, and a combination of other material systems can also be used.

Further, the tensile stress layer can be provided as a lower layer of the p-type conductivity type layer, or as an upper layer if possible, or as both a lower layer and an upper layer. When provided in both the lower layer and the upper layer, a greater effect can be expected.

The tensile stress layer may be provided in the vicinity of the pn junction. However, if the tensile stress layer is structurally possible and has no adverse effect, the tensile stress layer may be formed over other portions such as the lower portion of the n-type semiconductor layer. It may be provided.

Further, in the present invention, a tensile stress layer, a drain layer, a source layer or a channel layer and, if necessary, a buffer layer can be provided.

The surface on which the drain layer, the source layer and the channel layer are formed is preferably insulative. For example, when a tensile stress layer is formed and these layers are formed on the surface, it is preferable to use a tensile stress layer having at least an insulating surface. Further, for example, in the case where a tensile stress layer is formed on the upper surface of the p-type conductive layer and a drain layer, a source layer, and a channel layer are formed on the surface of the buffer layer, it is preferable to use a buffer layer having at least an insulating surface. .

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments.

Embodiment 1 FIG. 1 is a sectional view showing a first embodiment of the present invention. This transistor uses a semi-insulating GaAs substrate as a semiconductor substrate 1 and has an i-Al _0.5 G
The buffer layer 2 of a _0.5 As provided, using the i-In _0.2 Ga _0.8 As layer as a stress layer 3 tensile thereon, p ⁺ -GaAs layer degenerated to the drain layer 4, and degenerate source layer 5 n ⁺ - GaAs layer, channel layer 6 has degenerated thickness 12n
m of about n ⁺ -GaAs layer, a gate insulating layer 7 i-Al
_0.3 Ga _0.7 As, an Al film on the gate electrode 8, an AuZn / Au film on the drain electrode 9, and an AuGe / A on the source electrode 10.
It is configured by laminating as shown in the figure using a u film.

Also in the transistor according to the first embodiment of the present invention, an interband tunnel junction is formed between the drain layer 4 and the channel layer 6, and the differential negative resistance characteristic is controlled by controlling the channel concentration by the gate voltage. Is obtained. At this time, the tensile stress layer 3 is not lattice-matched with the underlying layer, but its thickness is sufficiently increased until the strain is relaxed. As a result, the lattice constant of the p ⁺ -GaAs layer serving as the drain layer 4 is reduced by the underlying tensile stress layer 3
, A tensile strain is applied, the light hole concentration increases, and the tunnel current increases.

The method of manufacturing the transistor of this embodiment is performed as follows. First, (10) on the GaAs substrate 1
0) A laminated structure of a buffer layer 2 of 500 nm i-Al _0.5 Ga _0.5 As and a tensile stress layer 3 of 200 nm of i-In _0.2 Ga _0.8 As on the surface, and a thickness of 20 nm to be a drain layer 4
Respectively formed at a substrate temperature of 520 ° C. by the p ⁺ -GaAs layer (concentration 5 × 10 ¹⁹ cm ^-3 of Be containing as a dopant.) The molecular beam epitaxy (MBE) method. After removing the p ⁺ -GaAs layer other than the portion serving as the drain to form the drain layer 4, the source portion has a thickness of 20 μm.
nm n ⁺ -GaAs source layer 5 (concentration 1 × 10 ¹⁹ c
It contains m- ³ Si as a dopant. ) Was selectively grown. Further, a thickness of 12 nm serving as a channel layer
N ⁺ -GaAs layer (containing 1 × 10 ¹⁹ cm ⁻³ of Si as a dopant) and a 20-nm-thick i-Al _0.3 Ga _0.7 As layer serving as a gate insulating layer are grown on the entire surface. After depositing an Al film having a thickness of 50 nm, the Al film and the underlying i-Al _0.3 Ga _0.7 As layer and n ⁺ -GaAs layer are processed into a gate electrode shape, and the gate electrode 8, the gate insulating layer 7, and the channel layer 6 are formed. Was formed. Finally, a drain electrode 9 made of AuZn / Au is formed by a lift-off method.
And a source electrode 10 made of an AuGe / Au multilayer film.

With the device having this structure, the peak current density of the differential negative resistance characteristic is increased by about one digit as compared with the conventional structure.

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, a tensile stress layer 3b having a larger lattice constant than the drain layer is inserted above the drain layer 4, and the drain layer is distorted by both the lower tensile stress layer 3a and the upper tensile stress layer 3b. It has a structure. Thereby, the first
The strain in the drain layer can be made larger than in the first embodiment, and as a result, the current density further increases as compared with the first embodiment.

The method of manufacturing the transistor of this embodiment is performed as follows. First, (10) on the GaAs substrate 1
0) A stacked structure of a buffer layer 2 of 500 nm i-Al _0.5 Ga _0.5 As and a tensile stress layer 3 a of 200 nm of i-In _0.2 Ga _0.8 As on the surface, and a thickness of 20 n serving as a drain layer 4
m p ⁺ -GaAs layer (containing 5 × 10 ¹⁹ cm ⁻³ concentration of Be as a dopant), tensile stress layer 3b
An i-In _0.2 Ga _0.8 As layer having a thickness of 30 nm is formed at a substrate temperature of 520 ° C. by a molecular beam epitaxy (MBE) method. I-In other than the part to be drain
_0.2 Ga _0.8 As layer and p ⁺ -GaAs layer to form a further drain electrode removed portion of the i-In _{0 .2} Ga _0.8 A
After removing the s layer to form the drain layer 4 and the tensile stress layer 3b, a 20 nm thick n ⁺ -GaAs
Source layer 5 (concentration 1 × 10 ¹⁹ cm ^-. Which contains Si of ³ as a dopant) were selectively grown. Further, a 12 nm-thick n ⁺ -GaAs layer (containing Si at a concentration of 1 × 10 ¹⁹ cm ⁻³ as a dopant) serving as a channel layer, and a 20 nm-thick i-A serving as a gate insulating layer.
_10.3 Ga _0.7 As layer 7 is grown on the entire surface and has a thickness of 50 nm.
After depositing an Al film, an Al film and an underlying i-Al _0.3 Ga _0.7 As layer and an n ⁺ -GaAs
The s layer was processed to form a gate electrode 8, a gate insulating layer 7, and a channel layer 6. Finally, by lift-off method, A
drain electrode 9 made of uZn / Au and AuGe /
A source electrode 10 made of an Au multilayer film was formed.

With the device having this structure, the peak current density of the differential negative resistance characteristic is increased by about one digit compared to the conventional structure.

Embodiment 3 Next, a third embodiment of the present invention will be described with reference to FIG. In this example, the conductivity of the semiconductor constituting the drain layer, the source layer, and the channel layer of Example 1 was reversed. In this case, the channel layer becomes a p-type conductivity type, so that tensile strain was applied to the channel layer to increase the hole concentration. Thus, by reversing the polarity of the voltage applied to the first embodiment, similar characteristics can be obtained, and a complementary element can be realized.

The manufacturing method of this embodiment is performed as follows. First, on the (100) plane of the GaAs substrate 1, 500
i-Al _0.5 Ga _0.5 As buffer layer 2 of 200 nm
Lamination structure of i-In _0.2 Ga _0.8 As tensile stress layer 3 and 20 nm thick n ⁺ -GaAs to be drain layer 4
Layers (containing Si having a concentration of 1 × 10 ¹⁹ cm ^-3 as a dopant) are formed at a substrate temperature of 520 ° C. by a molecular beam epitaxy (MBE) method. After removing the n ⁺ -GaAs layer other than the portion serving as the drain to form the drain layer 4, a 20 nm thick p ⁺ -GaAs is formed on the source portion.
(Containing Be at a concentration of 5 × 10 ¹⁹ cm ⁻³ as a dopant) was selectively grown. Further, a 10 nm-thick p ⁺ -GaAs layer (containing Be at a concentration of 1 × 10 ¹⁹ cm ⁻³ as a dopant) serving as a channel layer, and a 20 nm-thick i-A serving as a gate insulating layer.
After growing an l _0.3 Ga _0.7 As layer on the entire surface and depositing an Al film having a thickness of 50 nm, the gate electrode is formed into an Al film, an i-Al _0.3 Ga _0.7 As layer under the Al film, and ap ⁺ -GaAs layer.
The layers were processed to form a gate electrode 8, a gate insulating layer 7, and a channel layer 6. Finally, by lift-off method, Au
Drain electrode 8 made of Ge / Au and AuZn / A
A source electrode 9 made of a u multilayer film was formed. With the device having this structure, characteristics complementary to those of the first embodiment can be obtained.
In addition, the peak current density of the differential negative resistance characteristic is increased by about one digit compared to the conventional structure.

[0029]

According to the present invention, a tunnel transistor having a negative resistance characteristic having a high current density can be provided. Therefore, high-speed operation at room temperature, low power consumption, and ultra-high density integration are possible. It is possible to realize a tunnel device integrated circuit.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 buffer layer 3 tensile stress layer 3a tensile stress layer (lower side) 3b tensile stress layer (upper side) 4 drain layer 5 source layer 6 channel layer 7 gate insulating layer 8 gate electrode 9 drain electrode 10 source electrode 13 buffer layer

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29/80-29 / 812

Claims (4)

(57) [Claims] 1. A semiconductor substrate having a drain layer of a first conductivity type semiconductor, a source layer of a second conductivity type semiconductor, and a channel layer of a second conductivity type semiconductor, wherein the drain layer and the channel layer are inter-band tunneling. In a tunnel transistor forming a junction, at least one of an upper surface and a lower surface of a semiconductor layer having a p-type conductivity (hereinafter, referred to as a p-type conductivity type layer) of one of the drain layer and the channel layer is provided. And a layer having a tensile stress with respect to the layer (hereinafter referred to as a tensile stress layer). 2. The tunnel transistor according to claim 1, wherein said tensile stress layer is formed of a semiconductor having a lattice constant larger than a lattice constant of said p-type conductivity type layer. 3. A drain layer of a first conductivity type semiconductor, a source layer of a second conductivity type semiconductor, and a channel layer of a second conductivity type semiconductor are formed on a semiconductor substrate, and inter-band tunneling is performed between the drain layer and the channel layer. A method for manufacturing a tunnel transistor to be a junction, wherein a tensile stress layer is provided in contact with at least one of an upper surface and a lower surface of the p-type conductivity type layer. 4. The method according to claim 3, wherein the tensile stress layer is formed of a semiconductor having a lattice constant larger than a lattice constant of the p-type conductivity type layer.