JP2808753B2 - Method for forming conductive layer of InP - Google Patents
Method for forming conductive layer of InPInfo
- Publication number
- JP2808753B2 JP2808753B2 JP30970389A JP30970389A JP2808753B2 JP 2808753 B2 JP2808753 B2 JP 2808753B2 JP 30970389 A JP30970389 A JP 30970389A JP 30970389 A JP30970389 A JP 30970389A JP 2808753 B2 JP2808753 B2 JP 2808753B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- inp
- forming conductive
- present
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、InP基板を用いた超高速、超高周波用電界
効果トランジスタあるいはヘテロ接合バイポーラトラン
ジスタ等の半導体装置の導電層を形成する方法に関す
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a conductive layer of a semiconductor device using an InP substrate, such as a field effect transistor for ultra high speed and ultra high frequency, or a heterojunction bipolar transistor.
InP等の化合物半導体結晶は電子飽和速度および電子
移動度が大きいことから超高周波素子材料として注目さ
れ、これを用いた電界効果トランジスタ等の半導体装置
の検討がいくつか行なわれており、例えばショットキー
接合型電界効果トランジスタ（MESFET）あるいは変調ド
ープ型電界効果トランジスタ等で良好な特性が得られて
いる。Compound semiconductor crystals such as InP have attracted attention as ultra-high-frequency device materials because of their high electron saturation speed and electron mobility.Semiconductor devices such as field-effect transistors using this have been studied. Good characteristics have been obtained with a junction field effect transistor (MESFET) or a modulation doped field effect transistor.
従来、InPの導電層を形成する方法として、例えばイ
オン注入法を用いてSiイオンを注入した後、熱所して活
性化を行うことが用いられている。Conventionally, as a method of forming a conductive layer of InP, for example, after ion implantation of Si ions using an ion implantation method, activation is performed in a hot place.
ところで、超高周波で用いるFETの動作層は高濃度
で、かつ膜厚の薄いことが必要とされるが、上記の方法
を用いて動作層を形成する場合、低エネルギーでイオン
を打ち込み、かつドーズ量を高める必要がある。さらに
活性化を行う場合にも短時間アニール等の特別な方法を
用いなければならない。By the way, the operating layer of the FET used at the ultra-high frequency needs to have a high concentration and a small film thickness. The amount needs to be increased. Further, when performing activation, a special method such as short-time annealing must be used.
本発明の目的はこのような問題点を解消し、簡単な方
法を用いて高濃度で、かつチャネル厚の薄いInP動作層
を提供することにある。An object of the present invention is to solve such a problem and to provide an InP operation layer having a high concentration and a small channel thickness by using a simple method.
前記目的を達成するため、本発明に係るInPの導電層
形成方法においては、半絶縁性InP基板を、SF6ガスを導
入したプラズマ中に晒した後、熱処理するものである。In order to achieve the above object, in the method for forming a conductive layer of InP according to the present invention, a semi-insulating InP substrate is exposed to plasma into which SF 6 gas has been introduced, and then heat-treated.
Ｎ型InP動作層を形成する方法として通常VPE法等の結
晶成長法あるいはイオン注入法が用いられている。イオ
ン注入法を用いることにより、簡便な工程により再現性
よく動作層を形成することができる。しかしながら、通
常の方法ではチャネル厚およびキャリア濃度に限界があ
り、十分な高濃度薄膜チャネルを得ることは困難であ
る。ところで、SF6プラズマ中にInP基板を適当な時間晒
すことにより、InP基板表面にSF6から分解したＳが吸着
する。これをさらに適当な時間熱処理することによりＳ
が活性化してＮ型ドーパントとして働き、表面から100
〜200Å程度の厚さの導電層が形成される。この導電層
は１×1013cm-2程度の高いシートキャリア濃度を持つ。As a method of forming the N-type InP operation layer, a crystal growth method such as a VPE method or an ion implantation method is generally used. By using an ion implantation method, an operation layer can be formed with good reproducibility by simple steps. However, the channel thickness and the carrier concentration are limited by the ordinary method, and it is difficult to obtain a sufficiently high-concentration thin film channel. However, by exposing the InP substrate suitable time during SF 6 plasma, S decomposed from SF 6 is adsorbed on the InP substrate surface. This is further heat-treated for an appropriate time so that S
Is activated and acts as an N-type dopant,
A conductive layer having a thickness of about 200 ° is formed. This conductive layer has a high sheet carrier concentration of about 1 × 10 13 cm −2 .
以下、本発明の一実施例を図を用いて説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明に係るInPの導電層形
成方法を工程順に示す図である。1 (a) to 1 (c) are views showing a method for forming a conductive layer of InP according to the present invention in the order of steps.
第１図（ａ）に示すように通常の平行平板反応性イオ
ンエッチング装置を用いて半絶縁性InP基板１をSF6ガス
を例えば10Pa導入したプラズマ中で２〜３分間処理し、
その後第１図（ｂ）に示すように保護膜として例えばPS
G膜２を2000Å通常のCVD装置を用いて基板１の表面に堆
積させる。さらに通常の電気炉を用いて、例えば水素ガ
ス雰囲気中700℃で20分間熱処理を行うことにより、第
１図（ｃ）に示すようにInP導電層３を形成する。As shown in FIG. 1 (a), the semi-insulating InP substrate 1 is treated for 2 to 3 minutes in a plasma into which SF 6 gas is introduced, for example, at 10 Pa, using a conventional parallel plate reactive ion etching apparatus.
Thereafter, as shown in FIG.
A G film 2 is deposited on the surface of the substrate 1 by using a conventional CVD apparatus of 2000 °. Further, by performing a heat treatment at 700 ° C. for 20 minutes in a hydrogen gas atmosphere using a normal electric furnace, the InP conductive layer 3 is formed as shown in FIG. 1C.
第２図は本発明の方法を用いて形成された導電層と従
来のイオン注入法を用いて形成された導電層のキャリア
濃度の深さ方向プロファイルを示す。図から明らかなよ
うに本発明によれば、高濃度でかつチャネル厚の薄い導
電層が得られる。FIG. 2 shows the depth profile of the carrier concentration of the conductive layer formed by using the method of the present invention and the conductive layer formed by using the conventional ion implantation method. As is clear from the figure, according to the present invention, a conductive layer having a high concentration and a small channel thickness can be obtained.
以上の説明から明らかなように本発明によれば、簡単
な工程により高濃度で、かつチャネル厚の薄いInP導電
層が得られ、これを動作層に用いることにより高性能な
InP系トランジスタの作製が可能となる。As is clear from the above description, according to the present invention, an InP conductive layer having a high concentration and a small channel thickness can be obtained by a simple process, and a high performance
InP-based transistors can be manufactured.
第１図（ａ），（ｂ），（ｃ）は本発明による導電層形
成方法を工程順に示す図、第２図は本発明の方法を用い
て形成された導電層と従来のイオン注入法を用いて形成
された導電層のキャリア濃度の深さ方向プロファイルを
示す図である。 １……半絶縁性InP基板 ２……PSG膜 ３……InP導電層1 (a), 1 (b) and 1 (c) are views showing a conductive layer forming method according to the present invention in the order of steps, and FIG. 2 is a diagram showing a conductive layer formed by using the method of the present invention and a conventional ion implantation method. FIG. 7 is a diagram showing a depth profile of the carrier concentration of a conductive layer formed by using FIG. 1. Semi-insulating InP substrate 2. PSG film 3. InP conductive layer
Claims (1)
ラズマ中に晒した後、熱処理することを特徴とするInP
の導電層形成方法。1. An InP substrate, comprising: exposing a semi-insulating InP substrate to plasma into which SF 6 gas has been introduced;
Method for forming a conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30970389A JP2808753B2 (en) | 1989-11-29 | 1989-11-29 | Method for forming conductive layer of InP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30970389A JP2808753B2 (en) | 1989-11-29 | 1989-11-29 | Method for forming conductive layer of InP |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03171619A JPH03171619A (en) | 1991-07-25 |
| JP2808753B2 true JP2808753B2 (en) | 1998-10-08 |
Family
ID=17996270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30970389A Expired - Fee Related JP2808753B2 (en) | 1989-11-29 | 1989-11-29 | Method for forming conductive layer of InP |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2808753B2 (en) |
-
1989
- 1989-11-29 JP JP30970389A patent/JP2808753B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03171619A (en) | 1991-07-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |