JP2762974B2 - Semiconductor container - Google Patents
Semiconductor containerInfo
- Publication number
- JP2762974B2 JP2762974B2 JP7329964A JP32996495A JP2762974B2 JP 2762974 B2 JP2762974 B2 JP 2762974B2 JP 7329964 A JP7329964 A JP 7329964A JP 32996495 A JP32996495 A JP 32996495A JP 2762974 B2 JP2762974 B2 JP 2762974B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- ceramic layer
- layer
- semiconductor
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 63
- 239000000919 ceramic Substances 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 23
- 238000001465 metallisation Methods 0.000 claims description 15
- 238000007789 sealing Methods 0.000 claims description 10
- 239000003566 sealing material Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 7
- 238000005219 brazing Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体容器に関し、
特に超高周波電力増幅用半導体装置の半導体容器に関す
る。TECHNICAL FIELD The present invention relates to a semiconductor container,
In particular, the present invention relates to a semiconductor container for a semiconductor device for amplifying ultra-high frequency power.
【０００２】[0002]
【従来の技術】高周波電力増幅装置の高周波利得を低下
させないためには、半導体容器の金属（又はメタライズ
パターン）で遮蔽された断面を小型化し、入出力のアイ
ソレーションを向上させ、かつ遮断周波数を上げること
が必要とされている。2. Description of the Related Art In order not to lower the high-frequency gain of a high-frequency power amplifier, a cross section of a semiconductor container shielded by a metal (or a metallized pattern) is miniaturized, input / output isolation is improved, and a cut-off frequency is reduced. It is needed to raise.
【０００３】このような課題を満足させる構造として、
超高周波電力増幅用半導体装置の従来の半導体容器は、
図３（Ａ）〜図３（Ｃ）に示すように、セラミック層
（セラミック基板）１と、半導体素子１６を搭載するた
めのメタライズパターン５と、入力端子９と、出力端子
１０と、接地端子１１Ａおよび１１Ｂと、入力端子９を
半導体素子１６の入力電極に金属細線１８で電気的に接
続するための配線パターン６と、出力端子１０を半導体
素子１６の入力電極に金属細線１８で電気的に接続する
ための配線パターン７と、接地端子１１Ａおよび１１Ｂ
を半導体素子の接地電極に金属細線２０で電気的に接続
するための配線（接地）パターン８Ａ及び８Ｂと、接地
配線パターン８Ａ及び８Ｂの一部に封止金属ロー材１７
の流れ止め用に設けられた凹部（非メタライズ領域から
なる溝）２２Ａ、２２Ｂと、セラミック基板１に接着さ
れ、接地配線パターン８Ａ及び８Ｂに接する内壁がメタ
ライズ（図中１２で示す）され、かつキャップ１４の封
止メタライズ層１５と気密封止するためのメタライズ層
１３を有する中空のセラミック層２１と、を備えて構成
されていた。なお、接地配線パターン８Ａ、８Ｂに設け
た金属ロー材流れ止め用の凹部（非メタライズ領域）２
２Ａ、２２Ｂの深さは数μｍ程度とされる。As a structure that satisfies such a problem,
Conventional semiconductor containers for semiconductor devices for amplifying ultra-high frequency power are:
As shown in FIGS. 3A to 3C, a ceramic layer (ceramic substrate) 1, a metallized pattern 5 for mounting a semiconductor element 16, an input terminal 9, an output terminal 10, and a ground terminal 11A and 11B, the wiring pattern 6 for electrically connecting the input terminal 9 to the input electrode of the semiconductor element 16 with the thin metal wire 18, and the output terminal 10 electrically connecting the input electrode of the semiconductor element 16 with the thin metal wire 18. Wiring pattern 7 for connection and ground terminals 11A and 11B
(Ground) patterns 8A and 8B for electrically connecting the ground wiring of the semiconductor element to the ground electrode of the semiconductor element by a thin metal wire 20;
(A groove formed of a non-metallized area) 22A, 22B provided for stopping the flow, and an inner wall which is adhered to the ceramic substrate 1 and which is in contact with the ground wiring patterns 8A, 8B is metalized (indicated by 12 in the figure), and The sealing metallized layer 15 of the cap 14 and the hollow ceramic layer 21 having the metallized layer 13 for hermetic sealing were provided. In addition, the concave portions (non-metallized regions) 2 for stopping the flow of the metal brazing material provided in the ground wiring patterns 8A and 8B.
The depth of 2A and 22B is set to about several μm.
【０００４】図３（Ａ）は、従来の半導体容器の平面
図、図２（Ｂ）は図２（Ａ）のＡ−Ａ′線に沿った断面
を示す図、図２（Ｃ）は図３（Ａ）のＢ−Ｂ′線に沿っ
た断面を示す図である。FIG. 3A is a plan view of a conventional semiconductor container, FIG. 2B is a view showing a cross section taken along line AA 'of FIG. 2A, and FIG. It is a figure which shows the cross section along the BB 'line of 3 (A).
【０００５】[0005]
【発明が解決しようとする課題】上述した従来の半導体
容器は、キャップ１４を上にして封止する際には、封止
用金属ロー材が半導体容器のメタライズ１２の側面に沿
って流れ、接地配線パターン８Ａ、８Ｂに設けた金属ロ
ー材流れ止め用の凹部（非メタライズ領域）２２Ａ、２
２Ｂを越え、接地用金属細線に触れて金属細線を溶断す
る不具合があり、逆にキャップを下にして封止する際に
は、封止部の気密性が悪く、気密不良を発生するという
不具合があった。When the conventional semiconductor container described above is sealed with the cap 14 facing upward, the sealing metal brazing material flows along the side surface of the metallization 12 of the semiconductor container and is grounded. Depressed portions (non-metallized regions) 22A, 2A, 2B provided in the wiring patterns 8A, 8B for stopping the flow of the metal brazing material.
There is a problem that the metal fine wire is blown by touching the fine metal wire for ground exceeding 2B, and conversely, when sealing with the cap down, the hermeticity of the sealing portion is poor and a poor airtightness occurs. was there.
【０００６】従って、本発明は上記問題点に鑑みて為さ
れたものであって、キャップを封止する際、封止用金属
ロー材が接地用配線を溶断することを防止する半導体容
器を提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and provides a semiconductor container which prevents a sealing metal brazing material from blowing a ground wiring when a cap is sealed. The purpose is to do.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するた
め、本発明は、半導体素子を搭載し該半導体素子を外部
端子に接続するためのメタライズパターンを備えたセラ
ミック基板と、内壁にシールド用メタライズ層を有し前
記半導体素子を取り囲むようにして配設される中空のセ
ラミック層と、を有する半導体素子の容器において、前
記セラミック基板が２層からなり、第１のセラミック層
には外部端子と前記半導体素子を電気的に接続するため
のメタライズパターン及び一側端面上にシールド用の接
地メタライズパターンを備え、前記第２のセラミック層
には前記半導体素子を接着するためのメタライズパター
ンと、前記第１のセラミック層に形成された外部端子と
前記半導体素子とを電気的に接続するための前記メタラ
イズパターンと前記半導体素子とを接続するためのメタ
ライズパターンと、を備え、前記第２のセラミック層の
前記接地用メタライズパターンの前記中空セラミック層
に接する領域に封着シール材流れ止め用の穴を設け、前
記第１のセラミック層に形成された前記シールド用の接
地メタライズパターンと電気的に接続されたことを特徴
とする半導体容器を提供する。In order to achieve the above object, the present invention provides a ceramic substrate having a metallized pattern for mounting a semiconductor element and connecting the semiconductor element to external terminals, and a metallizing plate for shielding on an inner wall. And a hollow ceramic layer disposed so as to surround the semiconductor element, wherein the ceramic substrate comprises two layers, and a first ceramic layer has external terminals and A metallization pattern for electrically connecting the semiconductor element and a ground metallization pattern for shielding on one end face; a metallization pattern for bonding the semiconductor element to the second ceramic layer; The metallized pattern for electrically connecting external terminals formed on the ceramic layer and the semiconductor element; and A metallization pattern for connecting a conductive element, and a hole for stopping the flow of a sealing material is provided in a region of the second ceramic layer in contact with the hollow ceramic layer of the ground metallization pattern; A semiconductor container characterized by being electrically connected to the shield metallization pattern formed on one ceramic layer.
【０００８】[0008]
【発明の実施の形態】本発明の実施の形態を図面を参照
して以下に説明する。Embodiments of the present invention will be described below with reference to the drawings.
【０００９】図１は、本発明に係る半導体容器の一実施
形態を示す。図１（Ａ）は平面図、図１（Ｂ）は図１
（Ａ）のＡ−Ａ′線の断面図、図１（Ｃ）は図１（Ａ）
のＢ−Ｂ′線の断面図である。FIG. 1 shows an embodiment of a semiconductor container according to the present invention. FIG. 1A is a plan view, and FIG.
1A is a cross-sectional view taken along the line AA ′ of FIG.
FIG. 7 is a sectional view taken along line BB ′ of FIG.
【００１０】本実施形態の半導体容器は、図１に示すよ
うに、第１のセラミック基板２Ａと、第２のセラミック
基板２Ｂと、両セラミック基板の接合部に設けられた接
地用メタライズ層３と、半導体素子１６を搭載するため
のメタライズパターン５と、入力端子９と、出力端子１
０と、接地端子１１Ａ及び１１Ｂと、入力端子９を半導
体素子１６の入力電極に金属細線１８で電気的に接続す
るための配線パターン６と、出力端子１０を半導体素子
１６の入力電極に金属細線１９で電気的に接続するため
の配線パターン７と、接地端子１１Ａ及び１１Ｂを半導
体素子の接地電極に金属細線２０で電気的に接続するた
めの配線（接地）パターン８Ａ及び８Ｂと、第２のセラ
ミック基板２Ｂに接着され、接地配線パターン８Ａ及び
８Ｂに接する内壁がメタライズ（１２）され、かつキャ
ップ１４の封止メタライズ層１５と気密封止するための
メタライズ層１３を有する中空のセラミック層２１と、
第２のセラミック基板２Ｂの接地用メタライズパターン
の中空セラミック層２１に接する部分に封着シール材流
れ止め用の穴４Ａ及び４Ｂと、を備えて構成されてい
る。穴４Ａ及び４Ｂは第２のセラミック基板２Ｂを例え
ば穴ぐり加工して形成される。As shown in FIG. 1, the semiconductor container according to the present embodiment includes a first ceramic substrate 2A, a second ceramic substrate 2B, and a metallization layer 3 for grounding provided at a joint between the two ceramic substrates. Metallized pattern 5 for mounting semiconductor element 16, input terminal 9, output terminal 1
0, the ground terminals 11A and 11B, the wiring pattern 6 for electrically connecting the input terminal 9 to the input electrode of the semiconductor element 16 with the thin metal wire 18, and the output terminal 10 connecting the thin metal wire to the input electrode of the semiconductor element 16. A wiring pattern 7 for electrical connection at 19; wiring (ground) patterns 8A and 8B for electrically connecting the ground terminals 11A and 11B to the ground electrode of the semiconductor element with a thin metal wire 20; A hollow ceramic layer 21 adhered to the ceramic substrate 2B, an inner wall in contact with the ground wiring patterns 8A and 8B is metallized (12), and has a metallized layer 13 for hermetically sealing with the sealing metallized layer 15 of the cap 14; ,
The second ceramic substrate 2B is provided with holes 4A and 4B for stopping the flow of the sealing material at a portion in contact with the hollow ceramic layer 21 of the metallized pattern for grounding. The holes 4A and 4B are formed by, for example, boring the second ceramic substrate 2B.
【００１１】図２は、本発明の第２の実施形態を示す。
本実施形態に係る半導体容器は、前記第１の実施形態に
加えて、半導体素子１６が直接、第１のセラミック基板
２Ａに搭載されるように、第２のセラミック基板２Ｂの
所定の領域に穴を開けた構成とされている。FIG. 2 shows a second embodiment of the present invention.
The semiconductor container according to the present embodiment has a hole in a predetermined region of the second ceramic substrate 2B so that the semiconductor element 16 is directly mounted on the first ceramic substrate 2A in addition to the first embodiment. Is opened.
【００１２】このように、半導体素子を第１のセラミッ
ク基板に直接搭載するよう、第２のセラミック基板に穴
を設けた場合、半導体素子を搭載する際の金属ロー材が
接地用および入出力用配線パターンに付着してボンディ
ング不良を起こす不具合を防止する効果がある。As described above, when a hole is provided in the second ceramic substrate so that the semiconductor element is directly mounted on the first ceramic substrate, the metal brazing material for mounting the semiconductor element is used for grounding and input / output. This has an effect of preventing a problem of causing a bonding failure by adhering to the wiring pattern.
【００１３】[0013]
【発明の効果】以上説明したように、本発明の半導体容
器は、第２のセラミック基板に設けた穴がキャップを封
止する際に金属封止ロー材の流れ止めの役割を果たし、
接地用金属細線の溶断を防止する効果がある。As described above, according to the semiconductor container of the present invention, the hole provided in the second ceramic substrate functions as a stopper for the metal sealing brazing material when the cap is sealed.
This has the effect of preventing the thin metal wire for ground from fusing.
【００１４】また、本発明（請求項２）によれば、半導
体素子を第１のセラミック基板に直接搭載するよう、第
２のセラミック基板に穴を設けた場合、半導体素子を搭
載する際の金属ロー材が接地用および入出力用配線パタ
ーンに付着してボンディング不良を起こす不具合を防止
する効果がある。Further, according to the present invention (claim 2), when a hole is provided in the second ceramic substrate so that the semiconductor element is directly mounted on the first ceramic substrate, the metal for mounting the semiconductor element can be reduced. This has the effect of preventing the problem that the soldering material adheres to the grounding and input / output wiring patterns and causes bonding failure.
【図面の簡単な説明】[Brief description of the drawings]
【図１】（Ａ）本発明に係る半導体容器の第１の実施形
態の構成を示す平面図である。 （Ｂ）本発明に係る半導体容器の第１の実施形態の構成
を示す断面図である（図１（Ａ）のＡ−Ａ′線に沿った
断面を示す図）。 （Ｃ）本発明に係る半導体容器の第１の実施形態の構成
を示す断面図である（図１（Ａ）のＢ−Ｂ′線に沿った
断面を示す図）。FIG. 1A is a plan view showing a configuration of a first embodiment of a semiconductor container according to the present invention. FIG. 1B is a cross-sectional view illustrating a configuration of the first embodiment of the semiconductor container according to the present invention (a cross-sectional view taken along line AA ′ in FIG. 1A). FIG. 2C is a cross-sectional view illustrating a configuration of the first embodiment of the semiconductor container according to the present invention (a cross-sectional view taken along line BB ′ in FIG. 1A).
【図２】（Ａ）本発明に係る半導体容器の第２の実施形
態の構成を示す平面図である。 （Ｂ）本発明に係る半導体容器の第２の実施形態の構成
を示す断面図である（図２（Ａ）のＡ−Ａ′線に沿った
断面を示す図）。 （Ｃ）本発明に係る半導体容器の第２の実施形態の構成
を示す断面図である（図２（Ａ）のＢ−Ｂ′線に沿った
断面を示す図）。FIG. 2A is a plan view showing a configuration of a second embodiment of the semiconductor container according to the present invention. FIG. 2B is a cross-sectional view illustrating a configuration of a second embodiment of the semiconductor container according to the present invention (a cross-sectional view taken along line AA ′ in FIG. 2A). FIG. 2C is a cross-sectional view illustrating a configuration of a second embodiment of the semiconductor container according to the present invention (a cross-sectional view taken along line BB ′ in FIG. 2A).
【図３】（Ａ）従来の半導体容器の構成を示す平面図で
ある。 （Ｂ）従来の半導体容器の構成を示す断面図である（図
３（Ａ）のＡ−Ａ′線に沿った断面を示す図）。 （Ｃ）従来の半導体容器の構成を示す断面図である（図
３（Ａ）のＢ−Ｂ′線に沿った断面を示す図）。FIG. 3A is a plan view showing a configuration of a conventional semiconductor container. FIG. 3B is a cross-sectional view illustrating a configuration of a conventional semiconductor container (a cross-sectional view taken along line AA ′ in FIG. 3A). FIG. 3C is a cross-sectional view illustrating a configuration of a conventional semiconductor container (a cross-sectional view taken along line BB ′ in FIG. 3A).
２Ａ 第１のセラミック基板 ２Ｂ 第２のセラミック基板 ３ 接地メタライズ層 ４Ａ、４Ｂ 穴 2A First ceramic substrate 2B Second ceramic substrate 3 Ground metallization layer 4A, 4B hole
Claims (3)
子に接続するためのメタライズパターンを備えたセラミ
ック基板と、 内壁にシールド用メタライズ層を有し前記半導体素子を
取り囲むようにして配設される中空のセラミック層と、 を有する半導体素子の容器において、 前記セラミック基板が２層からなり、第１のセラミック
層には外部端子と前記半導体素子を電気的に接続するた
めのメタライズパターン及び上面にシールド用の接地メ
タライズパターンを備え、 前記第２のセラミック層には前記半導体素子を接着する
ためのメタライズパターンと、前記第１のセラミック層
に形成された外部端子と前記半導体素子とを電気的に接
続するための前記メタライズパターンと前記半導体素子
とを接続するためのメタライズパターンと、を備え、 前記第２のセラミック層の前記接地用メタライズパター
ンの前記中空セラミック層に接する領域に封着シール材
流れ止め用の穴を設け、前記第１のセラミック層に形成
された前記シールド用の接地メタライズパターンと電気
的に接続されたことを特徴とする半導体容器。1. A ceramic substrate having a metallized pattern for mounting a semiconductor element and connecting the semiconductor element to an external terminal, and a metallized layer for shielding on an inner wall is provided so as to surround the semiconductor element. A hollow ceramic layer and a semiconductor element container, comprising: a ceramic substrate comprising two layers; a first ceramic layer having a metallized pattern for electrically connecting external terminals and the semiconductor element; A metallization pattern for bonding the semiconductor element to the second ceramic layer; and an external terminal formed on the first ceramic layer and the semiconductor element electrically connected to the second ceramic layer. A metallization pattern for connecting the semiconductor element and the metallization pattern for connecting the semiconductor element; A hole for stopping the flow of a sealing material is provided in a region of the grounding metallization pattern of the second ceramic layer which is in contact with the hollow ceramic layer, and the shield grounding formed in the first ceramic layer is provided. A semiconductor container electrically connected to a metallized pattern.
子が搭載される領域に穴をあけ、前記半導体素子が前記
第１のセラミック層に直接的に接着されることを特徴と
する請求項１記載の半導体容器。2. The semiconductor device according to claim 1, wherein a hole is formed in a region of the second ceramic layer where the semiconductor element is mounted, and the semiconductor element is directly bonded to the first ceramic layer. 2. The semiconductor container according to 1.
子に接続するためのメタライズパターンを備えたセラミ
ック基板と、 内壁にシールド用メタライズ層を有し前記半導体素子を
取り囲むようにして配設される中空のセラミック層と、
を有する半導体素子の容器において、 前記セラミック基板が複数層のセラミック層から成り、 最上のセラミック層が、下層のセラミック層の上面に配
設された接地用メタライズ層が前記中空セラミック層に
接する所定の領域に封着シール流れ止め用の穴を備えた
ことを特徴とする半導体容器。3. A ceramic substrate having a metallized pattern for mounting a semiconductor element and connecting the semiconductor element to an external terminal, and having a metallized layer for shielding on an inner wall and surrounding the semiconductor element. A hollow ceramic layer,
Wherein the ceramic substrate is composed of a plurality of ceramic layers, and the uppermost ceramic layer is a predetermined metallization layer disposed on the upper surface of the lower ceramic layer, and the ground metallization layer is in contact with the hollow ceramic layer. A semiconductor container comprising a hole for preventing a flow of a sealing seal in a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7329964A JP2762974B2 (en) | 1995-11-24 | 1995-11-24 | Semiconductor container |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7329964A JP2762974B2 (en) | 1995-11-24 | 1995-11-24 | Semiconductor container |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09148468A JPH09148468A (en) | 1997-06-06 |
| JP2762974B2 true JP2762974B2 (en) | 1998-06-11 |
Family
ID=18227243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7329964A Expired - Fee Related JP2762974B2 (en) | 1995-11-24 | 1995-11-24 | Semiconductor container |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762974B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005020046A (en) * | 2003-06-23 | 2005-01-20 | Mitsubishi Electric Corp | Electromagnetic apparatus and manufacturing method thereof |
| JP5101375B2 (en) * | 2008-04-03 | 2012-12-19 | 日本特殊陶業株式会社 | Package for storing semiconductor elements |
-
1995
- 1995-11-24 JP JP7329964A patent/JP2762974B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09148468A (en) | 1997-06-06 |
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