JP2759414B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an electrode or a wiring which can be used for a semiconductor device formed on a substrate having an insulating surface, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a technique for forming fine wiring using tantalum or aluminum has been known. And
A technique of covering these wirings with an oxide to make them insulated is also known. These techniques can be used for an integrated circuit formed on a substrate and the like. In particular, it can be used for a wiring portion of an active matrix type liquid crystal display device in which thin film transistors (TFTs) formed on a substrate having an insulating surface such as a glass substrate are integrated.

FIG. 2 shows an example of this technique. In FIG. 2, an aluminum film 22 for forming a wiring is formed on a suitable base 21 (generally an insulator).
Sc or Y, which is a group IIIa element, is added to this aluminum film. In the following, in the case where aluminum is simply used, it is assumed that such an impurity is included. In order to form this aluminum film as a wiring, it is necessary to etch the aluminum film using the resist mask 23.

As etching, isotropic wet etching is usually used. In this case, the etched end portion has a gentle shape as shown in FIG.

[0005] Then, an oxide layer 25 is formed around the patterned aluminum 22. This oxide layer 25 has a voltage of 100 V in an ethylene glycol solution containing tartaric acid, boric acid, and nitric acid of 3 to 10%.
It can be formed by applying the above voltage to aluminum. This step is generally called an anodizing step.

The oxide layer formed in the above-described anodic oxidation step is formed along the side surface of the smoothly formed aluminum film, as shown at 24 in FIG.

The formation of a wiring pattern in a shape as shown in FIG. 2C is not preferable in miniaturizing the wiring pattern and improving the isolation between the wirings.

In order to solve this problem, it is conceivable to use etching having anisotropy in the vertical direction. However, it is necessary to delicately set the edging conditions so as not to etch the base, which makes the process difficult. Increase.

On the other hand, conventionally, a structure as shown in FIG. 4 has been proposed as a TFT (thin film transistor).
FIG. 4 shows a dense barrier type anodic oxide layer 408.
And the porous anodic oxide layer 409 are connected to the gate electrode 40.
7 and the offset gate region 413 is formed by utilizing the thicknesses of these two oxide layers.

Although a dense anodic oxide layer is excellent in insulating properties, it is difficult to grow it to a thickness of 2,000 mm or more, and a high voltage is required in the anodic oxidation step. It is not suitable for obtaining the offset lengths 413 and 414 (for example, 1 μm).

On the other hand, a porous anodic oxide layer 409
Can form a thick oxide layer at low voltage,
The withstand voltage is extremely low, and the characteristics as an insulator are low. The structure of the TFT shown in FIG. 4 utilizes the features of the dense anodic oxide layer and the porous anodic oxide layer. That is, the porous anodic oxide layer 409, which is easy to grow, is used to increase the length of the offset gate, and the dense anodic oxide layer 408 is used to insulate the gate electrode. And insulation of the gate electrode.

[0012] However, according to studies by the present inventors, as shown in FIG. 4 the growth of the porous anodic oxide layer, is difficult to perform only laterally of the gate electrode,
It was confirmed that the length of the growth cannot be too large.

FIG. 3 shows this state. First, an aluminum film 32 having a thickness of 1 μm is formed on a base 31. This aluminum film contains 0.2 wt% of Sc (scandium) so that abnormal growth of aluminum does not occur in the subsequent anodic oxidation step.

By performing patterning using a photoresist mask 33, a state as shown in FIG. 3B is obtained. Next, using a 3 to 20% aqueous solution of citric acid, oxalic acid, phosphoric acid, chromic acid, or sulfuric acid, a porous anodic oxide layer 34 is formed on the exposed side surface of the gate electrode 32. At this time, the anodic oxide layer can be grown at a low applied voltage of about 10 to 30 V.

However, as shown at 35 in FIG. 3C, oxidation proceeds from the upper surface side of the gate electrode 32 where the mask 33 is present, and the growth of the oxide layer is observed also in this portion. There was found. It has been found that when the oxidation from the upper portion indicated by 35 progresses, the growth of the oxide layer from the side surface indicated by 34 is hindered.

That is, it has been found that when the anodic oxidation from the top indicated by 35 proceeds, the anodic oxidation indicated by 34 significantly decreases or almost stops.

Further, the anodic oxidation indicated by 35 which proceeds from near the interface of the mask 33 is uncontrollable and occurs with large variations. Therefore, it has been confirmed that the thickness of the anodic oxide layer in the lateral direction indicated by 34 also has a large variation.

The progress of the anodic oxidation step in the state shown in FIG. 3C is considered to be due to poor adhesion between the mask 33 and the aluminum film 32.

[Problems to be Solved by the Invention] An object of the present invention is to provide a technique for forming a pattern side surface vertically when forming a fine pattern such as a wiring.
Another object is to provide a structure in which anodic oxidation from the top surface does not progress when a porous anodic oxide layer is formed on the side surface of an electrode, and a method for manufacturing the same.

FIG. 1 shows the basic manufacturing steps provided by the present invention. In FIG. 1, reference numeral 11 denotes a base, for example, in FIG. 4, a gate insulating film 402 formed on a silicon semiconductor thin film. First, anodically oxidizable material, such as aluminum, tantalum, titanium, or silicon, is formed as 12 on the upper surface of the substrate. Then, in the anodic oxidation step, the dense oxide layer 13 is formed thin.

For example, when aluminum is used as 12, the step of forming the dense oxide layer 13 is as follows.
By energizing the aluminum 12 (about 10 to 30 V) in a 3 to 10% tartar liquid or an ethylene glycol solution containing boric acid or nitric acid, 100 to 10%
A dense oxide layer 13 having a thickness of about 00, for example, about 200
To form

In this step, the thickness of the oxide layer to be formed can be controlled by adjusting the applied voltage and the anodic oxidation time.

Next, a suitable mask 14 such as a photoresist or polyimide is formed. Then, a voltage of 10 to 30 V is applied in an acidic aqueous solution of 3 to 20% of citric acid, oxalic acid, phosphoric acid, chromic acid, and sulfuric acid to form the porous oxide layer 15. In this step,
Oxidation from above does not progress at all due to the action of the dense oxide layer 13 functioning as a barrier, so that the porous oxide layer 15 can be formed with a required thickness.

Further, a dense oxide layer 16 is formed to a thickness of 2000.degree. By the same steps as those for forming the dense oxide layer. In this step, a dense oxide layer 16 is formed between the porous oxide layer 15 and the aluminum 12.

After that, the basic steps are completed by removing the mask 14 and the dense oxide layer 13. At this time, since the dense oxide layer 13 is thin, it can be removed with an etchant such as buffered hydrofluoric acid. Further, the porous oxide layer 15 can be selectively removed with a phosphoric acid-based etchant.

In this way, it is possible to form a wiring pattern or an electrode pattern in which the portion 18 is formed vertically and well.

If the porous oxide layer 15 is used, it may be left as it is.

[0028]

【Example】

[Embodiment 1] This embodiment relates to a fine wiring using an anodizable material. FIG. 1 shows a schematic manufacturing process of this embodiment. In this embodiment, an example is described in which aluminum is used as a main component as a wiring material. As the material other than aluminum, tantalum, titanium, silicon, a mixed material thereof, or a material containing these materials as main components can be used.

In this embodiment, as shown by 18 in FIG. 1D, an aluminum wiring in which an end portion is formed vertically and an oxide layer 16 having a dense and excellent withstand voltage is formed therearound. 12

First, on a suitable base 11 (generally an insulating film or insulating material), an aluminium film 12 as a material for forming wiring is formed to a thickness of 2 μm. The thickness of the aluminum may be formed to a required thickness, and is not particularly limited. Further, aluminum to which 0.2 wt% of Sc (scandium) is added is used. This is for preventing abnormal growth (hillock) of aluminum from occurring in the subsequent anodic oxidation step. For preventing abnormal growth of aluminum at high temperature, S
Additives other than c (for example, Y) may be used.

Then, a voltage of 10 to 30 V is applied in an ethylene glycol solution containing 3% of tartaric acid,
A dense oxide layer 13 of about 00 ° is formed. And
Using a resist mask 14 for patterning, the aluminum film 12 and the oxide layer 13 thereon are processed into a predetermined pattern. At this time, since the oxide layer 13 is thin, it can be easily etched.

When the above patterning is performed by isotropic etching, the end of the aluminum film is formed in a gentle shape as indicated by 17. Further, due to the difference in the etching rate between the oxide layer 13 and the aluminum film 12, the etching progresses to the shape shown in FIG.

Then, a voltage of 10 to 30 V is applied to the aluminum electrode 12 in a 10% aqueous solution of oxalic acid to perform anodic oxidation. In this step, as shown at 15 in FIG. 1C, a porous (porous) oxide grows inward. This growth proceeds only from the surface in contact with the solution, and the growth distance can be arbitrarily controlled.

And if the growth distance is to some extent,
It has been confirmed that the growth edge is almost vertical. On the other hand, it has been confirmed that in the formation of a dense oxide layer, the state of oxidation proceeds along the shape of the starting state.

In this embodiment, the aluminum film 12
Is 2 μm, and the growth distance of the oxide layer 15 is 500 μm.
Although it is 0 °, it is confirmed by electron micrographs that the growth tip is almost vertical.

Further, by applying a voltage of 150 V in an ethylene glycol solution containing 3% of tartaric acid, a dense anodic oxide layer 16 having a thickness of 2000 mm is formed. The oxide layer 16 grows uniformly so as to surround the aluminum wiring 12. The oxide layer 16 grows from the interface between the porous oxide layer 15 and the aluminum wiring 12 toward the inside of the aluminum wiring 12.

Then, the resist mask 14 is removed,
Further, the oxide layer 13 is removed with buffered hydrofluoric acid. Since the oxide layer 13 is thin, it can be easily and selectively removed.

Next, the porous oxide layer 15 is etched with H ₃ PO ₄ which is a phosphoric acid-based etchant.
At this time, since the dense oxide layer 16 is formed, the aluminum wiring 12 is not etched at all, and only the oxide layer 15 can be selectively removed.

Thus, an aluminum wiring 12 whose periphery is covered with a dense and high withstand voltage oxide layer 16 as shown in FIG. 1D can be obtained.

In the structure shown in FIG.
As shown in FIG. 7, the side surface of the wiring portion 12 may be formed vertically. Therefore, it can be effectively used for achieving finer wiring.

[Embodiment 2] This embodiment relates to a structure in which the present invention is applied to the structure of a gate electrode of a TFT. FIG. 5 shows this embodiment. The TFT shown in this embodiment has a structure having low-concentration impurity regions 511 and 512 and high-concentration impurity regions 510 and 513 as shown in FIG. Has an offset gate region determined by the thickness of the anodic oxide layer 508.

First, a substrate (Corning 7059, 300
mm × 400mm or 100mm × 100mm) 5
01 as a base oxide film 502 having a thickness of 1000 to 300
A 0 ° silicon oxide film was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, TEOS must be
A film decomposed and deposited by the method D may be used.

Thereafter, an amorphous silicon film is deposited in a thickness of 300 to 5000 °, preferably 500 to 1000 ° by a plasma CVD method or an LPCVD method.
The crystals were left to stand in a reducing atmosphere at 24 ° C. for 24 hours to be crystallized.
This step may be performed by laser irradiation.
Then, the silicon film crystallized in this manner was patterned to form island regions 503. Further, a silicon oxide film 504 having a thickness of 700 to 1500 ° was formed thereon by a sputtering method.

Thereafter, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc (scandium)) film having a thickness of 1000 to 3 μm (here, 6000 °) is formed by electron beam evaporation or sputtering. Formed.

Before the formation of the photoresist 506, an aluminum oxide film (anodic oxide layer) having a thickness of 100 to 1000 (here, 200) is formed by anodic oxidation.
Form 500. This step is performed by applying a voltage of 10 to 30 V in an ethylene glycol solution containing 3% tartaric acid. The oxide layer is dense and has good adhesion to the photoresist 506 formed thereon, and also suppresses current leakage from the photoresist. This is extremely effective in forming the anodic oxide only on the side surfaces.

Then, a photoresist 506 (for example,
OFPR800 / 30 cp (Tokyo Ohka) was formed by spin coating. Thereafter, the photoresist and the aluminum film were patterned to form a gate electrode 505 and a mask film 506. (FIG. 5 (A))

Further, anodization is performed by passing an electric current through the electrolytic solution to a thickness of 3000 to 6000 °, for example, a thickness of 50
An anodic oxide 507 of 00 ° was formed. Anodizing is 3
Using an aqueous acidic solution such as citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc.
A constant current of V may be applied to the gate electrode. In this embodiment, the voltage is set to 10 V in an oxalic acid solution (30 ° C.)
Anodized for 0-40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (FIG. 5 (B))

The above process proceeds only in the lateral direction as shown in FIG. 5 and the required thickness can be obtained because of the formation of the dense oxide layer 500.

Next, the mask was removed, and a current was again applied to the gate electrode in the electrolytic solution. This time, 3-1
An ethylene glycol solution containing 0% tartaric acid, boric acid, and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. As a result, a barrier-type anodic oxide 508 was formed on the upper and side surfaces of the gate electrode. The thickness of the anodic oxide 508 is proportional to the applied voltage,
At an applied voltage of 150 V, an anodic oxide of 2000 ° was formed. The thickness of the anodic oxide 508 was determined by the required offset and the size of the overlap.
A high voltage of 250 V or more is required to obtain an anodic oxide having a thickness of 00 ° or more, which adversely affects the characteristics of the TFT. Therefore, the thickness is preferably 3000 ° or less. In this embodiment, the voltage was increased to 80 to 150 V, and the voltage was selected according to the required thickness of the anodic oxide film 508. (FIG. 5
(C))

After that, the silicon oxide film 504 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selectivity between silicon and silicon oxide. For example, if CF ₄ is used as an etching gas, the anodic oxide is not etched, and only the silicon oxide film 504 is etched. Also,
The silicon oxide film 504 'under the porous anodic oxide 507 was left without being etched. (FIG. 5 (D))

Thereafter, the anodic oxide 507 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxide 507 was etched, and the etching rate was about 600 ° / min. The gate insulating film 504 'thereunder remains as it is. Then, an impurity is implanted into the active layer 503 of the TFT in a self-aligned manner by using the gate electrode portion (that is, the gate electrode and the anodic oxide film around the gate electrode) and the gate insulating film as a mask by an ion doping method. (Source / drain region) 51
0, 513 and high resistance impurity regions 511, 512 were formed. Since phosphine (PH ₃ ) was used as the doping gas, an N-type impurity region was formed. Diborane (B ₂ H ₆ ) may be used as a doping gas to form a P-type impurity region. The dose is 5 × 10 ^{14 to} 5 ×
10 ¹⁵ cm ^-2 and the acceleration energy were 10 to 30 keV. Thereafter, a KrF excimer laser (wavelength 248 n)
m, a pulse width of 20 nsec) to activate the impurity ions introduced into the active layer.

According to the result of SIMS (secondary ion mass spectrometry), the impurity concentration of the regions 510 and 513 is 1 × 10
^{20 to} 2 × 10 ²¹ cm ⁻³ , 1 × 1 in regions 511 and 512
0 ^{17 to} 2 × 10 ¹⁸ cm ⁻³ . In dose conversion,
The former is 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² and the latter is 2 × 10
¹³ was ~5 × 10 ¹⁴ cm ^-2. This difference is caused by the presence or absence of the gate insulating film 504 '. Generally, the impurity concentration of the low resistance impurity region is 0.5 to 3 orders of magnitude higher than that of the high resistance impurity region. (FIG. 5
(E))

Finally, an interlayer insulator 514 is formed on the entire surface.
A silicon oxide film having a thickness of 3000 was formed by the CVD method. Then, contact holes are formed in the source / drain of the TFT, and aluminum wiring / electrodes 515 and 516 are formed.
Was formed. Further, hydrogen annealing was performed at 200 to 400 ° C. Thus, the TFT was completed. (FIG. 5 (F))

[0054]

In the anodic oxidation step, a thin and dense oxide layer is formed on the upper surface of the material for forming the oxide layer, and then a porous oxide layer is formed on the side surface of the material. The porous oxide layer can be formed with good controllability. Further, following the formation of the porous oxide layer, a dense oxide layer is formed, and by removing the porous oxide layer, the porous oxide layer is covered with the dense oxide layer, and the side surfaces are formed vertically. Wirings and electrodes can be configured.

[Brief description of the drawings]

FIG. 1 shows a process for manufacturing a wiring utilizing the present invention.

FIG. 2 shows a conventional example.

FIG. 3 shows a conventional example.

FIG. 4 shows a structure of a TFT.

FIG. 5 illustrates a manufacturing process of a TFT according to an example.

[Explanation of symbols]

 Reference numeral 12 Base aluminum 13 Dense oxide layer 14 Resist mask 15 Porous oxide layer 16 Dense oxide layer 21 ··· Base 22 ··· Aluminum 23 ··· Resist mask 25 ··· Oxide layer 31 ··· Base 32 ··· Aluminum 33 ··· Resist mask 34 ··· .Oxide layer 35.. .Oxide layer

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/3205 H01L 21/3213 H01L 21/336

Claims (5)

(57) [Claims] A first step of forming a dense first oxide layer on an upper surface of the film by anodizing a film made of an anodizable material; A second step of patterning the film into a predetermined shape to form an electrode or a wiring, and poling the side of the electrode or the wiring by anodizing.
A third step of forming a glass-like second oxide layer; and a fourth step of forming a dense third oxide layer on the upper and side surfaces of the electrode or wiring by anodic oxidation. A method for manufacturing a semiconductor device, comprising: 2. A first step of forming a dense first oxide layer on the upper surface of the film by anodizing a film made of an anodizable material; and the dense first oxide layer. And a second step of patterning the film into a predetermined shape to form an electrode or a wiring, and poling the side of the electrode or the wiring by anodizing.
A third step of forming a glass-like second oxide layer; a fourth step of forming a dense third oxide layer on the upper and side surfaces of the electrode or wiring by anodizing; A fifth step of removing the porous second oxide layer; and a method for manufacturing a semiconductor device. 3. A method for manufacturing an insulated gate field effect semiconductor device, comprising: forming a dense first oxide layer on an upper surface of a film made of an anodizable material by anodizing the film. 1
And a second step of patterning the dense first oxide layer and the film into a predetermined shape to form a gate electrode whose upper surface is covered with the dense first oxide layer, Paula a side surface of the gate electrode by anodizing
A third step of forming a second oxide layer in a semiconductor shape. 4. A method for manufacturing an insulated gate field effect semiconductor device, comprising: a first step of forming an insulating film on a semiconductor layer; and forming a film made of an anodizable material on the insulating film. A second step, by anodizing the film made of the anodizable material, to form a dense film on the upper surface of the film made of the anodizable material;
A third step of forming a simple first oxide layer, and a fourth step of forming a mask film on the dense first oxide layer.
A step of patterning the dense first oxide layer and the film with the mask film to form a gate electrode, and forming a polar on the side surface of the gate electrode by anodizing.
A sixth step of forming a second oxide layer in the form of an oxide, a seventh step of removing the mask film, an eighth step of removing the dense first oxide layer, and anodization. Performing a ninth step of forming a dense third oxide layer on the upper surface and side surfaces of the gate electrode; and forming the gate electrode covered with the dense third oxide layer and the porous second electrode. Forming a gate insulating film by etching the insulating film using the oxide layer as a mask, and forming a first region in which a portion of the semiconductor layer is exposed ; An eleventh step of forming a second region covered with only the gate insulating film on the semiconductor layer by removing the second oxide layer; and covering the dense third oxide layer with the third region. The gate electrode and the gate insulating film A twelfth step of implanting an impurity into the semiconductor by forming a low-resistance impurity region in the first region and a high-resistance impurity region in the second region. Method of manufacturing. 5. The method according to claim 4, further comprising, after the twelfth step, a thirteenth step of irradiating the low-resistance region and the high-resistance region with a laser to activate the impurities. A method for manufacturing a semiconductor device.