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JP2751911B2 - Pad for wire bonding of hybrid integrated circuit and method of forming the pad - Google Patents

Pad for wire bonding of hybrid integrated circuit and method of forming the pad

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Publication number
JP2751911B2
JP2751911B2 JP8058635A JP5863596A JP2751911B2 JP 2751911 B2 JP2751911 B2 JP 2751911B2 JP 8058635 A JP8058635 A JP 8058635A JP 5863596 A JP5863596 A JP 5863596A JP 2751911 B2 JP2751911 B2 JP 2751911B2
Authority
JP
Japan
Prior art keywords
pad
integrated circuit
hybrid integrated
wire bonding
gold plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8058635A
Other languages
Japanese (ja)
Other versions
JPH09252021A (en
Inventor
博仁 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8058635A priority Critical patent/JP2751911B2/en
Publication of JPH09252021A publication Critical patent/JPH09252021A/en
Application granted granted Critical
Publication of JP2751911B2 publication Critical patent/JP2751911B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は混合集積回路のワイ
ヤボンディング用パッドに関し、特にベアチップＬＳＩ
等の高集積ＩＣ搭載用基板のワイヤボンディング用パッ
ドに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pad for wire bonding of a mixed integrated circuit, and more particularly to a bare chip LSI.
And the like for a wire bonding pad of a highly integrated IC mounting substrate.

【０００２】[0002]

【従来の技術】従来用いられていたこの種の混成集積回
路の基板用電極パッドは、絶縁層を有する金属基板上に
導電性接着剤を介してパッドとなる金属薄膜を固着し、
これに重畳するように所望のパターンに導電性塗料を印
刷焼成して導電層を固着して形成していた。図４は特開
昭６０−４５０９２公報で開示された従来技術の電極パ
ッドの構造を示す模式的断面図であり、図中符号４１で
示されるものは金属基板、４２は導電性接着剤、４３は
金属薄膜、４４は電極パッド、４５は導電層、４６は外
部導線、４７ははんだ層を示す。2. Description of the Related Art Conventionally, an electrode pad for a substrate of a hybrid integrated circuit of this kind is formed by fixing a metal thin film serving as a pad on a metal substrate having an insulating layer via a conductive adhesive.
A conductive paint is printed and baked in a desired pattern so as to overlap with this, and the conductive layer is fixed and formed. FIG. 4 is a schematic cross-sectional view showing the structure of a conventional electrode pad disclosed in Japanese Patent Application Laid-Open No. 60-45092, in which reference numeral 41 denotes a metal substrate, 42 denotes a conductive adhesive, and 43 denotes a conductive adhesive. Denotes a metal thin film, 44 denotes an electrode pad, 45 denotes a conductive layer, 46 denotes an external conductor, and 47 denotes a solder layer.

【０００３】図５は、図４の基板用電極パッドの製造工
程を示す説明図であり、（ａ）は金属薄膜の片面に一部
を除いて導電性接着剤を塗布した状態の斜視図、（ｂ）
は金属基板に金属薄膜を接着した状態の斜視図、（ｃ）
は金属薄膜の一部を除去した状態の斜視図、（ｄ）は露
出した導電性接着剤に重畳して導電層を形成した状態の
斜視図、（ｅ）は金属薄膜に外部導線をはんだで接続し
た状態の断面図であり、符号４２ａは露出した導電性接
着剤、４３ａは除去される金属薄膜部を示す。FIG. 5 is an explanatory view showing a manufacturing process of the substrate electrode pad of FIG. 4. FIG. 5A is a perspective view showing a state where a conductive adhesive is applied to one side of a metal thin film except for a part thereof. (B)
Is a perspective view of a state in which a metal thin film is bonded to a metal substrate, (c)
Is a perspective view of a state in which a part of the metal thin film is removed, (d) is a perspective view of a state in which a conductive layer is formed so as to overlap with the exposed conductive adhesive, and (e) is a metal thin film to which an external conductor is soldered. It is a sectional view of the connected state, wherein reference numeral 42a denotes an exposed conductive adhesive, and 43a denotes a metal thin film portion to be removed.

【０００４】ほぼ金属パッドの形状に形成した銅などの
金属薄膜４３の片面に、導電性接着剤４２を隣接する２
つの隅部を除いて塗布し（ａ）、熱伝導の良好なＡｌ板
の表面を陽極酸化してアルミナ絶縁層を設けた金属基板
４１の絶縁層面に、裏返して導電性接着剤４２を下面と
した金属薄膜４３を所定の位置に固着し（ｂ）、エッチ
ングにより金属薄膜４３の不要部４３ａを除去し、導電
性接着剤４２の一部４２ａを露出させる（ｃ）、露出し
た導電性接着剤４２ａに重畳するように所定のパターン
に導電性塗料を印刷焼成して導電層４５を形成し
（ｄ）、金属薄膜４３に外部導線４６をはんだ層４７で
接続する。A conductive adhesive 42 is placed on one side of a thin metal film 43 of copper or the like formed substantially in the shape of a metal pad.
(A) The surface of an Al plate having good thermal conductivity is anodized, and the conductive adhesive 42 is turned upside down on the insulating layer surface of the metal substrate 41 provided with the alumina insulating layer. The metal thin film 43 thus fixed is fixed at a predetermined position (b), an unnecessary portion 43a of the metal thin film 43 is removed by etching, and a part 42a of the conductive adhesive 42 is exposed (c). The conductive layer 45 is formed by printing and baking a conductive paint in a predetermined pattern so as to overlap with the conductive layer 42 a (d), and the external conductive wire 46 is connected to the metal thin film 43 by the solder layer 47.

【０００５】以上のような工程で、外部導線４６は電極
パッド４４の金属薄膜４３に強力に接続される。In the above steps, the external conductor 46 is strongly connected to the metal thin film 43 of the electrode pad 44.

【０００６】[0006]

【発明が解決しようとする課題】上述の従来の技術で
は、通常のはんだによる外部導線の接続には十分対応で
きるが、ワイヤボンディング用の電極処理が行なわれて
いないので、最近小型軽量化の目的で搭載の機会の増加
しているＬＳＩ等の高集積ＩＣ（半導体装置）のワイヤ
によるボンディングは難しく、接続できたとしても信頼
性に乏しいという問題がある。The above-mentioned prior art can sufficiently cope with the connection of external conductors by ordinary soldering, but since the electrode processing for wire bonding is not performed, the object of recent miniaturization is to reduce the size and weight. However, there is a problem that it is difficult to bond a highly integrated IC (semiconductor device) such as an LSI, which has an increasing number of mounting opportunities, with a wire, and even if the connection can be made, the reliability is poor.

【０００７】ワイヤボンディング用に電極パッドに処理
を行なうためには、一般に金めっきを用いるが、そのた
めには構造上全部のパッドを一括してめっきを行なう必
要があり、ワイヤボンディングの必要のない金属パッド
にまで高価な金めっき処理を行なう必要があるという問
題点もあった。[0007] In order to perform processing on electrode pads for wire bonding, gold plating is generally used. For that purpose, it is necessary to perform plating on all pads collectively from the viewpoint of structure, so that metal which does not require wire bonding is required. There is also a problem that expensive gold plating must be performed on the pads.

【０００８】本発明の目的は、混成集積回路用のワイヤ
ボンディング用パッドと、必要な電極パッドのみをワイ
ヤボンディング対応可能とする電極パッドの形成方法と
を提供することにある。It is an object of the present invention to provide a wire bonding pad for a hybrid integrated circuit and a method for forming an electrode pad that enables only necessary electrode pads to be compatible with wire bonding.

【０００９】[0009]

【課題を解決するための手段】本発明の混成集積回路の
ワイヤボンディング用パッドは、混成集積回路のワイヤ
ボンディング用パッドであって、混成集積回路の基板上
に導電層により形成された第１のパッドと、片面に金め
っき層が形成された金属片と反対面に重着された導電性
接着剤とからなる第２のパッドとから構成され、第２の
パッドは導電性接着剤を介して第１のパッド上に固着さ
れている。SUMMARY OF THE INVENTION A wire bonding pad of a hybrid integrated circuit according to the present invention is a wire bonding pad of a hybrid integrated circuit, the first pad being formed by a conductive layer on a substrate of the hybrid integrated circuit. A pad, and a second pad made of a metal piece having a gold plating layer formed on one surface and a conductive adhesive layered on the opposite surface, and the second pad is formed via the conductive adhesive. It is fixed on the first pad.

【００１０】また、混成集積回路の基板上に導電層によ
り形成された第１のパッドと、片面に金めっき層が形成
され、反対面に接着層が形成された誘電体とからなる第
２のパッドとから構成され、第２のパッドは金めっき層
を表面として接着層で第１のパッド上に固着されていて
もよい。[0010] A second pad composed of a conductive layer on a substrate of a hybrid integrated circuit and a dielectric having a gold plating layer formed on one surface and an adhesive layer formed on the other surface. The second pad may be fixed on the first pad by an adhesive layer with the gold plating layer as a surface.

【００１１】本発明の混成集積回路のワイヤボンディン
グ用パッドの形成方法は、混成集積回路の基板上の所定
の位置に、所定の形状で、導電層により第１のパッドを
形成し、片面に金めっき層が形成された金属板を、金め
っき層を接着面としてポリマーのフイルム上に剥離可能
に接着し、金属板の反対面に導電性接着剤を重着し、導
電性接着剤と金属板との不要部分をフイルム上から除去
して、所定の位置に所定のパッド形状の第２のパッドを
形成し、第１のパッドの上面に、第２のパッドの導電性
接着剤面が整合するように、フイルムを配置して、第２
のパッドを第１のパッドに導電性接着剤で固着させ、フ
ィルムを剥離することにより接続面に金めっきを有する
パッドを形成する。According to a method of forming a pad for wire bonding of a hybrid integrated circuit according to the present invention, a first pad is formed by a conductive layer in a predetermined shape at a predetermined position on a substrate of a hybrid integrated circuit, and gold is formed on one surface. The metal plate on which the plating layer is formed is peelably adhered to the polymer film with the gold plating layer as the bonding surface, and a conductive adhesive is applied on the opposite surface of the metal plate, and the conductive adhesive and the metal plate An unnecessary portion of the second pad is removed from the film to form a second pad having a predetermined pad shape at a predetermined position, and the conductive adhesive surface of the second pad is aligned with the upper surface of the first pad. So that the film is placed
Is fixed to the first pad with a conductive adhesive, and the film is peeled off to form a pad having gold plating on the connection surface.

【００１２】また、混成集積回路の基板上の所定の位置
に、所定の形状で、導電層により第１のパッドを形成
し、所定のパッド形状に形成された第２のパッドを、金
めっき層を接着面としてポリマーのフイルム上に、剥離
可能に所定の位置に接着し、第１のパッドの上面に、第
２のパッドの接着面が整合するように、フイルムを配置
して、第２のパッドを第１のパッドに固着させ、フィル
ムを剥離することにより接続面に金めっきを有するパッ
ドを形成してもよい。A first pad of a predetermined shape is formed by a conductive layer at a predetermined position on a substrate of the hybrid integrated circuit, and a second pad formed in a predetermined pad shape is replaced with a gold plating layer. Is adhered to a predetermined position on a polymer film as an adhesive surface, and the film is arranged on the upper surface of the first pad such that the adhesive surface of the second pad is aligned with the second film. The pad having the gold plating on the connection surface may be formed by fixing the pad to the first pad and peeling the film.

【００１３】混成集積回路の電極パッドの内、ワイヤボ
ンディングで接続される電極パッドを、ワイヤボンディ
ングに適したパッドの構造とできるので、ワイヤによる
電気的接続信頼性が向上する。[0013] Of the electrode pads of the hybrid integrated circuit, the electrode pad connected by wire bonding can have a pad structure suitable for wire bonding, so that the reliability of electrical connection by wires is improved.

【００１４】また、それ以外の電極パッドには、ワイヤ
ボンディング用の処理を行なわないので、経済的に電極
パッドを形成することができる。Further, since the other electrode pads are not subjected to the process for wire bonding, the electrode pads can be formed economically.

【００１５】[0015]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。図１は本発明の第１の実施
の形態のワイヤボンディング用パッドの形成工程を示す
模式的斜視図であり、（ａ）はパッドＡが所定のパター
ンに配置されたポリマーシートを示し、（ｂ）は導電層
と接続したパッドＢが所定のパターンに配設された基板
を示す。図２はパッドＢ上にパッドＡが固着され、基板
上に固着されたＩＣのパッドＣとワイヤでボンディング
された状態を示し、（ａ）は斜視図、（ｂ）は（ａ）の
断面Ｘ−Ｘの断面図である。両図中、符号１１は基板、
１２はパッドＢ、１３はパッドＡ、１４はポリマーシー
ト、１５はＩＣ、１５ａはパッドＣ、１６はワイヤ、１
７は導電性接着剤、１８は金属片である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic perspective view showing a step of forming a wire bonding pad according to a first embodiment of the present invention. FIG. 1A shows a polymer sheet in which pads A are arranged in a predetermined pattern, and FIG. ) Shows a substrate on which pads B connected to a conductive layer are arranged in a predetermined pattern. 2A and 2B show a state in which a pad A is fixed on a pad B and a pad C of an IC fixed on a substrate is bonded with a wire. FIG. 2A is a perspective view, and FIG. 2B is a sectional view of FIG. It is sectional drawing of -X. In both figures, reference numeral 11 is a substrate,
12 is a pad B, 13 is a pad A, 14 is a polymer sheet, 15 is an IC, 15a is a pad C, 16 is a wire, 1
7 is a conductive adhesive, and 18 is a metal piece.

【００１６】フイルム状の柔軟性のあるポリマーシート
１４上の、ワイヤボンディング用の電極パッドの配置に
対応する位置に、パッドＡ１３が配置されている。パッ
ドＡは、ワイヤと接続させるための金めっきが片面に施
された銅やコバールなどの金属片１８と、反対面の全面
に塗布された導電性接着剤１７とから構成され、金属片
１８の金めっき面がポリマーシート１４に剥離可能に貼
り付けられている。A pad A13 is arranged on the film-like flexible polymer sheet 14 at a position corresponding to the arrangement of the electrode pads for wire bonding. The pad A is composed of a metal piece 18 such as copper or Kovar having gold plating on one side for connection with a wire, and a conductive adhesive 17 applied on the entire surface on the opposite side. The gold plating surface is releasably attached to the polymer sheet 14.

【００１７】一方、混成集積回路の基板１１の絶縁層面
には、通常のはんだによる接続用の従来技術による電極
パッドの他に、ワイヤ１６によるボンディングを必要と
するＬＳＩ等のＩＣ１５の接続するパッド位置に、所定
のパターンで導電層と一体となったパッドＢ１２が形成
されており、パッドＢ１２上にポリマーシート１４を用
いてパッドＡ１３を接着剤１７を下面として整合状態で
転載して接着させ、ポリマーシート１４を除去すること
によって金めっき面を有するワイヤボンディング用の電
極パッドが基板１１上に形成される。On the other hand, on the insulating layer surface of the substrate 11 of the hybrid integrated circuit, in addition to the conventional electrode pads for connection using solder, pad positions to be connected to ICs 15 such as LSIs which require bonding by wires 16 are connected. A pad B12 integrated with the conductive layer is formed in a predetermined pattern, and the pad A13 is transferred onto and bonded to the pad B12 in an aligned state with the adhesive 17 as a lower surface using a polymer sheet 14. By removing the sheet 14, an electrode pad for wire bonding having a gold-plated surface is formed on the substrate 11.

【００１８】次にこの形成工程を一実施例によって詳細
に説明する。先ず、厚さ１００μｍの透明なポリマーシ
ート１４上に、厚さ０．２〜０．５μｍの金めっき処理
をしたコバールからなる厚さ１００μｍの金属板が、金
めっき面を下にして剥離可能に貼り付けられる。Next, this forming step will be described in detail with reference to an embodiment. First, a 100-μm-thick transparent polymer sheet 14 is coated with a gold-plated Kovar having a thickness of 0.2 to 0.5 μm. Pasted.

【００１９】貼り付けられた金属板の上面に銀ペースト
等の導電性接着剤１７が塗布される。A conductive adhesive 17 such as a silver paste is applied to the upper surface of the attached metal plate.

【００２０】次に、ワイヤ１６によるボンディングを必
要とするＬＳＩ等のＩＣ１５の接続するパッド位置にパ
ッドが形成されるように接着剤１７をマスク加工し、金
属板をエッチングで除去して、ポリマーシート１４上の
所定の位置に、所定の形状のパッドＡ１３が形成され
る。Next, an adhesive 17 is mask-processed so that a pad is formed at a pad position where an IC 15 such as an LSI which requires bonding by a wire 16 is connected, and a metal plate is removed by etching. A pad A13 having a predetermined shape is formed at a predetermined position on the.

【００２１】混成集積回路の、陽極酸化により表面にア
ルミナ絶縁層が形成されたＡｌなどの金属やセラミック
等の基板１１の絶縁層面に、通常のはんだによる接続用
の従来技術による電極パッドを形成するとともに、ワイ
ヤ１６によるボンディングを必要とするＬＳＩ等のＩＣ
１５の接続するパッド位置に、所定のパターンで従来技
術の導電層と一体となったパッドＢ１２を形成する。A conventional electrode pad for connection by ordinary solder is formed on an insulating layer surface of a substrate 11, such as a metal such as Al or a ceramic, having an alumina insulating layer formed on the surface by anodic oxidation of the hybrid integrated circuit. In addition, ICs such as LSIs that require bonding by wires 16
A pad B12 integrated with the conductive layer of the related art is formed in a predetermined pattern at a pad position to be connected to the pad 15.

【００２２】基板１１に形成されたパッドＢ１２上に、
ポリマーシート１４とともにパッドＡ１３を接着剤１７
を下面として位置合わせして転載して接着し、ポリマー
シート１４を除去することによって金めっき面を有する
ワイヤボンディング用の電極パッドが基板１１上に形成
される。On a pad B12 formed on the substrate 11,
Adhesive 17 with pad A13 together with polymer sheet 14
The lower electrode is aligned as a lower surface, transferred and adhered, and the polymer sheet 14 is removed, whereby an electrode pad for wire bonding having a gold-plated surface is formed on the substrate 11.

【００２３】基板１１上の所定の位置にＩＣ１５を固着
し、ＩＣ１５のパッドＣ１５ａと基板１１に形成された
ワイヤボンディング用の電極パッドの金めっき面とを金
ワイヤ１６で接続する。The IC 15 is fixed at a predetermined position on the substrate 11, and the pad C 15 a of the IC 15 is connected to the gold-plated surface of the electrode pad for wire bonding formed on the substrate 11 by the gold wire 16.

【００２４】本実施例ではポリマーシート１４に貼り付
けられた金属板をエッチングにより整形してパッドＡ１
３を形成したが、予めパッドの形状に形成されたパッド
Ａ１３をポリマーシート１４の所定の位置に貼り付けて
もよい。In the present embodiment, the metal plate adhered to the polymer sheet 14 is shaped by etching to form the pad A1.
Although the pad 3 is formed, a pad A13 formed in a pad shape in advance may be attached to a predetermined position of the polymer sheet 14.

【００２５】次に図３を参照して第２の実施の形態を説
明する。図３は本発明の第２の実施の形態のワイヤボン
ディング用パッドの近傍の模式的断面図であり、符号３
１は基板、３２はパッドＢ、３５はＩＣ、３５ａはパッ
ドＣ、３６はワイヤ、３８は、誘電体３８ａは金めっ
き、３８ｂは接着層である。Next, a second embodiment will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view showing the vicinity of a wire bonding pad according to a second embodiment of the present invention.
1 is a substrate, 32 is a pad B, 35 is an IC, 35a is a pad C, 36 is a wire, 38 is a dielectric 38a, gold plating, and 38b is an adhesive layer.

【００２６】本実施の形態では、第１の実施の形態で、
金属片１８と接着剤１７で構成されていたパッドＡ１３
が、片面が金めっきされ反対面に接着層を持つ、誘電体
で構成される。その他の構成及びワイヤボンディング用
パッドの形成工程は第１の実施の形態と同様である。In the present embodiment, in the first embodiment,
Pad A13 composed of metal piece 18 and adhesive 17
However, it is composed of a dielectric material, one side of which is gold-plated and has an adhesive layer on the other side. Other configurations and the process of forming the wire bonding pads are the same as those of the first embodiment.

【００２７】[0027]

【発明の効果】以上説明したように本発明は、混成集積
回路の電極パッドの内、ワイヤボンディングで接続され
る電極パッドを、ワイヤボンディングに適したパッドの
構造とすることができるので、ワイヤによる電気的接続
強度を向上させ信頼性を高めることができるという効果
がある。As described above, according to the present invention, among the electrode pads of the hybrid integrated circuit, the electrode pads connected by wire bonding can be formed in a pad structure suitable for wire bonding. There is an effect that electrical connection strength can be improved and reliability can be improved.

【００２８】また、それ以外の電極パッドは、ワイヤボ
ンディング用の処理を行なわず従来技術が応用できるの
で全体のコストが下がり、経済的に電極パッドを形成す
ることができるという効果もある。In addition, since the conventional technology can be applied to the other electrode pads without performing the process for wire bonding, the overall cost can be reduced and the electrode pads can be formed economically.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態のワイヤボンディン
グ用パッドの形成工程を示す模式的斜視図である。
（ａ）はパッドＡが所定のパターンに配置されたポリマ
ーシートを示す。（ｂ）は導電層と接続したパッドＢが
所定のパターンに配設された基板を示す。FIG. 1 is a schematic perspective view showing a step of forming a wire bonding pad according to a first embodiment of the present invention.
(A) shows a polymer sheet in which pads A are arranged in a predetermined pattern. (B) shows a substrate on which pads B connected to a conductive layer are arranged in a predetermined pattern.

【図２】パッドＢ上にパッドＡが固着され、基板上に固
着されたＩＣのパッドＣとワイヤでボンディングされた
状態を示す説明図である。（ａ）は斜視図である。
（ｂ）は（ａ）の断面Ｘ−Ｘの断面図である。FIG. 2 is an explanatory diagram showing a state in which a pad A is fixed on a pad B and is bonded to a pad C of an IC fixed on a substrate with a wire. (A) is a perspective view.
(B) is a sectional view taken along the section XX of (a).

【図３】本発明の第２の実施の形態のワイヤボンディン
グ用パッドの近傍の模式的断面図である。FIG. 3 is a schematic cross-sectional view showing the vicinity of a wire bonding pad according to a second embodiment of the present invention.

【図４】特開昭６０−４５０９２公報で開示された従来
技術の電極パッドの構造を示す模式的断面図である。FIG. 4 is a schematic sectional view showing the structure of a conventional electrode pad disclosed in Japanese Patent Application Laid-Open No. 60-45092.

【図５】図４の基板用電極パッドの製造工程を示す説明
図である。（ａ）は金属薄膜の片面に一部を除いて導電
性接着剤を塗布した状態の斜視図である。（ｂ）は金属
基板に金属薄膜を接着した状態の斜視図である。（ｃ）
は金属薄膜の一部を除去した状態の斜視図である。
（ｄ）は露出した導電性接着剤に重畳して導電層を形成
した状態の斜視図である。（ｅ）は金属薄膜に外部導線
をはんだで接続した状態の断面図である。FIG. 5 is an explanatory view showing a manufacturing process of the substrate electrode pad of FIG. 4; (A) is a perspective view of a state where a conductive adhesive is applied to one side of a metal thin film except for a part thereof. (B) is a perspective view of a state where a metal thin film is adhered to a metal substrate. (C)
FIG. 3 is a perspective view of a state where a part of the metal thin film is removed.
(D) is a perspective view showing a state in which a conductive layer is formed so as to overlap the exposed conductive adhesive. (E) is a sectional view showing a state in which an external conductor is connected to the metal thin film by soldering.

【符号の説明】[Explanation of symbols]

１１、３１ 基板 １２、３２ パッドＢ １３ パッドＡ １４ ポリマーシート １５、３５ ＩＣ １５ａ パッドＣ １６、３６ ワイヤ １７ 導電性接着剤 １８ 金属片 ３８ 誘電体 ３８ａ 金めっき ３８ｂ 接着層 ４１ 金属基板 ４２ 導電性接着剤 ４２ａ 露出した導電性接着剤 ４３ 金属薄膜 ４３ａ 除去される金属薄膜部 ４４ 電極パッド ４５ 導電層 ４６ 外部導線 ４７ はんだ層 11, 31 Substrate 12, 32 Pad B 13 Pad A 14 Polymer sheet 15, 35 IC 15a Pad C 16, 36 Wire 17 Conductive adhesive 18 Metal piece 38 Dielectric 38a Gold plating 38b Adhesive layer 41 Metal substrate 42 Conductive adhesive Agent 42a Exposed conductive adhesive 43 Metal thin film 43a Metal thin film portion to be removed 44 Electrode pad 45 Conductive layer 46 External conductor 47 Solder layer

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 混成集積回路のワイヤボンディング用パ
ッドであって、 前記混成集積回路の基板上に導電層により形成された第
１のパッドと、 片面に金めっき層が形成された金属片と反対面に重着さ
れた導電性接着剤とからなる第２のパッドとから構成さ
れ、 前記第２のパッドは前記導電性接着剤を介して前記第１
のパッド上に固着されていることを特徴とするワイヤボ
ンディング用パッド。1. A wire bonding pad for a hybrid integrated circuit, comprising: a first pad formed by a conductive layer on a substrate of the hybrid integrated circuit; and a metal piece having a gold plating layer formed on one surface. A second pad made of a conductive adhesive layered on a surface, wherein the second pad is connected to the first pad via the conductive adhesive.
A wire bonding pad fixed on the pad. 【請求項２】 混成集積回路のワイヤボンディング用パ
ッドであって、 前記混成集積回路の基板上に導電層により形成された第
１のパッドと、 片面に金めっき層が形成され、反対面に接着層が形成さ
れた誘電体とからなる第２のパッドとから構成され、 前記第２のパッドは前記金めっき層を表面として前記接
着層で前記第１のパッド上に固着されていることを特徴
とするワイヤボンディング用パッド。2. A wire bonding pad for a hybrid integrated circuit, comprising: a first pad formed by a conductive layer on a substrate of the hybrid integrated circuit; and a gold plating layer formed on one surface and adhered to an opposite surface. A second pad made of a dielectric on which a layer is formed, wherein the second pad is fixed on the first pad by the adhesive layer with the gold plating layer as a surface. Wire bonding pad. 【請求項３】 請求項１に記載の混成集積回路のワイヤ
ボンディング用パッドの形成方法であって、 混成集積回路の基板上の所定の位置に、所定の形状で、
導電層により第１のパッドを形成し、 片面に金めっき層が形成された金属板を、前記金めっき
層を接着面としてポリマーのフイルム上に剥離可能に接
着し、前記金属板の反対面に導電性接着剤を重着し、前
記導電性接着剤と前記金属板との不要部分を前記フイル
ム上から除去して、所定の位置に所定のパッド形状の前
記第２のパッドを形成し、 前記第１のパッドの上面に、前記第２のパッドの導電性
接着剤面が整合するように、前記フイルムを配置して、
前記第２のパッドを前記第１のパッドに前記導電性接着
剤で固着させ、 前記フィルムを剥離することにより接続面に金めっきを
有するパッドを形成することを特徴とするワイヤボンデ
ィング用パッドの形成方法。3. The method of forming a wire pad for a hybrid integrated circuit according to claim 1, wherein the hybrid integrated circuit has a predetermined shape at a predetermined position on a substrate.
A first pad is formed by a conductive layer, and a metal plate having a gold plating layer formed on one surface is releasably adhered to a polymer film using the gold plating layer as an adhesion surface, and is attached to an opposite surface of the metal plate. An electrically conductive adhesive is applied, and unnecessary portions of the electrically conductive adhesive and the metal plate are removed from the film to form the second pad having a predetermined pad shape at a predetermined position. Disposing the film such that the conductive adhesive surface of the second pad is aligned with the upper surface of the first pad;
Forming a pad having gold plating on a connection surface by fixing the second pad to the first pad with the conductive adhesive and peeling the film; Method. 【請求項４】 請求項１又は請求項２に記載の混成集積
回路のワイヤボンディング用パッドの形成方法であっ
て、 混成集積回路の基板上の所定の位置に、所定の形状で、
導電層により第１のパッドを形成し、 所定のパッド形状に形成された前記第２のパッドを、金
めっき層を接着面としてポリマーのフイルム上に、剥離
可能に所定の位置に接着し、 前記第１のパッドの上面に、前記第２のパッドの接着面
が整合するように、前記フイルムを配置して、前記第２
のパッドを前記第１のパッドに固着させ、 前記フィルムを剥離することにより接続面に金めっきを
有するパッドを形成することを特徴とするワイヤボンデ
ィング用パッドの形成方法。4. A method for forming a wire bonding pad for a hybrid integrated circuit according to claim 1, wherein the hybrid integrated circuit has a predetermined shape at a predetermined position on a substrate of the hybrid integrated circuit.
Forming a first pad with a conductive layer, bonding the second pad formed in a predetermined pad shape to a predetermined position on a polymer film with a gold plating layer as an adhesive surface, in a releasable manner; Disposing the film so that the adhesive surface of the second pad is aligned with the upper surface of the first pad;
A method for forming a pad for wire bonding, comprising: fixing a pad to the first pad; and peeling the film to form a pad having a gold plating on a connection surface.
JP8058635A 1996-03-15 1996-03-15 Pad for wire bonding of hybrid integrated circuit and method of forming the pad Expired - Lifetime JP2751911B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8058635A JP2751911B2 (en) 1996-03-15 1996-03-15 Pad for wire bonding of hybrid integrated circuit and method of forming the pad

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8058635A JP2751911B2 (en) 1996-03-15 1996-03-15 Pad for wire bonding of hybrid integrated circuit and method of forming the pad

Publications (2)

Publication Number Publication Date
JPH09252021A JPH09252021A (en) 1997-09-22
JP2751911B2 true JP2751911B2 (en) 1998-05-18

Family

ID=13090053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8058635A Expired - Lifetime JP2751911B2 (en) 1996-03-15 1996-03-15 Pad for wire bonding of hybrid integrated circuit and method of forming the pad

Country Status (1)

Country Link
JP (1) JP2751911B2 (en)

Also Published As

Publication number Publication date
JPH09252021A (en) 1997-09-22

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