JP2781019B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2781019B2 JP2781019B2 JP1231135A JP23113589A JP2781019B2 JP 2781019 B2 JP2781019 B2 JP 2781019B2 JP 1231135 A JP1231135 A JP 1231135A JP 23113589 A JP23113589 A JP 23113589A JP 2781019 B2 JP2781019 B2 JP 2781019B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- semiconductor chip
- semiconductor device
- copper foil
- electrolytic copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 claims description 30
- 239000011347 resin Substances 0.000 claims description 28
- 229920005989 resin Polymers 0.000 claims description 28
- 238000012546 transfer Methods 0.000 claims description 25
- 238000007789 sealing Methods 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 239000011889 copper foil Substances 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000011253 protective coating Substances 0.000 claims description 8
- 238000010292 electrical insulation Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000007613 environmental effect Effects 0.000 description 7
- 238000007689 inspection Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体チップが一体的に樹脂封止されて提供
される半導体装置およびその製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device provided with a semiconductor chip integrally sealed with a resin, and a method of manufacturing the same.
（従来の技術） 半導体装置は電子装置をはじめきわめて多種類の製品
に広く利用されており、ICカードといった小形製品にも
利用されるようになっている。(Prior Art) Semiconductor devices are widely used in a wide variety of products including electronic devices, and are also used in small products such as IC cards.
これら製品で用いられる半導体装置の実装方式には、
パッケージに半導体チップを搭載してパッケージごと回
路基板に実装するパッケージ方式と、回路基板に半導体
チップをじかに接続するベアチップ方式とがある。The semiconductor device mounting methods used in these products include:
There are a package system in which a semiconductor chip is mounted on a package and the entire package is mounted on a circuit board, and a bare chip system in which a semiconductor chip is directly connected to a circuit board.
前記のパッケージ方式の場合には、パッケージ内に半
導体チップが封止されて保護されているので、取り扱い
がきわめて容易であり、実装が容易にでき、また耐環境
性に優れている等の特徴がある。In the case of the above-mentioned package system, since the semiconductor chip is sealed and protected in the package, it is extremely easy to handle, easy to mount, and has excellent features such as excellent environmental resistance. is there.
これに対し、ベアチップ方式は回路基板にじかに半導
体チップを接続するから、小面積で実装でき、高密度実
装が可能になるという特徴がある。On the other hand, the bare chip method is characterized in that a semiconductor chip is directly connected to a circuit board, so that it can be mounted in a small area and high density mounting is possible.
（発明が解決しようとする課題） しかしながら、上記ベアチップ方式にしても、半導体
チップは回路基板等の接続用基板に実装されるから、IC
カードのようなきわめて薄型に形成される装置において
は基板の厚さが薄型化を阻むという問題点があった。ま
た半導体チップが露出することから、耐環境性に劣ると
いう問題は避けられない。(Problems to be Solved by the Invention) However, even with the above bare chip method, since the semiconductor chip is mounted on a connection board such as a circuit board, an IC is required.
In an extremely thin device such as a card, there is a problem that the thickness of the substrate prevents the thinning. Further, since the semiconductor chip is exposed, the problem of poor environmental resistance is inevitable.
そこで本発明は上記問題点を解消すべくなされたもの
であり、その目的とするところは、小型化が図れ、かつ
耐環境性に優れる半導体装置およびその製造方法を提供
するにある。SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a semiconductor device which can be reduced in size and has excellent environmental resistance and a method for manufacturing the same.
（課題を解決するための手段） 本発明は上記目的を達成するため次の構成を備える。(Means for Solving the Problems) The present invention has the following configuration to achieve the above object.
すなわち、半導体チップと回路パターンとがフリップ
チップ法あるいはTAB方式によって電気的に接続され、
前記回路パターンの半導体チップが搭載された一方の面
側に、前記半導体チップおよび回路パターンが封止樹脂
により一体に樹脂封止された半導体装置において、前記
回路パターンは電解銅箔がエッチングされて形成され、
該電解銅箔の粗面側となる一方の面が前記封止樹脂に接
合されていることを特徴としている。That is, the semiconductor chip and the circuit pattern are electrically connected by the flip chip method or the TAB method,
In a semiconductor device in which the semiconductor chip and the circuit pattern are integrally resin-sealed with a sealing resin on one surface side on which the semiconductor chip of the circuit pattern is mounted, the circuit pattern is formed by etching an electrolytic copper foil. And
One surface of the electrolytic copper foil which is on the rough side is joined to the sealing resin.
半導体チップと回路パターンとが樹脂封止されている
ので、小型化が図れ、耐環境性にも優れると共に、電解
銅箔からなる回路パターンの粗面側が封止樹脂に接合さ
れているので、接合が強固である。Since the semiconductor chip and the circuit pattern are resin-sealed, miniaturization and excellent environmental resistance can be achieved, and the rough side of the circuit pattern made of electrolytic copper foil is bonded to the sealing resin. Is strong.
電解銅箔からなる前記回路パターンの鏡面側となる他
方の面を前記封止樹脂の表面に露出させてもよい。The other surface on the mirror surface side of the circuit pattern made of the electrolytic copper foil may be exposed to the surface of the sealing resin.
あるいは電解銅箔からなる前記回路パターンの鏡面側
となる他方の面を、外部接続用の端子部等の所要個所を
除いて、電気的絶縁性を有する保護コーティングによっ
て被覆してもよい。この場合には一層耐環境性に優れ
る。Alternatively, the other surface on the mirror surface side of the circuit pattern made of the electrolytic copper foil may be covered with a protective coating having an electrical insulation property except for a necessary portion such as a terminal portion for external connection. In this case, the environment resistance is further improved.
また本発明に係る半導体装置の製造方法では、電気的
絶縁性を有するベースフィルム上に剥離可能に金属層が
設けられた転写フィルムの金属層をエッチングして回路
パターンを形成する工程と、該転写フィルムの回路パタ
ーンが形成された一方の面側に半導体チップをフリップ
チップ法あるいはTAB方式によって電気的に接続して搭
載する工程と、前記転写フィルムの半導体チップが搭載
された一方の面側に、前記半導体チップおよび回路パタ
ーンを一体に樹脂封止する工程と、前記ベースフィルム
を封止樹脂から剥離除去する工程とを含むことを特徴と
している。Further, in the method for manufacturing a semiconductor device according to the present invention, a step of forming a circuit pattern by etching a metal layer of a transfer film provided with a releasable metal layer on an electrically insulating base film, A step of electrically connecting and mounting a semiconductor chip on one surface side on which a circuit pattern of the film is formed by a flip chip method or a TAB method, and on one surface side of the transfer film on which the semiconductor chip is mounted, The method includes a step of integrally sealing the semiconductor chip and the circuit pattern with a resin, and a step of peeling and removing the base film from a sealing resin.
回路パターンを転写法によって形成するので製造が容
易である。Since the circuit pattern is formed by a transfer method, manufacture is easy.
なお、前記回路パターンの他方の面側に、外部接続用
の端子部等の所要個所を除いて、電気的絶縁性を有する
保護コーティングを施すようにすれば、耐環境性に一層
優れる半導体装置を提供できる。In addition, if a protective coating having electrical insulation properties is applied to the other surface side of the circuit pattern except for a required portion such as a terminal portion for external connection, a semiconductor device having more excellent environmental resistance can be obtained. Can be provided.
また前記金属層が設けられた転写フィルムとして、電
気的絶縁性を有するベースフィルムに電解銅箔を鏡面側
をベースフィルムに向け、粗面側を外方に向けて接合し
た転写フィルムを用いることにより、封止樹脂との接合
強度の高い回路パターンを有する半導体装置を提供でき
る。Further, as the transfer film provided with the metal layer, by using a transfer film bonded to the base film having electrical insulating properties, the electrolytic copper foil is mirror-faced to the base film, and the roughened surface is directed outward. In addition, it is possible to provide a semiconductor device having a circuit pattern having a high bonding strength with a sealing resin.
（実施例） 以下に本発明の好適な実施例を添付図面に基づいて詳
細に説明する。(Embodiment) Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
第１図は本発明に係る半導体装置の製造方法を示す説
明図である。この製造方法においては転写フィルムを用
いることを特徴とする。FIG. 1 is an explanatory view showing a method for manufacturing a semiconductor device according to the present invention. This manufacturing method is characterized in that a transfer film is used.
転写フィルムはベースフィルム上に金属層を剥離可能
に接合したものであるが、第１図（ａ）は転写フィルム
10の金属層にレジストパターンを形成した後、エッチン
グを施して回路パターン12を形成した状態を示す。回路
パターン12は半導体チップが接続されるボンディング部
及び信号線路、回路部品接続部、外部接続用の端子部等
を含む。The transfer film is obtained by bonding a metal layer on a base film in a releasable manner.
This shows a state where a circuit pattern 12 is formed by forming a resist pattern on the metal layer 10 and then performing etching. The circuit pattern 12 includes a bonding portion to which the semiconductor chip is connected, a signal line, a circuit component connection portion, an external connection terminal portion, and the like.
14は転写フィルムベースフィルム、15は剥離層、16は
金属層である。金属層16としては電解銅箔が好適に利用
でき、ベースフィルム14に電解銅箔の鏡面側を接合する
ことにより転写フィルムとすることができる。14 is a transfer film base film, 15 is a release layer, and 16 is a metal layer. Electrodeposited copper foil can be suitably used as the metal layer 16, and a transfer film can be obtained by bonding the mirror side of the electroplated copper foil to the base film.
第２図に電解銅箔を用いた転写フィルム10の拡大図を
示す。図のように、電解銅箔はその表面が複雑な凹凸が
形成された粗面に形成されるから、粗面を封止樹脂側に
して後述する樹脂封止を行うことにより、表面の凹凸に
よるアンカー効果によって回路パターン12と封止樹脂が
強固に接合するという利点がある。FIG. 2 shows an enlarged view of the transfer film 10 using the electrolytic copper foil. As shown in the figure, the surface of the electrolytic copper foil is formed on a rough surface having complicated irregularities. There is an advantage that the circuit pattern 12 and the sealing resin are firmly joined by the anchor effect.
第１図（ｂ）は回路パターン12に半導体チップ18と回
路部品20を接続した状態を示す。ここではフリップ法に
よって半導体チップ18を接続する例を示す。この場合は
半導体チップ18にはあらかじめバンプ19を形成してお
き、回路パターン12のボンディング部とバンプ19を位置
合わせし、半導体チップ18を加圧、加熱して接続する。FIG. 1B shows a state in which the semiconductor chip 18 and the circuit component 20 are connected to the circuit pattern 12. Here, an example in which the semiconductor chips 18 are connected by the flip method is shown. In this case, bumps 19 are formed on the semiconductor chip 18 in advance, the bonding portions of the circuit pattern 12 are aligned with the bumps 19, and the semiconductor chip 18 is connected by pressing and heating.
なお、半導体チップ18を確実にボンディングするた
め、半導体チップ18が接合される回路パターン12のボン
ディング部にはあらかじめ平滑処理及び金めっき等の表
面処理を施すようにするとよい。回路部品20ははんだ付
け等によって接合する。In order to securely bond the semiconductor chip 18, the bonding portion of the circuit pattern 12 to which the semiconductor chip 18 is bonded may be subjected to a smoothing process and a surface treatment such as gold plating in advance. The circuit components 20 are joined by soldering or the like.
次に、転写フィルム10のベースフィルム14を封止樹脂
22から剥離する。これにより、回路パターン12が露出す
る。転写フィルム10の金属層16に上記の電解銅箔を用い
た場合は、金属層16の鏡面が露出する。Next, the base film 14 of the transfer film 10 is sealed with a sealing resin.
Peel from 22. Thereby, the circuit pattern 12 is exposed. When the above-described electrolytic copper foil is used for the metal layer 16 of the transfer film 10, the mirror surface of the metal layer 16 is exposed.
得られた半導体装置の回路パターン12の接点部に金め
っきを施し、実装用のモジュールとして電子装置等に搭
載する。The contact portion of the circuit pattern 12 of the obtained semiconductor device is plated with gold, and mounted on an electronic device or the like as a mounting module.
また、単体として利用するような場合は、第１図
（ｄ）のように端子部24を除く範囲に電気的絶縁性を有
する保護コーティング26を施して回路パターン12を保護
するようにするといい。In the case where the circuit pattern 12 is used as a single unit, it is preferable to protect the circuit pattern 12 by applying a protective coating 26 having an electrical insulating property to a region excluding the terminal portion 24 as shown in FIG.
なお、上記実施例では、フリップチップ法によって半
導体チップを接続したが、TAB方式によって半導体チッ
プを接続する場合も同様にして製造することができる。In the above embodiment, the semiconductor chips are connected by the flip chip method. However, when the semiconductor chips are connected by the TAB method, the semiconductor chips can be similarly manufactured.
第３図にTAB方式による製造方法を示す。図で27がTAB
テープである。TABテープ27はバンプ19によって半導体
チップ18に一括ボンディングされ、インナーリード部分
が樹脂封止される。28は封止樹脂である。FIG. 3 shows a manufacturing method using the TAB method. In the figure, 27 is TAB
It is a tape. The TAB tape 27 is collectively bonded to the semiconductor chip 18 by the bump 19, and the inner lead portion is resin-sealed. 28 is a sealing resin.
TABテープ27が接続された半導体チップ18は第３図
（ａ）に示すように、転写フィルム10の回路パターン12
に合わせて接続される。第３図（ｂ）は、TABテープを
介して半導体チップ18を接続した後、回路部品20等を搭
載して樹脂封止した状態を示す。樹脂封止後は、ベース
フィルム14を剥離し、上記実施例と同様の方法にしたが
って製造する。As shown in FIG. 3 (a), the semiconductor chip 18 to which the TAB tape 27 is connected has the circuit pattern 12 of the transfer film 10.
Connected according to. FIG. 3 (b) shows a state in which after connecting the semiconductor chip 18 via a TAB tape, the circuit component 20 and the like are mounted and resin-sealed. After the resin sealing, the base film 14 is peeled off, and it is manufactured according to the same method as in the above embodiment.
第４図は長尺状の転写フィルムを用いた加工例を示
す。FIG. 4 shows a processing example using a long transfer film.
図で14は前記転写フィルム10のベースフィルムで、ベ
ースフィルム14上には回路パターンが繰り返しパターン
で形成され、同時に各回路パターンに接続して検査用ラ
イン40及び電解めっきの導通をとるためのバスライン42
が設けられる。In the figure, reference numeral 14 denotes a base film of the transfer film 10, on which a circuit pattern is formed in a repetitive pattern on the base film 14, and connected to each circuit pattern at the same time to establish a test line 40 and a bus for conducting electroplating. Line 42
Is provided.
転写フィルムに対してはまず、金属層をエッチングし
て回路パターンおよび検査用ライン40、バスライン42を
形成する。次に、所定部位にめっきを施し、半導体チッ
プ、回路部品等を搭載し、樹脂封止する。第４図は樹脂
封止した状態を示す。樹脂封止した後、ベースフィルム
14を剥離除去し、次いで封止樹脂22に保護コーティング
を施す。この後、端子部等に仕上げめっきを施し、検査
用ライン40等の不要部分を除去して各モジュールを単体
に分離する。For the transfer film, first, the metal layer is etched to form the circuit pattern, the inspection line 40, and the bus line. Next, plating is performed on a predetermined portion, and a semiconductor chip, a circuit component, and the like are mounted and sealed with a resin. FIG. 4 shows a state of resin sealing. After sealing with resin, base film
14 is removed and then a protective coating is applied to the sealing resin 22. Thereafter, the terminal portions and the like are subjected to finish plating, unnecessary portions such as the inspection lines 40 and the like are removed, and each module is separated into single units.
モジュール部をあらかじめ検査する場合は、樹脂封止
した後、検査用ライン40の短絡部分を打ち抜いて行う。
図で44は回路を独立させるための打ち抜き部である。In the case of inspecting the module portion in advance, after the resin is sealed, the short-circuit portion of the inspection line 40 is punched out.
In the figure, reference numeral 44 denotes a punching section for making the circuit independent.
こうして、半導体チップ、回路部品等が搭載されて樹
脂封止された半導体装置が得られる。Thus, a semiconductor device in which the semiconductor chip, the circuit components, and the like are mounted and sealed with a resin is obtained.
この製造方法においては、上記のようにしてめっき処
理等を含めて連続加工ができ、また、製造途中において
半導体装置の検査を行うことができ、有効な製造方法と
することができる。In this manufacturing method, continuous processing including plating treatment and the like can be performed as described above, and the semiconductor device can be inspected during the manufacturing process, thereby providing an effective manufacturing method.
上記実施例で説明した半導体装置の製造方法によれ
ば、各種製品、用途に応じた機能を有する半導体装置を
製造することが容易にでき、各種機器に搭載して所要の
機能を発揮させることができる。According to the method of manufacturing a semiconductor device described in the above embodiment, a semiconductor device having a function corresponding to various products and applications can be easily manufactured, and can be mounted on various devices to exhibit required functions. it can.
また、得られた半導体装置を単体としてみた場合、半
導体チップは回路パターンに接続されているのみで、回
路基板を使用しないから、装置の小形化、薄型化にきわ
めて有効である。これにより、ICカードのような小形製
品にも容易に応用利用することが可能になる。Further, when the obtained semiconductor device is viewed as a single body, the semiconductor chip is only connected to the circuit pattern and does not use a circuit board, which is extremely effective for downsizing and thinning the device. This makes it possible to easily apply and use small products such as IC cards.
また、上記製造方法においてはフリップチップ法ある
いはTAB方式によって半導体チップを接続しているか
ら、半導体チップを接続する面積が小さくてすみ、高密
度実装が可能となると共に、さらに薄形化を図ることが
できる。また、半導体チップおよび回路部品等が樹脂に
よって完全に封止して提供されるから耐環境性も向上す
るという利点がある。In addition, in the above manufacturing method, since the semiconductor chips are connected by the flip chip method or the TAB method, the area for connecting the semiconductor chips can be small, high-density mounting is possible, and further thinning is required. Can be. Further, since the semiconductor chip and the circuit components are completely sealed and provided with the resin, there is an advantage that the environmental resistance is improved.
以上、本発明について好適な実施例をあげて種々説明
したが、本発明はこの実施例に限定されるものではな
く、発明の精神を逸脱しない範囲内で多くの改変を施し
得るのはもちろんのことである。As described above, the present invention has been described variously with preferred embodiments, but the present invention is not limited to these embodiments, and it is needless to say that many modifications can be made without departing from the spirit of the invention. That is.
（発明の効果） 本発明に係る半導体装置では、半導体チップと回路パ
ターンとが樹脂封止されているので、小型化、薄型化が
図れ、耐環境性にも優れると共に、電解銅箔からなる回
路パターンの粗面側が封止樹脂に接合されているので、
接合が強固である。(Effect of the Invention) In the semiconductor device according to the present invention, since the semiconductor chip and the circuit pattern are resin-sealed, the size and thickness can be reduced, the environment resistance is excellent, and the circuit made of electrolytic copper foil is used. Since the rough side of the pattern is joined to the sealing resin,
Bonding is strong.
電解銅箔からなる前記回路パターンの鏡面側となる他
方の面を、外部接続用の端子部等の所要個所を除いて保
護コーティングによって被覆することにより、一層耐環
境性に優れる半導体装置を提供できる。By coating the other surface of the circuit pattern made of the electrolytic copper foil on the mirror surface side with a protective coating except for a required portion such as a terminal portion for external connection, a semiconductor device having more excellent environmental resistance can be provided. .
また本発明方法によれば、回路パターンを転写法によ
って形成するので製造が容易である。Further, according to the method of the present invention, since the circuit pattern is formed by the transfer method, manufacturing is easy.
その際、転写フィルムとして、電気的絶縁性を有する
ベースフィルムに電解銅箔を鏡面側をベースフィルムに
向け、粗面側を外方に向けて接合した転写フィルムを用
いることにより、封止樹脂との接合強度の高い回路パタ
ーンを有する半導体装置を提供できる。At that time, as a transfer film, by using a transfer film in which the electrolytic copper foil is bonded to the base film having electrical insulation properties with the mirror side facing the base film and the rough side facing outwards, the sealing resin and And a semiconductor device having a circuit pattern having a high bonding strength.
第１図は半導体装置の製造方法の第１の実施例を示す説
明図、第２図は転写フィルムの断面図、第３図は半導体
チップの他の搭載方法を示す説明図、第４図は長尺状フ
ィルムを用いた製造例を示す説明図である。 10……転写フィルム、12……回路パターン、14……ベー
スフィルム、18……半導体チップ、19……バンプ、20…
…回路部品、22……封止樹脂、24……端子部、26……保
護コーティング、27……TABテープ、28……封止樹脂、4
0……検査用パターン、42……バスライン。FIG. 1 is an explanatory view showing a first embodiment of a method of manufacturing a semiconductor device, FIG. 2 is a sectional view of a transfer film, FIG. 3 is an explanatory view showing another mounting method of a semiconductor chip, and FIG. It is explanatory drawing which shows the example of manufacture using a long film. 10 ... Transfer film, 12 ... Circuit pattern, 14 ... Base film, 18 ... Semiconductor chip, 19 ... Bump, 20 ...
… Circuit components, 22… Seal resin, 24… Terminal part, 26… Protective coating, 27… TAB tape, 28 …… Seal resin, 4
0: Inspection pattern, 42: Bus line.
Claims (6)
チップ法あるいはTAB方式によって電気的に接続され、
前記回路パターンの半導体チップが搭載された一方の面
側に、前記半導体チップおよび回路パターンが封止樹脂
により一体に樹脂封止された半導体装置において、 前記回路パターンは電解銅箔がエッチングされて形成さ
れ、該電解銅箔の粗面側となる一方の面が前記封止樹脂
に接合されていることを特徴とする半導体装置。1. A semiconductor chip and a circuit pattern are electrically connected by a flip chip method or a TAB method.
In a semiconductor device in which the semiconductor chip and the circuit pattern are integrally resin-sealed with a sealing resin on one surface side on which the semiconductor chip of the circuit pattern is mounted, the circuit pattern is formed by etching an electrolytic copper foil And a roughened side of the electrolytic copper foil is joined to the sealing resin.
側となる他方の面が、前記封止樹脂の表面に露出してい
ることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the other surface on the mirror surface side of the circuit pattern made of electrolytic copper foil is exposed on the surface of the sealing resin.
側となる他方の面が、外部接続用の端子部等の所要個所
を除いて、電気的絶縁性を有する保護コーティングによ
って被覆されていることを特徴とする請求項１記載の半
導体装置。3. The other side of the circuit pattern made of electrolytic copper foil, which is a mirror surface side, is covered with a protective coating having electrical insulation properties except for required portions such as external connection terminals. The semiconductor device according to claim 1, wherein:
剥離可能に金属層が設けられた転写フィルムの金属層を
エッチングして回路パターンを形成する工程と、 該転写フィルムの回路パターンが形成された一方の面側
に半導体チップをフリップチップ法あるいはTAB方式に
よって電気的に接続して搭載する工程と、 前記転写フィルムの半導体チップが搭載された一方の面
側に、前記半導体チップおよび回路パターンを一体に樹
脂封止する工程と、 前記ベースフィルムを封止樹脂から剥離除去する工程と を含むことを特徴とする半導体装置の製造方法。4. A step of forming a circuit pattern by etching a metal layer of a transfer film having a metal layer releasably provided on a base film having electrical insulation, and forming a circuit pattern of the transfer film. A step of electrically connecting and mounting a semiconductor chip on one surface side by a flip chip method or a TAB method, and mounting the semiconductor chip and the circuit pattern on one surface side of the transfer film on which the semiconductor chip is mounted. A method of manufacturing a semiconductor device, comprising: a step of integrally sealing with a resin; and a step of peeling and removing the base film from a sealing resin.
続用の端子部等の所要個所を除いて、電気的絶縁性を有
する保護コーティングを施す工程を含むことを特徴とす
る請求項４記載の半導体装置の製造方法。5. The method according to claim 4, further comprising the step of applying a protective coating having an electrical insulation property to the other surface side of the circuit pattern except for a required portion such as a terminal portion for external connection. The manufacturing method of the semiconductor device described in the above.
て、電気的絶縁性を有するベースフィルムに電解銅箔を
鏡面側をベースフィルムに向け、粗面側を外方に向けて
接合した転写フィルムを用いることを特徴とする請求項
４または５記載の半導体装置の製造方法。6. A transfer film provided with the metal layer, wherein an electrolytic copper foil is bonded to an electrically insulating base film with the mirror side facing the base film and the rough side facing outward. 6. The method for manufacturing a semiconductor device according to claim 4, wherein said method is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1231135A JP2781019B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1231135A JP2781019B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1296198A Division JP2813587B2 (en) | 1998-01-26 | 1998-01-26 | Semiconductor device and manufacturing method thereof |
| JP1296498A Division JP2813588B2 (en) | 1998-01-26 | 1998-01-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0394460A JPH0394460A (en) | 1991-04-19 |
| JP2781019B2 true JP2781019B2 (en) | 1998-07-30 |
Family
ID=16918831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1231135A Expired - Fee Related JP2781019B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2781019B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100394565C (en) * | 1999-11-10 | 2008-06-11 | 日立化成工业株式会社 | Adhesive film for semiconductor, lead frame and semiconductor device using the same, and method of producing semiconductor device |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4140555B2 (en) * | 1994-03-18 | 2008-08-27 | 日立化成工業株式会社 | Manufacturing method of semiconductor package |
| JPH10340925A (en) * | 1997-06-09 | 1998-12-22 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JP3883784B2 (en) * | 2000-05-24 | 2007-02-21 | 三洋電機株式会社 | Plate-shaped body and method for manufacturing semiconductor device |
| JP2002076040A (en) * | 2000-08-30 | 2002-03-15 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| WO2004075293A1 (en) * | 2003-02-19 | 2004-09-02 | Hitachi Chemical Co., Ltd. | Adhesive film for semiconductor, metal sheet with such adhesive film, wiring substrate with adhesive film, semiconductor device, and method for manufacturing semiconductor device |
| JP4751585B2 (en) * | 2004-07-12 | 2011-08-17 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP5046481B2 (en) * | 2004-09-27 | 2012-10-10 | 日立電線株式会社 | Semiconductor device and manufacturing method thereof |
| JP4714042B2 (en) * | 2006-03-01 | 2011-06-29 | Ｏｋｉセミコンダクタ株式会社 | Manufacturing method of component-embedded substrate |
| JP4305502B2 (en) | 2006-11-28 | 2009-07-29 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
| JP5271949B2 (en) | 2009-09-29 | 2013-08-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59208756A (en) * | 1983-05-12 | 1984-11-27 | Sony Corp | Manufacture of semiconductor device package |
| JPH01210393A (en) * | 1988-02-19 | 1989-08-23 | Matsushita Electric Ind Co Ltd | Integrated circuit device |
-
1989
- 1989-09-06 JP JP1231135A patent/JP2781019B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100394565C (en) * | 1999-11-10 | 2008-06-11 | 日立化成工业株式会社 | Adhesive film for semiconductor, lead frame and semiconductor device using the same, and method of producing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0394460A (en) | 1991-04-19 |
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