JP2740235B2 - Electric circuit device - Google Patents
Electric circuit deviceInfo
- Publication number
- JP2740235B2 JP2740235B2 JP3428189A JP3428189A JP2740235B2 JP 2740235 B2 JP2740235 B2 JP 2740235B2 JP 3428189 A JP3428189 A JP 3428189A JP 3428189 A JP3428189 A JP 3428189A JP 2740235 B2 JP2740235 B2 JP 2740235B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- auxiliary capacitance
- contact hole
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010408 film Substances 0.000 claims description 112
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000009413 insulation Methods 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 description 11
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 239000011521 glass Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は電気回路接続の為のコンタクトホールを備え
た電気回路装置、特に薄膜トランジスタを多数備えた薄
膜トランジスタアレイの如き電気回路装置に関する。The present invention relates to an electric circuit device having a contact hole for electric circuit connection, and more particularly to an electric circuit device such as a thin film transistor array having a large number of thin film transistors.
（ロ）従来の技術 近年、多数の薄膜トランジスタ（以下、TFTと省略す
る）を液晶表示パネル基板にアレイ状に配置したアクテ
ィブマトリクス型の液晶表示装置が開発されている。(B) Conventional technology In recent years, an active matrix type liquid crystal display device in which a large number of thin film transistors (hereinafter abbreviated as TFTs) are arranged in an array on a liquid crystal display panel substrate has been developed.
この様な液晶表示装置は、各画素毎にTFTに結合され
た画素電極が設けられ、この画素電極毎にTFTを介して
画素信号が印加される構成であり、この画素信号電位保
持能力を補助するための補助容量電極を付加する事が提
案されている（例えば、特開昭54−106194号公報、特開
昭56−65174号公報）。Such a liquid crystal display device has a configuration in which a pixel electrode coupled to a TFT is provided for each pixel, and a pixel signal is applied to each pixel electrode via the TFT, and this pixel signal potential holding ability is assisted. It has been proposed to add an auxiliary capacitance electrode for performing the operation (for example, JP-A-54-106194 and JP-A-56-65174).
第４図に補助容量電極を備えた液晶表示装置の模式的
な等価回路を示す。FIG. 4 shows a schematic equivalent circuit of a liquid crystal display device having an auxiliary capacitance electrode.
同図において、画素対応でマトリクス配置された多数
のTFT［Ｔ］と、各TFT［Ｔ］に結合したLCD容量［CL］
の一方の電極をなす画素表示電極膜（50）と、この画素
表示電極膜（50）を一方の電極とする補助容量［CA］の
他方の電極をなす補助容量電極膜（20）と、該膜（20）
の外部引き出し用の端子膜［Ｘ］と、各ゲート電極ライ
ン［Ｇ］並びにドレイン電極のライン［Ｄ］とが液晶表
示装置の一方の基板に設けられる。このような基板とし
て、現在、出願人が開発中のTFTマトリクスアレイの要
部（一画素のTFT付近の断面）を第３図に示す。In the figure, a large number of TFTs [T] arranged in a matrix corresponding to pixels and an LCD capacitor [C L ] coupled to each TFT [T].
A pixel display electrode film (50) forming one of the electrodes; an auxiliary capacitance electrode film (20) forming the other electrode of the auxiliary capacitance [C A ] having the pixel display electrode film (50) as one electrode; The membrane (20)
Is provided on one substrate of the liquid crystal display device. The external lead terminal film [X], the gate electrode lines [G], and the drain electrode lines [D] are provided on one substrate. FIG. 3 shows a main part (a cross section near a TFT of one pixel) of a TFT matrix array which is currently under development by the applicant as such a substrate.
尚、第３図のLCD容量［CL］の他方の電極は図示しな
いが、液晶表示装置の他方の基板上に共通電極として形
成されている。Although not shown, the other electrode of the LCD capacitor [C L ] in FIG. 3 is formed as a common electrode on the other substrate of the liquid crystal display device.
第３図において、（10）はガラス基板、（20）はITO
からなる補助容量電極膜、（30）は酸化シリコン或は、
窒化シリコンからなる補助容量絶縁膜、（40）は金／ク
ロムの２層構造のゲート電極膜、（50）はITOからなる
画素単位の表示電極膜、（60）は酸化シリコン或は、窒
化カシリコンからなるゲート絶縁膜、（70）はアモルフ
ァスシリコンからなる半導体膜、（80），（90）はアル
ミニウムからなるソース、及びドレイン電極膜であり、
この内、ゲート電極膜（50）とゲート絶縁膜（60）と半
導体膜（70）とソース、及びドレイン電極膜（80）（9
0）でTFT［Ｔ］を構成している。更に、表示電極膜（5
0）と補助容量電極膜（20）とで補助容量［CA］が構成
される。In Fig. 3, (10) is a glass substrate, (20) is ITO
(30) is silicon oxide or
Auxiliary capacitance insulating film made of silicon nitride, (40) a gate electrode film of a two-layer structure of gold / chromium, (50) a display electrode film of a pixel unit made of ITO, (60) silicon oxide or silicon nitride A gate insulating film consisting of: (70) a semiconductor film consisting of amorphous silicon; (80) and (90) a source and drain electrode films consisting of aluminum;
Among them, the gate electrode film (50), the gate insulating film (60), the semiconductor film (70), the source and drain electrode films (80) (9
0) constitutes a TFT [T]. Furthermore, the display electrode film (5
0) and the auxiliary capacitance electrode film (20) constitute an auxiliary capacitance [C A ].
この様な積層構造体の最下層にあって補助容量［CA］
を形成するための補助容量電極膜（20）は、TFTアレイ
基板の周囲の特定箇所に於て、外部引き出し用の端子と
コンタクト（結合）する構成となっている。In the lowermost layer of such a laminated structure, the auxiliary capacitance [C A ]
The auxiliary capacitance electrode film (20) for forming the TFT is configured to contact (coupling) with a terminal for external drawing at a specific location around the TFT array substrate.
この様なコンタクト手段は、本願出願人の設計による
と、上記補助容量電極膜（20）から延長した補助容量電
極延長膜（21）が露出する位置で、補助容量絶縁膜（3
0）の延長膜（31）と上記ゲート電極膜（40）パターン
形成時に同時形成された独立の端子膜（41）との積層部
分にコンタクトホール［Ｃ］を設け、上記ソース或はド
レイン電極膜パターン形成時に同時形成された電極パタ
ーンをコンタクトメタル（81）として用いる事によっ
て、コンタクトホール内で露出した補助容量電極延長膜
と該ホール周辺の端子膜［Ｘ］との電気的結合がなされ
る。According to the design of the applicant of the present invention, such a contact means is provided at a position where the auxiliary capacitance electrode extension film (21) extending from the auxiliary capacitance electrode film (20) is exposed.
A contact hole [C] is provided in the layered portion of the extension film (31) of (0) and the independent terminal film (41) formed at the same time as the patterning of the gate electrode film (40), and the source or drain electrode film is formed. By using the electrode pattern formed at the same time as the pattern formation as the contact metal (81), electrical connection between the auxiliary capacitance electrode extension film exposed in the contact hole and the terminal film [X] around the hole is made.
しかしながら、この様な構造のコンタクト手段は、本
願出願人の製造試験によって、第２図に示す如き事故の
可能性を見いだした。However, the contact means having such a structure has found a possibility of an accident as shown in FIG. 2 by a manufacturing test of the present applicant.
即ち、第２図に示すコンタクト部分は、ガラス基板
（10）上に、補助容量電極膜（20）の延長膜（21）、補
助容量絶縁膜（30）の延長膜（31）、及び端子膜（41）
が積層された状態で、エッチングして、この補助容量絶
縁延長膜（31）と端子膜（41）とを貫通するコンタクト
ホール［Ｃ］を形成する時、補助容量絶縁延長膜（31）
のホール内壁にサイドエッチが生じる。この結果とし
て、端子膜（41）が急激な段差を形成する庇部を構成す
ることになるので、後に、ソース、及びドレイン電極膜
（80）（90）と同時にパターニングされるコンタクトメ
タル（81）が、このコンタクトホール［Ｃ］の急激な段
差によって切断される危惧があった。That is, the contact portion shown in FIG. 2 is composed of an extension film (21) of an auxiliary capacitance electrode film (20), an extension film (31) of an auxiliary capacitance insulating film (30), and a terminal film on a glass substrate (10). (41)
When the contact hole [C] penetrating the auxiliary capacitance insulating extension film (31) and the terminal film (41) is formed in a state in which the auxiliary capacitance insulating extension film (31) is laminated, the auxiliary capacitance insulating extension film (31) is formed.
Side etching occurs on the inner wall of the hole. As a result, the terminal film (41) constitutes an eave portion that forms a steep step, so that the contact metal (81) that is later patterned simultaneously with the source and drain electrode films (80) and (90) However, there is a fear that the contact hole [C] may be cut by a sharp step.
（ハ）発明が解決しようとする課題 本発明は、上述の点に鑑みてなされたものであり、上
述のコンタクトホール内でのコンタクトメタル切断を回
避できる構成のコンタクト手段を備えた電気回路装置を
提供するものである。(C) Problems to be Solved by the Invention The present invention has been made in view of the above points, and has an electric circuit device provided with a contact means having a configuration capable of avoiding cutting of a contact metal in a contact hole. To provide.
（ニ）課題を解決するための手段 発明の電気回路装置は、第２の電極と層間絶縁膜を貫
通して第１の電極膜を露出せしめるコンタクトホールを
設けると共に該コンタクトホールの内壁面に絶縁膜を埋
設被着し、該コンタクトホール底部に露出した第１の電
極とコンタクトホール外周の第２の電極とに跨る第３の
電極を被着形成したものである。(D) Means for Solving the Problems The electric circuit device of the present invention is provided with a contact hole penetrating the second electrode and the interlayer insulating film to expose the first electrode film, and is provided on the inner wall surface of the contact hole. A film is buried and applied, and a third electrode is formed so as to extend over the first electrode exposed at the bottom of the contact hole and the second electrode on the outer periphery of the contact hole.
更に、本発明の電気回路装置は、補助容量電極付きの
薄膜トランジスタアレイの周囲の特定個所に補助容量電
極膜の外部引き出し用のコンタクト手段を設けたもので
あり、該コンタクト手段は、上記補助容量電極膜から延
長した補助容量電極延長膜が露出する位置で、上記補助
容量絶縁膜の延長膜と上記ゲート電極膜パターン形成時
に同時形成された独立の端子膜との積層部分にコンタク
トホールを設けると共に該ホールの内壁面にゲート絶縁
膜の延長膜を被着せしめ、該ホール内で露出した補助容
量電極延長膜と該ホール周辺の端子膜とに跨って、上記
ソース或はドレイン電極膜パターン形成時に同時形成さ
れた独立のコンタクト金属膜を被着形成したものであ
る。Further, the electric circuit device according to the present invention is provided with a contact means for externally drawing out the auxiliary capacitance electrode film at a specific location around the thin film transistor array with the auxiliary capacitance electrode, and the contact means comprises the auxiliary capacitance electrode A contact hole is provided in a laminated portion of the extension film of the auxiliary capacitance insulating film and the independent terminal film formed simultaneously when the gate electrode film pattern is formed at a position where the auxiliary capacitance electrode extension film extended from the film is exposed. An extension film of a gate insulating film is applied to the inner wall surface of the hole, and the extension film of the auxiliary capacitance electrode exposed in the hole and the terminal film around the hole are simultaneously formed at the time of forming the source or drain electrode film pattern. The independent contact metal film thus formed is deposited.
（ホ）作用 本発明の電気回路装置によれば、コンタクトホール形
成時のホール内壁のオーバーエッチング部分を絶縁膜に
て修復した状態で、コンタクト用の金属膜を被着形成で
きるので、従来ホール内のオーバーエッチングで形成さ
れる庇部によって多発していたコンタクト用の金属膜の
段差切れ事故を回避できる。(E) Function According to the electric circuit device of the present invention, a metal film for contact can be formed while the overetched portion of the inner wall of the hole at the time of forming the contact hole is repaired with an insulating film. Can be avoided because of the overhanging portion formed by the overetching of the contact metal film, which frequently occurs due to the overhanging portion.
（ヘ）実施例 第１図に本発明の電気回路装置を液晶表示装置のTFT
マトリクスアレイ基板に採用した場合の実施例の構成を
示す。同図は前述の第２図に対比するべく、TFTマトリ
クスアレイ基板の周囲の特定箇所の断面図である。即
ち、同図は、ガラス基板（10）［材質：ガラス、膜厚:1
mm］全ての補助容量電極膜（20）に連なった補助容量延
長膜（21）［ITO、1000Å］、補助容量絶縁膜（30）が
延長した補助容量絶縁延長膜（31）［窒化シリコン、40
00Å］、ゲート電極（40）と同時形成された端子膜（4
1）［金／クロム、800Å］、ゲート絶縁膜（60）が延長
したゲート絶縁延長膜（61）［窒化シリコン、4000
Å］、ソース、及びドレイン電極膜（80）（90）と同時
形成されるコンタクトメタル（81）［アルミニウム、80
00Å］の積層構造箇所を示している。(F) Embodiment FIG. 1 shows an electric circuit device according to the present invention as a TFT of a liquid crystal display device.
1 shows a configuration of an embodiment when adopted for a matrix array substrate. This figure is a cross-sectional view of a specific portion around the TFT matrix array substrate for comparison with FIG. That is, the figure shows a glass substrate (10) [material: glass, film thickness: 1
mm] Auxiliary capacitance extension film (21) [ITO, 1000 mm] connected to all auxiliary capacitance electrode films (20), Auxiliary capacitance insulation extension film (31) with extended auxiliary capacitance insulation film (30) [Silicon nitride, 40
00Å], the terminal film (4) formed simultaneously with the gate electrode (40).
1) [Gold / Chromium, 800 mm], extended gate insulation film (61) with extended gate insulation film (60) [Silicon nitride, 4000
Å], contact metal (81) formed simultaneously with the source and drain electrode films (80) (90) [aluminum, 80
00}].
同図に於て、上記補助容量延長膜（31）を「第１の電
極」、上記補助容量絶縁延長膜（31）を「層間絶縁
膜」、上記端子膜（41）を「第２の電極」、上記ゲート
絶縁延長膜（61）を「絶縁膜」、上記コンタクトメタル
（81）を「第３の電極」と見做すと、この場合の本発明
実施例の特徴は、「第２の電極」と層間絶縁膜を貫通し
て「第１の電極」を露出せしめるコンタクトホールを設
けると共に該ホールの内壁面に「絶縁膜」を被着し、該
ホール底部に露出した「第１の電極」とコンタクトホー
ル外周の「第２の電極」とに跨る「第３の電極」を被着
形成した点にある。In the figure, the auxiliary capacitance extension film (31) is a "first electrode", the auxiliary capacitance insulation extension film (31) is an "interlayer insulating film", and the terminal film (41) is a "second electrode". If the gate insulating extension film (61) is regarded as an "insulating film" and the contact metal (81) is regarded as a "third electrode", the feature of the embodiment of the present invention in this case is "2nd electrode". A contact hole that penetrates through the “electrode” and the interlayer insulating film to expose the “first electrode”, an “insulating film” is applied to the inner wall surface of the hole, and the “first electrode” exposed at the bottom of the hole ”And a“ third electrode ”straddling the“ second electrode ”around the contact hole.
この様な第１図の本発明実施例が、第２図の従来例と
異なるところは、コンタクトホール［Ｃ］の内壁面、及
び外周縁上部に亘って絶縁膜（61）を被着した点にあ
る。しかも該絶縁膜（61）は、これ専用に新たに成膜工
数を増加せしめて形成したものでは無く、ゲート絶縁膜
（60）の形成と同時に成膜してパターニング形成したゲ
ート絶縁延長膜（61）である。The difference between the embodiment of the present invention shown in FIG. 1 and the conventional example shown in FIG. 2 is that an insulating film (61) is applied over the inner wall surface of the contact hole [C] and the upper portion of the outer peripheral edge. It is in. Moreover, the insulating film (61) is not formed by newly increasing the number of film-forming steps exclusively for this purpose, but is formed by patterning and forming at the same time as the formation of the gate insulating film (60). ).
斯るゲート絶縁延長膜（61）は、コンタクトホール
［Ｃ］内壁にオーバーエッチングによる凹部があって
も、この凹部を埋め、しかもこのホール［Ｃ］外周縁を
適度なテーパー部を持つ形で覆うことになるので、急激
な段差が緩和されている。従って、ゲート絶縁延長膜
（61）が被着されたコンタクトホール［Ｃ］上に、上記
ソース、及びドレイン電極膜（80）（90）と同時にコン
タクトメタル（81）が形成される時、コンタクトホール
［Ｃ］部分の段差が緩和されているので、このコンタク
トメタル（81）に切断事故はなく、該ホール［Ｃ］底部
で露出した補助容量絶縁延長膜（31）と該ホール外周部
の端子膜（41）とが確実に接続される。Such a gate insulating extension film (61) fills the concave portion due to over-etching on the inner wall of the contact hole [C] and covers the outer peripheral edge of the hole [C] with an appropriate tapered portion. As a result, the sudden step is reduced. Therefore, when the contact metal (81) is formed simultaneously with the source and drain electrode films (80) and (90) on the contact hole [C] on which the gate insulating extension film (61) is deposited, Since the step in the portion [C] is reduced, there is no cutting accident in the contact metal (81), and the auxiliary capacitance insulating extension film (31) exposed at the bottom of the hole [C] and the terminal film on the outer periphery of the hole [C]. (41) is securely connected.
（ト）発明の効果 本発明の電気回路装置は、第２の電極と層間絶縁膜を
貫通して第１の電極膜を露出せしめるコンタクトホール
を設けると共に該コンタクトホールの内壁面に絶縁膜を
埋設被着し、該コンタクトホール底部に露出した第１の
電極とコンタクトホール外周の第２の電極とに跨る第３
の電極を被着形成したものであるので、コンタクトホー
ル形成時のホール内壁のオーバーエッチング部分を絶縁
膜にて修復した状態で、コンタクト用の金属膜を被着形
成できる。従って、従来コンタクトホール内のオーバー
エッチングで形成される庇部によって多発していたコン
タクト用の金属膜の段差切れ事故を回避でき、この結
果、第１の電極と第２の電極との電気的接続を確保でき
る。(G) Effect of the Invention The electric circuit device of the present invention has a contact hole penetrating the second electrode and the interlayer insulating film to expose the first electrode film and burying the insulating film on the inner wall surface of the contact hole. A third electrode, which is attached to and covers the first electrode exposed at the bottom of the contact hole and the second electrode on the outer periphery of the contact hole.
Therefore, a metal film for contact can be formed while the overetched portion of the inner wall of the hole at the time of forming the contact hole is repaired with an insulating film. Therefore, it is possible to avoid the step of disconnecting the metal film for the contact which often occurs due to the eaves formed by the over-etching in the contact hole. As a result, the electrical connection between the first electrode and the second electrode can be avoided. Can be secured.
さらに、アクティブマトリクス型の液晶表示装置のTF
Tマトリクスアレイ基板周囲の特定箇所において、本発
明を補助容量電極の外部への引き出し手段に採用すれ
ば、このTFTマトリクスアレイに本来必要であった工程
を増加せしめること無く確実なコンタクトを実現でき
る。In addition, TF of active matrix type liquid crystal display device
If the present invention is adopted as a means for extracting the auxiliary capacitance electrode to the outside at a specific location around the T matrix array substrate, reliable contact can be realized without increasing the steps originally required for the TFT matrix array.
第１図は本発明の電気回路装置をTFTマトリクスアレイ
基板に採用した場合の要部断面図、第２図は従来のTFT
マトリクスアレイ基板の要部断面図、第３図はTFTマト
リクスアレイ基板のTFTの断面図、第４図はTFTマトリク
スアレイ基板を持つ液晶表示装置の回路図である。 （10）……ガラス基板、 （21）……補助容量延長膜、 （31）……補助容量絶縁延長膜、 （41）……端子膜、 （61）……ゲート絶縁延長膜、 （81）……コンタクトメタル。FIG. 1 is a sectional view of a main part when an electric circuit device according to the present invention is used for a TFT matrix array substrate, and FIG. 2 is a conventional TFT.
FIG. 3 is a sectional view of a TFT of the TFT matrix array substrate, and FIG. 4 is a circuit diagram of a liquid crystal display device having the TFT matrix array substrate. (10) ... glass substrate, (21) ... auxiliary capacitance extension film, (31) ... auxiliary capacitance insulation extension film, (41) ... terminal film, (61) ... gate insulation extension film, (81) ...... Contact metal.
Claims (2)
１の電極上に層間絶縁膜を介して形成された第２の電極
とを備え、これら上記第１及び第２の電極を電気的に接
続する電気回路装置に於て、 上記第２の電極と上記層間絶縁膜を貫通するコンタクト
ホールを設けると共に該コンタクトホールの内壁面に絶
縁膜を埋設し、該コンタクトホール底部に露出した第１
の電極とコンタクトホール外周の第２の電極とに跨る第
３の電極を被着形成してなる事を特徴とする電気回路装
置。A first electrode provided on an insulating substrate and a second electrode formed on the first electrode with an interlayer insulating film interposed therebetween; and the first and second electrodes are electrically connected to each other. A contact hole penetrating the second electrode and the interlayer insulating film, an insulating film is buried on an inner wall surface of the contact hole, and a second electrode exposed at the bottom of the contact hole. 1
An electric circuit device, wherein a third electrode is formed so as to extend over the first electrode and a second electrode around the contact hole.
絶縁膜、ゲート電極膜並びに表示画素電極、ゲート絶縁
膜、半導体膜、ソース並びにドレイン電極膜の積層構造
をなす薄膜トランジスタアレイを備え、更に該薄膜トラ
ンジスタアレイの周囲の特定個所に上記補助容量電極膜
の外部引き出し用のコンタクト手段を設けた電気回路装
置に於て、 上記コンタクト手段は、上記補助容量電極膜から延長し
た補助容量電極延長膜が露出する位置で、上記補助容量
絶縁膜の延長膜と上記ゲート電極膜パターン形成時に同
時形成された独立の端子膜との積層部分にコンタクトホ
ールを設けると共に該ホールの内壁面にゲート絶縁膜の
延長膜を被着せしめ、該ホール内で露出した補助容量電
極延長膜と該ホール周辺の端子膜とに跨って、上記ソー
ス或はドレイン電極膜パターン形成時に同時形成された
独立のコンタクト金属膜を被着形成してなる事を特徴と
する電気回路装置。2. A thin film transistor array having a laminated structure of an auxiliary capacitance electrode film, an auxiliary capacitance insulation film, a gate electrode film, a display pixel electrode, a gate insulation film, a semiconductor film, a source and a drain electrode film on an insulating substrate, Further, in an electric circuit device provided with contact means for externally drawing out the auxiliary capacitance electrode film at a specific location around the thin film transistor array, the contact means comprises an auxiliary capacitance electrode extension film extending from the auxiliary capacitance electrode film. Is provided, a contact hole is provided in a laminated portion of the extension film of the auxiliary capacitance insulating film and the independent terminal film formed simultaneously with the formation of the gate electrode film pattern, and the gate insulating film is formed on the inner wall surface of the hole. An extension film is applied, and the source or the source is extended over the auxiliary capacitance electrode extension film exposed in the hole and the terminal film around the hole. An electric circuit device comprising an independent contact metal film formed simultaneously with the formation of a drain electrode film pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3428189A JP2740235B2 (en) | 1989-02-14 | 1989-02-14 | Electric circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3428189A JP2740235B2 (en) | 1989-02-14 | 1989-02-14 | Electric circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02212818A JPH02212818A (en) | 1990-08-24 |
| JP2740235B2 true JP2740235B2 (en) | 1998-04-15 |
Family
ID=12409779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3428189A Expired - Fee Related JP2740235B2 (en) | 1989-02-14 | 1989-02-14 | Electric circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2740235B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0499979A3 (en) | 1991-02-16 | 1993-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
-
1989
- 1989-02-14 JP JP3428189A patent/JP2740235B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02212818A (en) | 1990-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100333273B1 (en) | The array substrate of TFT type liquid crystal display device and a method of fabricating the same | |
| US5828433A (en) | Liquid crystal display device and a method of manufacturing the same | |
| US6323931B1 (en) | LCD with external circuit having anti-short-circuit pattern and particular structure | |
| US6642086B2 (en) | Method for fabricating thin film transistor array substrate for liquid crystal display | |
| JP2963529B2 (en) | Active matrix display device | |
| US6011608A (en) | Liquid crystal display panel wherein inorganic film is formed over an inorganic insulating film overlying wirings extending across seal area | |
| JP4211855B2 (en) | Liquid crystal display device and manufacturing method thereof | |
| JP2000284326A (en) | Liquid crystal display device and manufacturing method thereof | |
| JP2000162646A (en) | Method of manufacturing thin film transistor substrate for liquid crystal display device | |
| JP3053848B2 (en) | Active matrix substrate | |
| JPH06289413A (en) | Liquid crystal display device | |
| JP5040222B2 (en) | Display device | |
| JPH04253342A (en) | Thin film transistor array substrate | |
| JPH11352515A (en) | Liquid crystal display device and its production | |
| JP2740235B2 (en) | Electric circuit device | |
| JPH10325967A (en) | Liquid crystal display device and its manufacture | |
| JP3329273B2 (en) | Display device and manufacturing method thereof | |
| JP2001272698A (en) | Liquid crystal display device and manufacturing method therefor | |
| JPS61173286A (en) | Display unit | |
| JPH11326941A (en) | Active matrix display device | |
| JP2937126B2 (en) | Thin film transistor array substrate and method of manufacturing the same | |
| JPH07120790A (en) | Active matrix substrate and manufacturing method thereof | |
| JP4075220B2 (en) | Display panel and manufacturing method thereof | |
| CN100447642C (en) | Pixel structure and manufacturing method thereof | |
| JP2000029071A (en) | Array substrate for display device and its production |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |