CN100447642C - Pixel structure and manufacturing method thereof - Google Patents

Abstract

A pixel structure and its manufacturing method. When forming data lines and source/drain electrodes, a conductive layer is formed at the same time. The formed conductive layer has a coupling part and a connecting part, and the coupling part is used as a pixel storage capacitor. The upper electrode, and the connecting part connects the coupling part and the drain together. Afterwards, a contact window opening is defined above the connecting portion, so that the subsequently formed pixel electrode can electrically contact with the connecting portion of the conductive layer through the contact window opening. In this way, the pixel electrode, the conductive layer (including the coupling portion) and the drain are electrically connected to each other. Since the contact window of the present invention is not formed directly above the pixel storage capacitor, even though the etching process of the contact window may etch through the gate insulating layer, it will not cause leakage of the pixel storage capacitor.

Description

Pixel structure and manufacturing method thereof

technical field

The present invention relates to a pixel structure of a thin film transistor array (Thin Film Transistor Array) substrate and a manufacturing method thereof, and in particular to a pixel structure capable of preventing leakage of pixel storage capacitors and a manufacturing method thereof.

Background technique

The thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer, wherein the thin film transistor array substrate is composed of a plurality of thin film transistors arranged in an array and a pixel electrode ( Pixel Electrode) to form multiple pixel structures. The above thin film transistor includes a gate, a channel layer, a drain and a source, which are used as switching elements of the liquid crystal display unit.

Please refer to FIG. 1 , which is a schematic top view of a pixel structure of a conventional thin film transistor array substrate. The pixel structure is disposed on a substrate (not shown), which includes a scan line 102 , a data line 104 , a thin film transistor 130 , a pixel storage capacitor 116 and a pixel electrode 112 .

Wherein, the thin film transistor 130 includes a gate 106, a channel layer 108 and a source/drain 110a/110b, and the gate 106 is electrically connected to the scanning line 102, the source 110a is electrically connected to the data line 104, and the drain 110b It is electrically connected to the pixel electrode 112 through the contact window 114 .

In addition, the pixel storage capacitor 116 includes a lower electrode 118 , an upper electrode 120 and a capacitive dielectric layer between the lower electrode 118 and the upper electrode 120 , and the upper electrode 120 is electrically connected to the pixel electrode 112 through the contact window 122 . Wherein, the lower electrode 118 is a common line, which belongs to the first metal layer ( M1 ) like the scan line 102 and the gate 106 . The upper electrode 120 and the data line 104 and the source/drain 110 a / 110 b also belong to the second metal layer ( M2 ). A gate insulating layer (not shown) is arranged between the first metal layer and the second metal layer, and a protective layer (not shown) is arranged between the second metal layer and the pixel electrode 112 .

It is particularly worth mentioning that generally two edges of the substrate are provided with terminal portions (not shown) for electrical connection with the driving circuit, wherein the terminal portion is a part of the first metal layer (M1), and The data lines 104 and the scan lines 102 extending to the edge of the substrate are electrically connected to the terminals.

In order to expose the terminal portion so that it can be electrically connected with the driving circuit, it is necessary to etch away the gate insulating layer and the protection layer above the terminal portion. However, for the contact windows 114 and 122, only the protective layer needs to be etched away, especially for the contact window 122 on the pixel storage capacitor 116, only the protective layer can be etched away, and this place must be kept. The gate insulating layer is used to avoid leakage between the upper and lower electrodes 118 and 120 of the pixel storage capacitor 116 . Therefore, the etching step of the protective layer and the gate insulating layer is a critical and difficult technique for the manufacture of thin film transistors.

In the prior art, in order to overcome the above problems, one method is to form an additional layer of amorphous silicon layer under the contact window, which is defined at the same time as the channel layer of the thin film transistor. In other words, the amorphous silicon layer is used as a barrier layer to prevent the gate insulating layer under the contact window from being etched through. However, this method must adjust the etch selectivity ratio between the amorphous silicon and the gate insulating layer, so it is not easy to implement.

Another existing method is to first form an opening in the lower electrode under the contact window, that is, hollow out the place corresponding to the lower electrode under the contact window, so that even if the gate insulating layer under the contact window is Etching will not cause leakage between the upper electrode and the lower electrode. However, this method still has its disadvantages, that is, after digging the openings in the lower electrodes, it is still difficult to align the openings of the contact windows with the openings in the lower electrodes.

Contents of the invention

Therefore, the purpose of the present invention is to provide a pixel structure and its manufacturing method to solve the problem of etching the gate insulating layer and the protective layer in the manufacturing of thin film transistors in the prior art, which is prone to cause the pixel storage capacitor of the pixel structure to burn. , The leakage problem generated by the lower electrode.

The present invention proposes a pixel structure, which includes a scanning line, a common line, a gate insulating layer, a data line, a switching element (such as a thin film transistor), a conductive layer, a protective layer, and a flat layer , a contact window and a pixel electrode. Wherein, the scanning line is arranged on a substrate, the common line is also arranged on the substrate, and the common line is arranged parallel to the scanning line, and the common line is used as the lower electrode of the pixel storage capacitor. The gate insulating layer is disposed on the substrate, covering the scanning line and the common line. The data lines are configured on the gate insulating layer. In addition, the switch element is arranged on the substrate, and the switch element is electrically connected with the scan line and the data line. In addition, the conductive layer is disposed on the gate insulating layer, and the conductive layer has a coupling part and a connecting part, wherein the coupling part is located above the common line, which is used as the upper electrode of the pixel storage capacitor, and the connecting part connects the coupling part connected to the switching element. In a preferred embodiment, the connection part of the conductive layer is designed as a multi-channel structure, which includes a first part used to connect with the switching element, a second part used to connect with the coupling part, and a channel between the first part and the second part. The third part between the parts, the third part is the design of the multi-channel structure. The protective layer covers the data line, the switch element and the conductive layer, and the flat layer is disposed on the protective layer. In addition, the contact window is configured in the planar layer and the protective layer on the connecting portion. In a preferred embodiment, the contact window is configured in the planar layer and the protective layer on a channel in the multi-channel structure of the connecting portion. The pixel electrodes are disposed on the surface of the planar layer, wherein the pixel electrodes are electrically connected to the connecting portion of the conductive layer through the contact window. Since the switching element is connected to the conductive layer, and the pixel electrode is electrically connected to the connecting portion of the conductive layer, the pixel electrode, the entire conductive layer (including the coupling portion) and the switching element are electrically connected to each other.

The present invention also proposes a method for manufacturing a pixel structure. In this method, a gate, a scan line electrically connected to the gate, and a common line parallel to the scan line are first formed on a substrate, and the common line is subsequently used as a pixel. The lower electrode of the storage capacitor. Next, a gate insulating layer is formed on the substrate to cover the gate, the scanning line and the common line. Afterwards, a channel layer is formed on the gate insulating layer above the gate. Subsequently, a data line and a conductive layer are formed on the gate insulating layer, and a source/drain is formed on the channel layer at the same time, wherein the gate, the channel layer, and the source/drain form a thin film transistor, and the data line Electrically connected to the source. In addition, the formed conductive layer has a coupling part and a connecting part, wherein the coupling part is formed above the common line, which is used as the upper electrode of the pixel storage capacitor, and the connecting part of the conductive layer connects the coupling part with the thin film transistor connected to the drain. In a preferred embodiment, the connection part of the conductive layer is designed as a multi-channel structure, which includes a first part used to connect to the drain, a second part used to connect to the coupling part, and a channel between the first part and the second part. The third part between the parts is designed as a multi-channel structure, and the subsequently formed contact window opening will expose one of the channels of the third part. Afterwards, a protective layer is formed on the substrate to cover the data line, the conductive layer and the thin film transistor, and a flat layer is formed on the protective layer. Next, a contact window opening is formed in the flat layer and the passivation layer to expose the connection portion of the conductive layer. In a preferred embodiment, the formed contact window opening exposes one of the channels of the connection portion. Subsequently, a pixel electrode is formed on the surface of the planar layer, wherein the pixel electrode is electrically connected to the connection portion of the conductive layer through the opening of the contact window. Since the drain is connected to the conductive layer, and the pixel electrode is electrically connected to the conductive layer, the pixel electrode, the conductive layer, and the drain are electrically connected to each other.

Since the pixel electrode of the pixel structure of the present invention is electrically connected to the drain electrode and the upper electrode of the pixel storage capacitor through the same contact window, the pixel structure of the present invention is different from the existing pixel structure. The design of the structure.

Since the contact window of the pixel structure of the present invention is not arranged above the pixel storage capacitor, even if the etching step of the protective layer and the gate insulating layer will etch through the gate insulating layer, it will not cause the upper and lower of the pixel storage capacitor. Leakage occurs between the lower electrodes.

Description of drawings

FIG. 1 is a schematic top view of a pixel structure in an existing thin film transistor array substrate;

2 is a schematic top view of a pixel structure in a thin film transistor array substrate according to a preferred embodiment of the present invention;

Fig. 3 is the schematic sectional view of Fig. 2 by I-I '; And

FIG. 4 is a top view of the conductive layer in FIG. 2 .

Detailed ways

In order to make the above and other objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

Please refer to FIG. 2 and FIG. 3, FIG. 2 is a top view of a pixel structure in a thin film transistor array substrate according to a preferred embodiment of the present invention, and FIG. 3 is a schematic cross-sectional view from I-I' in FIG. 2. The manufacturing method of the pixel structure of the present invention firstly provides a substrate 200, wherein the substrate 200 is, for example, a glass substrate or a plastic substrate. Afterwards, a gate 206, a scan line 202 electrically connected to the gate 206, and a common line 218 parallel to the scan line 202 are formed on the substrate 200, and the common line 218 is subsequently used as the lower electrode of the pixel storage capacitor 216 . The gate 206 , the scan line 202 and the common line 218 belong to the first metal layer ( M1 ).

Here, the first metal layer further includes a plurality of terminal portions (not shown), which are formed at two edges of the substrate 200 , and the scan lines 202 formed above and the data lines formed subsequently extend to the substrate 200 The edge of each will be electrically connected with the terminal part.

Next, a gate insulating layer 205 is formed on the substrate 200 to cover the first metal layer (including the gate 206 , the scanning line 202 and the common line 218 ). In a preferred embodiment, the material of the gate insulating layer 205 is, for example, silicon nitride or silicon oxide.

Afterwards, a channel layer 208 is formed on the gate insulating layer 205 above the gate 206 . In a preferred embodiment, the material of the channel layer 208 is, for example, amorphous silicon, and an ohmic contact layer (not shown) is formed on the surface of the channel layer 208 to improve the connection between the channel layer 208 and the subsequently formed source electrode. / Electrical contact between the drain.

Subsequently, a data line 204 and a conductive layer 250 are formed on the gate insulating layer 205 (as shown in FIG. 250 and source/drain 210a/210b belong to the second metal layer (M2). Wherein, the source 210a is electrically connected to the data line 204, and the gate 206, the channel layer 208 and the source/drain 210a/210b form a thin film transistor.

The conductive layer 250 formed above has a coupling portion 220 and a connecting portion 240, wherein the coupling portion 220 is formed above the common line 218, which serves as the upper electrode of the pixel storage capacitor 216, and the connecting portion 240 connects the coupling portion 220 to the drain. Pole 210b is connected.

Especially, in a preferred embodiment, the connection portion 240 of the conductive layer 250 can be defined as a multi-channel structure. As shown in FIG. The second part 226b connected, and the third part 224 between the first part 226a and the second part 226b, the third part 224 is a multi-channel structure, three channels 224a, 224b, 224c are shown in the figure as an example To illustrate, but not to limit the invention. The purpose of making such a multi-channel structure is that when the opening of the contact window is subsequently defined, it will be defined above one of the channels, for example, above the middle channel 224b. The other passages 224a, 224c serve as conduction carriers. If one of the passages (such as the passage 224a) fails to conduct due to manufacturing factors or other factors, the remaining passages (such as the 224c) can continue Take on the task of the conduction carrier without making the entire pixel structure inoperable due to the above reasons.

It is particularly worth mentioning that a light-shielding layer 222 can be formed under the third portion 224 of the connecting portion 240, and this light-shielding layer 222 is part of the first metal layer. , the scan line 202 and the common line 218 are simultaneously defined. The purpose of forming the light-shielding layer 222 here is to shield the light scattering phenomenon caused by the subsequent formation of the contact window thereon.

After forming the second metal layer (including the data line 204, the conductive layer 250 and the source/drain 210a/210b), a protection layer 211 is formed on the substrate 200 to cover the second metal layer, wherein the protection layer 211 The material is, for example, silicon nitride or silicon oxide. Subsequently, a flat layer 213 is formed on the protection layer 211 , wherein the material of the flat layer 213 is, for example, an organic photosensitive material.

Afterwards, the planarization layer 213 and the passivation layer 211 are patterned to form a contact window opening 228 in the planarization layer 213 and the passivation layer 211 to expose a part of the connection portion 240 of the conductive layer 250 . In a preferred embodiment, the contact window opening 228 exposes one of the channels 224b of the connecting portion 240 . Here, if the second metal layer uses a titanium/aluminum double-layer metal layer as its material, then during the etching process for defining the contact window opening 228, it may be desirable to remove the aluminum layer on the upper layer of the channel 224b at the same time, leaving the lower layer Therefore, the thickness of the channel 224b in FIG. 3 is obviously smaller than that of the channels 224a and 224c.

It is particularly worth mentioning that since the contact opening 228 of the present invention is not defined directly above the pixel storage capacitor 216, even if the etching step for defining the contact opening 228 will etch through the gate insulating layer 205, the No leakage will be generated between the upper and lower electrodes 218 and 220 of the pixel storage capacitor 216 . Moreover, if this etching step will etch through the gate insulating layer 205, since the light-shielding layer 222 is disposed under the contact window opening 228, which is a film layer that is not electrically connected to other conductive material layers, it still does not Will have adverse effects on the entire component.

Afterwards, a pixel electrode 212 is formed on the surface of the planar layer 213 , wherein the pixel electrode 212 is electrically connected to the connection portion 240 (ie, the channel 224 b ) of the conductive layer 250 through the contact window opening 228 .

Since the coupling portion 220 of the conductive layer 250 is connected to the drain 210b of the thin film transistor 230 through the connection portion 240, and the pixel electrode 212 is electrically connected to the connection portion 240, the pixel electrode 212, the conductive layer 250 (including The coupling part 220 and the connecting part 240) and the drain 210b of the thin film transistor 230 are electrically connected to each other.

The pixel structure of the present invention includes a scanning line 202, a common line 218, a gate insulating layer 205, a data line 204, a switching element 230 (such as a thin film transistor), a conductive layer 250, a protective layer 211, a The flat layer 213 , a contact window 228 and a pixel electrode 212 .

Wherein, the scan line 202 is disposed on a substrate 200 , and the common line 218 is also disposed on the substrate 200 , which serves as the lower electrode of the pixel storage capacitor 216 , and the common line 218 is disposed parallel to the scan line 202 .

The gate insulating layer 205 is disposed on the substrate 200 and covers the scan lines 202 and the common lines 218 . The data line 204 is disposed on the gate insulating layer 205 .

In addition, the switching element 230 is, for example, a thin film transistor, which is disposed on the substrate 200. The thin film transistor 230 has a gate 206, a channel layer 208, and a source/drain 210a/210b, wherein the gate 206 is connected to the scan line 202 is electrically connected, the channel layer 208 is disposed on the gate insulating layer 205 above the gate 206 , the source/drain 210 a / 210 b is disposed on the channel layer 208 , and the source 210 a is electrically connected to the data line 204 .

In addition, the conductive layer 250 is disposed on the gate insulating layer 205, and the conductive layer 250 has a coupling portion 220 and a connecting portion 240, wherein the coupling portion 220 is located above the common line 218, which serves as the upper electrode of the pixel storage capacitor 216, The connection part 240 connects the coupling part 220 and the drain 210 b of the thin film transistor 230 . In the preferred embodiment shown in FIG. 4, the connection part 240 of the conductive layer 250 is, for example, a multi-channel structure, and the connection part 240 includes a first part 226a connected to the drain 210b, a second part 226b connected to the coupling part 220, and a bit The third portion 224 between the first portion 226a and the second portion 226b is designed as a multi-channel structure. Moreover, a light-shielding layer 222 is further configured under the third portion 224 of the connection portion 240, and the light-shielding layer 222 belongs to the first metal layer like the gate 206, the scanning line 202 and the common line 218, and the light-shielding layer 222 It is used to shield the subsequent light scattering phenomenon caused by the contact window formed thereon.

Furthermore, the protective layer 211 covers the data line 204 , the thin film transistor 230 and the conductive layer 250 . In addition, the flat layer 213 is disposed on the protective layer 211 .

The contact window 228 is disposed in the flat layer 213 and the protection layer 211 above the connection portion 240 , and the contact window 228 is electrically connected to the connection portion 240 of the conductive layer 250 . In a preferred embodiment, the contact window 228 is disposed in the planar layer 213 and the protection layer 211 above the channel 224 b of the connecting portion 240 , and is electrically connected to the channel 224 b of the connecting portion 240 .

The pixel electrode 212 is disposed on the surface of the planar layer 213, wherein the pixel electrode 212 is electrically connected to the connection portion 240 of the conductive layer 250 through the contact window 228. More specifically, the pixel electrode 212 is connected to the connection portion 240 through the contact window 228. The channel 224b is electrically connected. Through the electrical contact between the channel 224 b and the pixel electrode 212 , the pixel electrode 212 and the entire conductive layer 250 are electrically connected to each other. In addition, since the drain electrode 210b is connected to the conductive layer 250, the pixel electrode 212, the conductive layer 250, and the drain electrode 210b are electrically connected to each other.

Therefore, in the pixel structure of the present invention, the pixel electrode, the drain electrode, and the upper electrode of the pixel storage capacitor are electrically connected through the same contact window, so the pixel structure of the present invention is different from the existing one. Pixel structured design.

In addition, since the contact window of the pixel structure of the present invention is not arranged above the pixel storage capacitor, even if the etching step of the protective layer and the gate insulating layer will etch through the gate insulating layer, it will not cause damage to the pixel storage capacitor. Leakage occurs between the upper and lower electrodes.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection of the invention should be defined by the claims.

Claims (10)

1. A pixel structure, comprising: a scanning line configured on a substrate; A common line, configured on the substrate, serves as a lower electrode of a pixel storage capacitor; a gate insulating layer, disposed on the substrate, covering the scanning line and the common line; a data line configured on the gate insulating layer; a switch element configured on the substrate, wherein the switch element is electrically connected to the scan line and the data line; A conductive layer is disposed on the gate insulating layer, wherein the conductive layer has a coupling portion and a connecting portion, the coupling portion is located above the common line, and serves as the upper electrode of the pixel storage capacitor, and the connecting portion connecting the coupling part with the switching element; a protective layer covering the data line, the switch element and the conductive layer; a contact window disposed in the protection layer above the connecting portion; and a pixel electrode disposed on the protective layer, wherein the pixel electrode is electrically connected to the switching element and the coupling portion of the conductive layer through the contact window; It is characterized in that the connecting part of the conductive layer is a multi-channel structure, which includes: a first part connected to the coupling part; a second part connected to the switching element; and a third part, located between the first part and the second part, and the third part has a plurality of channels; Wherein, the contact window is configured in the protective layer above one of the channels in the third portion, and is electrically connected with the channel. 2 . The pixel structure according to claim 1 , wherein a light-shielding layer is further disposed under the connecting portion corresponding to the position where the contact window is disposed. 3 . 3. The pixel structure as claimed in claim 1, wherein a flat layer is disposed between the protective layer and the pixel electrode. 4. The pixel structure according to claim 1, wherein the switch element is a thin film transistor comprising: a gate electrically connected to the scanning line; a channel layer disposed on the gate insulating layer above the gate; and A source and a drain are arranged on the channel layer, and the source is electrically connected to the data line, and the drain is connected to the connection part of the conductive layer. 5. The pixel structure according to claim 1, wherein the scan line is arranged parallel to the common line. 6. A method for manufacturing a pixel structure, comprising: forming a gate, a scanning line electrically connected to the gate, and a common line on a substrate; forming a gate insulating layer on the substrate to cover the gate, the scanning line and the common line; forming a channel layer on the gate insulating layer above the gate; A data line and a conductive layer are formed on the gate insulating layer, and a source and a drain are formed on the channel layer at the same time, wherein the data line is electrically connected to the source, and the conductive layer has a a coupling part and a connecting part, the coupling part is formed above the common line, the connecting part connects the coupling part and the drain, and the gate, channel layer, source and drain form a thin film transistor; forming a protective layer on the substrate to cover the data line, the conductive layer and the thin film transistor; forming a contact opening in the passivation layer exposing the connection portion of the conductive layer; and forming a pixel electrode on the protective layer, wherein the pixel electrode is electrically connected to the conductive layer through the contact window opening; It is characterized in that the connecting part of the conductive layer is a multi-channel structure, which includes: a first part connected to the coupling part; a second part connected to the thin film transistor; and a third part, located between the first part and the second part, and the third part has a plurality of channels; Wherein, the contact window is configured in the protective layer above one of the channels in the third portion, and is electrically connected with the channel. 7 . The method for manufacturing the pixel structure according to claim 6 , wherein a light-shielding layer is further formed under the connection portion under the contact window. 8 . 8 . The method of manufacturing the pixel structure according to claim 7 , wherein the light-shielding layer is a part formed simultaneously when forming the gate, the scanning line and the common line. 9. The method for manufacturing a pixel structure as claimed in claim 6, wherein before forming the pixel electrode, a flat layer is further formed on the protective layer. 10 . The method for manufacturing a pixel structure as claimed in claim 6 , wherein the common line is formed parallel to the scan line. 11 .

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