JP2738711B2 - Electronic component connection structure and electronic device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and structure for connecting electronic components and an electronic device using the same, and more particularly to a method for connecting electronic components having a large number of fine connection terminals such as LSI chips to a wiring board in a flexible structure. The present invention relates to a preferred method and structure for connecting electronic components and the structure of an electronic device using the method. [Prior Art] Conventionally, there are three electrical connection methods for LSI chips: (1) wire bonding, (2) tape carrier bonding (or TAB: Tape Automated Bonding), and (3) flip chip bonding. (Reference 1:
Nihon et al. And two others, Semiconductor Handbook, P128, Science Horum Co., Ltd., 1986, 9, 25). Among the three connection methods, the methods (1) and (2) can be applied only to a chip having a structure in which the input / output terminals of the LSI chip are located at the periphery of the chip (see Table 3). 1). Details of the reason will be described later. On the other hand, the flip-chip bonding method (3) uses LSI
The present invention can also be applied to a chip having a structure in which connection terminals are provided over the entire surface of the chip including the central portion as well as the peripheral portion of the chip (hereinafter, referred to as a lattice-like terminal arrangement). In this method, a solder bump having a height of about 100 to 125 μm is provided on the surface of the terminal of the LSI chip to be connected, placed on this chip wiring board, and the solder is reheated and melted for connection. This method is a C-4 method (Solid Logic Technolo
gy) or CCB (Controlled Collapse Bonding)
It is known by its abbreviation. Fig. 25 (Literature 2: Honda et al., 3 persons, High-density mounting handbook, pp. 238, 1986) shows a principle schematic diagram of the connection mechanism of the CCB method. In this CCB method, the connection medium (in this case, solder) does not extend (exit) beyond the horizontal (horizontal) size of the LSI chip. In addition, one connection medium (solder) does not spread so much in the horizontal direction. For this reason, it is advantageous to connect and mount a large number of LSI chips having a lattice-like terminal arrangement continuously. As an example of chip connection and mounting by CCB method,
Ultra-high-speed computers that require a large number and high-density mounting,
For example, IBM's TCM (Thermal Conduction Medule) can be mentioned (from FIG. 24, Document 2, P240). As in the above example, electronic computers and high-end electronic devices require mounting of an LSI chip having a large number of connection terminals. Particularly in recent years, as shown in FIG. 23 (from Document 1),
The number of terminals of logic LSIs is increasing remarkably, and they are becoming a chip structure with a lattice-like terminal arrangement due to high-density arrangement and power supply characteristics. As described above, logic LSs are arranged in a grid and at a high density.
As described above, the I-chip cannot be applied to the wire bonding method or the tape carrier bonding method (hereinafter, TAB method) for the following reasons. The wire bonding method is a method in which a thin Au or Al wire is drawn out from the terminal of the LSI chip to the outside periphery thereof, as shown in FIG. For this reason, (1) a space is required on the outer periphery of the chip for pulling out and connecting leads (wires), and basically an extra space for connecting must be prepared. (2)
The leads are connected by a device called a wire bonder. The lead wires (wires) are bare wires having no insulating coating. When a large number of these wires are connected up to the terminal at the center of the chip, the wires come into contact with each other. For this reason, the wire bonding method is unsuitable for connection of a chip having a structure having a high-density and lattice-like terminal arrangement like the above-described logic LSI chip. Further, in the TAB method, as shown in FIG. 21 (from P1, P277), a wiring lead is provided on a film (carrier) and a chip is connected to the film through the lead. In the TAB method, an extra lead portion is required as a bonding margin to fix the lead wire to the film, and there is a problem in shortening the lead length. That is, in the conventional film carrier, an intermediate portion between the outer lead and the inner lead is made longer, and the portion is fixed and supported on the film base.
The inner leads are wired directly inward. For this reason, LSIs that can be connected to this are only suitable for memories with relatively few terminals, such as those with terminals arranged only in the peripheral area.
It was limited to LSI chips. However, logic LSI chips have an extremely large number of terminals (more than 500 on about 10 mm ^square ). Also, as described above, the terminals are arranged not only in the peripheral portion of the LSI chip but also in a lattice pattern uniformly up to the central portion. For this reason, a logic LSI chip having a lattice terminal arrangement cannot be connected in a shape in which the inner leads are linearly wired inward in a plane as in the TAB method. The shortcomings of the above two methods can be summarized as follows: (1) The extra space required is larger than the area occupied by the LSI chip.
(2) It cannot be applied to a chip having a structure having terminals in a grid pattern up to the center of the chip such as a logic LSI chip. For the above reasons, the method of connecting and mounting LSI chips with a terminal structure arranged in a grid-like and high-density manner, such as a logic LSI chip, in a high-density and compact manner is described in the CCB described earlier.
Only the flip chip bonding method typified by the method. However, in a flip chip bonding method such as a CCB method, a direct connection is made with a ball-shaped solder, and is basically a connection method having a rigid (hard) structure. Therefore, in recent years, inconvenience has occurred in this method. The situation will be described below. In recent years, in the field of high-performance electronic equipment such as electronic computers, there has been a demand for the development of a flexible chip connection technology for mounting an LSI chip. In this field, the rigid connection method such as the CCB method described above can no longer satisfy the demand. The reason why the above-mentioned flexible LSI chip connection method is required is because it is related to the operation speed which is one of the most important performances of an electronic computer, for example. That is, the operation speed is determined by the performance of the LSI and the performance of the wiring board for mounting and mounting the LSI when viewed from the hardware (device) side of the computer. Looking at recent trends in this wiring board, multilayer wiring boards made of ceramics (alumina, mullite, etc.) using W (tungsten) or Mo (molybdenum) as a wiring material have been developed and put into practical use. This is effective in connecting and mounting LSI chips at a high density and shortening the total wiring length of the increasing wiring. However, there are the following unsatisfactory points in the transmission performance of electric signals. (1) Since the ceramic substrate generally has a large electric permittivity (alumina ε: 9 to 10), parasitic electrification occurs at an interface where the ceramic substrate and the wiring come into contact with each other, which causes a delay in the transmission speed of the electric pulse signal. (2) W, Mo, etc., which are wiring conductor materials, have a higher electric resistance than other metal conductors, for example, Cu (copper). Therefore, the waveform of the electric pulse signal is deteriorated. As a result, it is difficult to reduce the time between transmitted pulses, which is a factor that hinders the transmission capacity and speed of the pulse signal. Therefore, in order to eliminate the above-mentioned disadvantages, recently, a wiring board using Cu or the like as a wiring material and an organic substance having a small electric permittivity such as a polyimide resin (ε3) as a substrate material will be developed or used. Tend to be. However, the above-mentioned high-performance wiring board has a larger linear thermal expansion coefficient than ceramics such as alumina, and has a difference in thermal expansion coefficient from Si, which is the main component of the LSI chip (hereinafter α difference).
Is as large as 100 to 130 × 10 ^-7 / ° C. Therefore, when the LSI chip is directly soldered to the wiring board as in the conventional LSI chip connection method, the following inconvenience occurs. That is, when an LSI chip is fixed to a wiring board using an organic substance and Cu, a large difference in α results in thermal stress in the solder connection, and the solder connection is destroyed due to the distortion due to the thermal stress. Results in disconnection. Therefore, as described above,
In the case of connecting LSI chips, a method capable of absorbing or relaxing thermal stress distortion caused by the α difference between them, that is, a method of connecting an LSI chip having a flexible structure is required. Even if a ceramic wiring board as in the related art is used, for example, the thermal expansion coefficient of an alumina ceramic wiring board (60 to 65 × 10 ⁻⁷ / ° C.) is the same as that of the LSI chip (30 ×
10 ⁻⁷ / ° C). In particular, with the recent increase in the size of LSI chips (10 mm ^□ → 16 mm ^□ ), thermal stress distortion due to α difference tends to increase. is there. For this reason, even when an LSI chip is connected to a conventional ceramic wiring substrate, an LSI chip connection method having a structure capable of absorbing or mitigating distortion caused by thermal stress is required. The above situation is summarized in Fig. 20. In FIG. 20, the vertical axis represents the size (size) of the LSI chip, the horizontal axis represents the α difference between the wiring substrate and the LSI chip (main component Si), and the oblique line in the figure represents the life in the CCB connection method. The limit value of is shown. This figure was created based on the experimental results of the inventors using the CCB connection method. From the above, it is clear that the durability has reached the limit in the connection of the rigid structure by the simple CCB method. The following is a summary of the deficiencies of the conventional generally well-known LSI chip connection technology. (1) The wire bonding method and the TAB method cannot be connected and mounted compactly in the horizontal direction. (2) The CCB cannot be mounted on a flexible structure. For such shortcomings of existing LSI chip connection technology,
In particular, for the purpose of solving the above problem (2), the one described in, for example, JP-A-61-110441 has been proposed by Ehrfeld.

[Problems to be solved by the invention]

However, the method proposed above has the following problems. (1) The connecting portion between the LSI chip and the wiring board does not have a deformation (freedom) or an elastic force (springiness) in the vertical (Z) direction. This means that after connecting the LSI chip to the wiring board,
Inconvenience occurs at the contact portion between the back surface (non-electrical connection surface) of the SI chip and the cooling body. That is, the LS connected to the wiring board
The I-chips are usually connected individually with some unevenness or slant (not perfectly horizontal).
Therefore, a gap (or poor contact) may occur at the contact interface between the chip and the cooling body. In order to compensate for this contact failure, the back surface of the chip is normally pressed from the side of the cooling body with a bar (heat-dissipating stud) provided with a spring mechanism (see FIGS. 19 and 24, and references 1 and 2). However, in this method, the cooling effect is reduced and the structure of the cooling body is complicated. On the other hand, the connection method in which the LSI chip has an elastic force (spring property) in the vertical (Z) direction has good contact properties and can simplify the conventional cooling body. However, the conventional connection method of only soldering by the CCB method or the above-mentioned connection method of Ehlfeld does not have enough or sufficient elastic force. (2) In the connection method of Ehlfeld, two connections are required for one terminal of the chip. That is, according to the above-mentioned Japanese Patent Application Laid-Open No. 61-110411, when a chip is connected to a substrate, two upper and lower connections are required for one terminal of the chip. This increases the number of connection points, which is not preferable in terms of chip connection work, reliability of electrical connection, and electrical resistance. This point is also one of the technical problems to be solved by the present invention. That is, in high-density mounting in which a large number of chips are mounted on one substrate, it is desirable that one terminal is connected to the substrate electrode at one place. No.
FIG. 18 shows a configuration of a coupling element in a case where connection is made at two points of the above-mentioned Eilelt (FIG. 18 (a) is a perspective view, and FIG. 18 (b) is a plan view). FIG. 19 (c) is a cross-sectional view showing a state of connection to the electrodes. In other words, the connecting element has two parallel pins 60a and 60b connected to each other by the thin leaf spring 60. In FIG. 18 (c), one pin of the coupling element
60b is electrically connected to the conductor portion 65 of the ceramic substrate 62, and the other pin 60a is electrically connected to the electrode 64 of the chip 61 via the solder 63. With such a configuration, one terminal 64 of the chip is connected to two pins 60a and 60b of the coupling element.
It is connected to the conductor path 65 of the substrate via the location, and the number of connection points becomes two. For the above reasons, it is desirable to complete the connection of the LSI chip by soldering once (many terminals at the same time) as in the conventional CCB soldering, even though it is a flexible structure connection method. Further, in the Eelfeld connection method, high energy is required (in JP-A-61-110441, synchrotron radiation is used) to produce a leaf spring, and the entire process is complicated and cannot be easily performed. There was a problem. On the other hand, an attempt to connect the LSI chip to a more or less flexible structure is disclosed in Japanese Patent Laid-Open No.
The method described in Japanese Patent Publication No. 1255 is proposed by Honda. In this method, as shown in FIG. 17, wiring films 71A and 71B are formed on the LSI chip 70 (electric circuit element) itself, and metal bumps (solder) 72A and 72B are provided at the tips thereof. How to connect to is described. Further, in this proposal, it is described that the film 73 (PiQ: organic film) called a spacer is removed before or after connecting the chip, and the wiring film and the metal bump absorb heat fluctuation distortion (from the text). . However, in this proposal, not only the following (1) to (4) are not clear, but also there is a drawback that there is no extensibility in a specific horizontal direction as described later. (1) Shapes and dimensions of the wiring films 71A and 71B (2) Wiring film, spacer formation, etching conditions (etching solution name, time, etc.) (3) Specific process conditions including the above (1) and (2) (4) Quantitative evaluation results of the invention For this reason, (1) how much thermal expansion and contraction due to thermal strain (from the main part), how much the wiring films 71A and 71B should be Dimensions (width, thickness,
Length, overall shape, etc.).
(2) Preparation of chemicals for implementing this proposal, film formation,
It is difficult to plan work procedures such as etching. Further, in this method, if the wiring films 71A and 71B in FIG. 17 are rectangular in shape, there is a defect in the connection structure that there is almost no elongation in the horizontal inward direction in FIG. That is, the solder bumps 72A and 72B shown in FIG.
In the B connection / cooling process, the wiring films 71A and 71B are severely pulled (tensioned) toward the inside in the drawing, and there is a structural defect that leads to disconnection or disconnection. Another method different from the above is proposed by Mr. Amano (Japanese Patent Application Laid-Open No. Sho 62-136830). The method is shown in FIG. However, even in this method, the solder connection portion must be subjected to a strong tensile stress in a specific horizontal direction. That is, the conductor layer 80 in FIG. 16 greatly extends in the horizontal outward direction when the substrate 81 is heated by chip heat generation or the like. However, the growth of the LSI chip 83 is small. This results in the solder connection 82 being pulled out horizontally. Therefore,
As in the Honda method described above, there is a structural drawback that tension is generated in a specific horizontal direction (although the direction is opposite to the Honda method). As described above, the method of Honda and Amano has a drawback in connection structure in which tension relaxation is not considered in a specific horizontal direction. In view of the above, an object of the present invention is to realize a connection structure having a freely deformable or springy property at least in a horizontal direction by using a simplified process.

[Means for Solving the Problems]

In order to achieve the above object, the present invention
Semiconductor chip having a first electrode, and the semiconductor chip
Plural second electrodes arranged to face the surface of
And electrically connected the first electrode and the second electrode
A plurality of leads, and the plurality of leads are collectively
Each of the plurality of leads formed by etching
Is almost horizontal with respect to the surface of the semiconductor chip.
Has at least a bent or curved shape in the direction
It is configured as follows. In this case, the plurality of leads are arranged vertically and horizontally,
Fits in an area approximately the same size as the semiconductor chip
Preferably, the plurality of leads are arranged so as to form a whole.
No. Also, a plurality of first electrodes, the plurality of first electrodes
A plurality of second electrodes arranged to face the surface having
A pole, the plurality of first electrodes, and the plurality of second electrodes;
Are arranged vertically and horizontally so that they are electrically connected to each other.
A plurality of leads, and the plurality of leads are collectively
Each of the plurality of leads formed by etching
Is substantially horizontal with respect to the surface having the plurality of first electrodes.
At least a bent shape or curve in the horizontal direction
It is configured to have a shape. More specific means for this will be described below.
You. Figures 12 to 14 show the shapes of the micro leads proposed above.
It shows an example. Here is the thickness (height) of the lead
Dimensions should be less than horizontal (horizontal) vertically
To have a moderate (no excess or shortage) spring property and
Micro leads are easily formed by etching (after
). Now, assuming Cu as the microlead material, Fig. 12
Spiral shape (line width 50μm, space width)
50μm, spiral diameter 300μmφ, thickness 20μm) microphone
Effect of using low-lead (lifetime of solder joint)
By the finite element method and the equation for estimating the solder life
Try to estimate. Setting conditions (1) Thermal expansion coefficient (α × 10 ^-7 / ℃) and dimensions
Method LSI chip: α = 30 (0 to 80 ° C) Arranged board: α = 170 (0 to 80 ° C) (2) Operating temperature range and cooling / heating cycle time 0 ° C to 80 ° C (ΔT), 1 cycle / day The results calculated under the above conditions are shown in FIG.
(However, the Young's modulus of the solder is 317kg / mm ^Two , Cu Young's modulus
Is 6000 ~ 12000Kg / mm ^Two Was assumed. The spring constant of the microlead shown in Fig. 11 is vertical (z)
29-57 g / mm in the horizontal direction and 100-380 g / mm in the horizontal (x, y) direction.
You. Also, the displacement amount difference Δy between the chip and the wiring board due to cold heat
= 8 µm, maximum equivalent strain of solder joint Δεeq = 0.3 to 0.5%
From this, it can be estimated that the life of the solder connection is 26 to 49 years
Was. As described above, the service life is sufficient and
Compared to the case where the life is not sustainable
You can predict that. The above service life is indicated by the hatched line (1) shown in FIG.
This is a cooling / heating cycle condition.
The service life is extended 2-3 times. The electrical characteristics were analyzed separately from the above.
As a result, the self inductance is 0.42nH (nanohenry) or less
Below, the resistance is about 12mΩ or less.
There is no problem. As described above, a material with excellent conductivity such as Cu
In a floating state (however, one end is fixed
Spiral) (spiral or swirl)
Connect LSI chip and wiring board via micro leads
By doing so, the basics of flexible connection intended by the present invention
You can get into the structure. Hereinafter, the micro lead structure (size, shape, floating
An overview of how to create a (state) is provided. First, the micro lead group (many) is an LSI chip
Size, for example 10mm ^□ 10mm chip ^□ Provide in
That is. The material used for the micro lead is usually
Any metal can be used as long as it has good conductivity.
Number, springiness (elastic modulus), withstand repeated deformation and
Considering workability such as etching, preferably Al, Cu, A
Metals such as u, Ni, and Cr. Next, one end of the micro lead is directly bonded to the wiring board
With the other end floating in the space
A method for performing the above will be described. This method was originally developed by the inventors.
Various experiments performed for the sake of clarification
It is. 9 and 10 are diagrams illustrating the principle of the above method. The method uses the through-hole conductor 4 of the wiring board 6 shown in FIG.
Through the contact hole where the micro lead is
Through the metal 16 that is in close contact with the through-hole conductor.
The metal layer 18 that forms the chloride lead itself and the
Consists of the material layer of
At the time of or after forming the micro leads,
It is created by removing the material layer 14 that supports.
(C in FIGS. 9 and 10) That is, the microphone having the structure floating in the space according to the present invention.
Low lead is metal used for micro lead on the wiring board
(For example, Cu)
After that, micro leads are plated and etched on
It can be easily made by forming it with a chin. this
Details of the production method will be described in Examples. In this specification,
As described above, the film material for forming the void portion is made of a lift-off material,
The film is called a lift-off film or a lift-off layer. Further
In the manufacturing method of the wiring board with micro leads of the present invention,
Therefore, the selection of the lift-off material is important. The present invention
The following lift-offs when using Cu for micro leads
Materials can be given. Lift-off material of the present invention
The material is easier to dissolve than the material used for microleads
I just need. (1) Al or Al-Si (2) MgO (3) CuO (4) AlN (5) B _Two O _Three −SiO _Two Base glass (6) Organic substances in organic solvents The above lift-off materials, (1) to (4) are made of Cu metal
Easily soluble in poorly soluble alkaline chemicals, (4)-
(6) is soluble in warm water and organic solvents. As a result, using Cu
After micro-leads are formed by etching,
An alkaline solution that is difficult to dissolve or hot water that does not dissolve Cu
The lift-off film can be removed with a solvent. That is, the microphone
In this process, one end of the lead is connected to the wiring board.
It is in a state of floating in space while being connected to the body. The present invention
This good selective etching process and conditions were found, and
It was possible by using In addition, the above micro lead is connected to the through hole of the wiring board.
Metals used to join the body include:
Can be. (1) Ni or Ni alloy (2) Au or Au alloy (3) Cr or Cr alloy
Depending on the metal type of the through-hole conductor,
Any metal can be used as long as it is easy to adjust to. These connections
The joint metal is extremely useful when the through-hole conductor is W or Mo.
It is effective. In addition, the metal used for microleads is a good conductor
If it is possible to use Cu, for example,
By wrapping it in a sandwich with Cr etc.
Effective. This will be described in an embodiment. Here
If only one of the effects of
Role of solder dam when connecting soldering tips by soldering
Eyes. In other words, Au provided as solder bumps
22 is very easy to wet with solder, so soldering is easy
it can. On the other hand, Cr does not wet with solder in the Cr19 part other than Au,
It serves to prevent solder from attaching to places other than the purpose. In addition, the above-mentioned joining metal was passed through as shown in FIG.
The hole conductor is Cu and Cu is used as the microlead material
If so, it is not necessary to use it. In this case before
Micro solders other than Au bumps instead of Cr19 for solder dam
The role is covered by covering the Cu
Can be achieved. Details on how to do this
An example will be described. By using the specific technical means described above,
The wiring board with micro-leads, which is the first part of the invention, is as follows
Can be obtained by taking the following steps. That is, at least the surface on which the electronic components are mounted
Prepare a wiring board consisting of a multilayer wiring structure with groups formed
Performing a lift-off material coating on the entire surface of the wiring substrate.
Forming and making contact holes at the conductor junction; before
A conductive layer for forming micro leads is provided on the entire surface including the electrode.
And then on the conductive layer for forming micro leads.
A resist film is formed and bent or swirled spiral
Place a micro lead pattern mask on the electrode
So that one end of the specified micro lead is located
Place, expose and develop micro-leads
Forming a resist pattern of the above;
The conductive layer for forming micro leads is
Etching process; then the lift-off film and
It has a step of dissolving and removing the resist pattern.
Making a micro-leaded wiring board by the method
can do. By the above method, the wiring board with micro leads can be easily
You can get a board. Next, the LSI chip using this
The connection method will be described. The wiring board with micro leads prepared by the above method
Of the LSI chip (8 in Fig. 12)
Solder balls already provided on the connection terminals (see Fig. 25)
Using a half mirror, and
LSI chips are connected by the source-down bonding method.
You. The connection temperature at this time is not provided on the LSI chip.
Perform at 200-330 ° C from the melting point. The LSI chip is connected to the micro lead on the wiring board
FIG. 5 shows a state in which the connection is made. The figure shows that
6 is a cross-sectional view of a part, in which 6 is a wiring board, and 4 is a cross-section.
Through hole conductor, 7 is micro lead, 24 is gap, 10
Indicates solder, and 11 indicates an LSI chip. [Operation] In the above-mentioned wiring board with micro leads, it is connected to an LSI chip.
Soldering even if there is a large difference in the coefficient of thermal expansion
The thermal stress generated at the joint can be reduced. That is,
Now, as shown in FIG.
Using the wire substrate 6 and the microchip 7, the LSI chip
The electrodes (not shown) of the pump 11 were joined with the solder 10. This place
In this case, the wiring board 6 has a large thermal expansion coefficient, and the LSI chip 11
small. For this reason, an LSI chip is mounted and electrically connected.
The connected wiring board (hereinafter, abbreviated as module) operates.
The LSI chip generates heat due to
If this happens, the substrate side extends much larger than the LSI chip. So
As a result, a deformation displacement difference occurs between the LSI chip and the substrate. Conventionally, this displacement difference causes the soldered part of the LSI chip
Was destroyed. However, with micro-leads according to the invention
On the printed circuit board, the micro lead itself moves X and X by the displacement.
And deformation in any direction, Y or horizontal,
Can be eased. Also, this micro lead
Because it can be springy or deformed in the direct (Z) direction, LSI
Complete the chip in the cooling body 12 located on the back (upper side) of the chip.
Can be fully adhered. As a result, LSI chip cooling
Effect can be sufficiently ensured, and the complex structure proposed in the past
Heat studs can be omitted, and the cooling body can be simplified.
You. Further, in the present invention, the microphone is directly connected to the conductor of the wiring board.
Fig. 2 shows a structure in which one end of a lead is generated.
(B) 9). Therefore, one terminal per chip terminal
The connection of the LSI chip is completed by joining the solder 10. Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 15 and FIGS.
This will be described using a table. Example 1 Formation of Micro Lead on Wiring Board: Part 1 FIG.
FIG. 4 is a cross-sectional view showing a structure of a substrate main body 6 serving as a point. this
In the example, an alumina-based ceramic is used as the base layer 2d.
Polyimide heat-resistant resin on the interlayer insulation layers 2a, 2b, 2c
The figure shows a substrate body consisting of a multi-layered structure.
Signal input / output and power supply
External terminal pins 5 for electricity, ground, etc. are implanted and
Is the wiring pattern 3c and the inside is a through-hole conductor
4 is a pin 5 and a surface circuit pattern 3c and upper layers 2a, 2b, 2c
Of each circuit pattern 3a, 3b, through-hole conductor 4
It is connected to the. That is, these interlayer insulating layers 2b, 2c
Circuit patterns 3a, 3b are also on the surface in the same plane direction, and
Inside, vertical through-holes interconnecting upper and lower circuits
A conductor 4 is provided. The surface 1 of the uppermost insulating layer 2a
The electrode 41 to which the icrory is connected is exposed, and this electrode 41
Lower circuit pattern 3 through internal through-hole conductor 4
a, 3b, 3c, electrically connected to through-hole conductor 4 respectively
Have been. The circuit pattern 3, the through-hole conductor 4,
Each of the externally exposed electrodes 41 was formed of copper (Cu). Next, a micro-lead is placed on the electrode 41 of the wiring board body 6.
3 (a) to 3 (i) are processes for forming the gate 7.
This will be described with reference to the drawings. The figure shows the vicinity of the upper surface 1 of the substrate 6.
An enlarged sectional view of a portion provided with the through-hole conductor 4 of FIG.
Is shown. Here, FIG. 3 (a) shows the wiring board 6
Immediately after making, Cu table at the top tip of through-hole conductor 4
The microphone is placed on this substrate 41 before the surface-exposed surface electrode 41 is oxidized.
Ni film 13 is formed to a thickness of about 0.3 μm as a low-lead bonding material
FIG. This Ni film 13 is exposed to the exposed hole of the through-hole conductor 4 of the wiring board.
Use a mask with holes provided at positions
It was formed by a tarling method. This through-hole conductor diameter
Is about 100μm and the mask diameter is slightly larger than 110μm
And Next, as shown in FIG.
Therefore, the Al film 14 is arranged as a lift-off material to a thickness of about 5 μm.
It was formed over the entire surface of the wire substrate. Next, an alkali-resistant resist (not shown) is lifted off.
Coating and drying on the material 14
The upper portion of the resist was removed. Then, 8% (heavy
Amount of NaOH aqueous solution adjusted to 2%
The Al film of the lift-off material 14 on the film 13 is removed, and the contact hole is removed.
, And after washing and drying, as shown in Fig. 3 (c).
A wiring board in a state as described above was obtained. Next, as shown in FIG.
The thickness of the film 16 is 1000 mm and the thickness of the Cu film 17 is 2 μm over the entire surface.
It was formed by a spun ring method. Furthermore, the thickness of Cu is reduced to 20 μm on the Cu film by electroplating.
After forming the Cu film layer 18 having a thickness of
It was formed to a thickness of Å by a sputtering method. State at this time
The state is shown in FIG. That is, here, Cr-Cu-Cr is in a sandwich state.
These are applied to the upper surface of the through-hole conductor described above.
Formed over the entire surface of the wiring board by bonding with the Ni film 13
It is in the state that was done. This thick film of Cr-Cu-Cr will be described later.
The micro leads themselves are formed by flash etching.
For the conductor layer. In addition, micro Lee
It has a three-layer structure capable of preventing curling of the metal. In addition, sputtering of Ni, Al, Cr, Cu formed above
The film formation conditions by the method are as follows.
Plating is performed by electroplating using an aqueous copper pyrophosphate solution.
became. These facilities and conditions are now very common
Industrial technology that is easily reproducible
You. The residual Cr-Cu-Cr film on the wiring board prepared as described above
Annealing at 200 ° C for 0.5h to remove residual stress
Was. Next, the above Cr-Cu-Cr film is micro-etched by etching.
When the leads are formed, the chip connecting portion (FIG. 2 and FIG.
In the process for applying the Au layer to the position corresponding to the position 8) in the figure
Move on. This Au layer is the solder for connecting the LSI chip 11.
And the contact part
This is to prevent surface oxidation in air.
You. In the Cr-Cu-Cr film, Cr is compared to Au.
Hard to get wet with solder. For this reason, during the connection work, the solder
To prevent solder from escaping into excess parts
(Solder dam) is effective. Hereinafter, Cr-Cu-
For providing an Au film only on the LSI chip connection portion 8 on the Cr film
The steps will be described. First, a positive die for Au plating is formed on the Cr film 19 shown in FIG.
Apply and dry Gyst 20. Next, the conductor bonding portion of the micro lead pattern 7 in FIG.
Exposed electrode of through-hole conductor 4 on center of circle 9 and wiring board
Align the center of the circle with 41 and use the micro lead pattern shown in Fig. 12.
7, the position and size corresponding to the chip connecting portion 8 are drawn.
(Circle with a dotted line: about 110 μmφ)
3 A part 21 of the resist film 20 shown in FIG.
Was. In this process, Fig. 12
Exposed through the mask pattern drawn at the
A hole 21 is provided by an image. Next, the Cr film 19 of the same portion is coated with 16.6% Ce (NO _Three ) _Four 2NH _Four NO _Three Water soluble
After removing by etching for about 2 minutes at room temperature using
As shown in FIG. 3 (g), the Au film 22 was
After the formation, the resist film 20 is removed, and as shown in FIG.
A state wiring board was obtained. Next, in order to form the micro leads 7, FIG.
Apply water-soluble negative resist on the entire surface of Au film 22 and Cr film 19
Dry (not shown). Next, the chip with the micro lead pattern shown in Fig. 12
Align the connection portion 8 with the center of the circle of the Au plating film 22,
The connection between the through-hole conductor joint 9 and the through-hole conductor 4
Align the center of the circle with the exposed electrode 41, and part of it is shown in FIG.
Using the micro lead pattern indicating the
Draw a pattern group by light and development.
The test strip is removed by photo-etching
The pattern of the turn was drawn to form a resist pattern. Next, the Cr-
16.6% Ce (NO _Three ) _Four 2NH _Four NO _Three Aqueous solution, 2min
And then 3.8% FeCl _Three (Ferric chloride) aqueous solution
The 50 sec Cu film is further cleaned with Cr using the cerium nitrate aqueous solution.
Each was removed by etching, and a part of it is shown in Fig. 12.
A microlead group was formed. That is, a Cr-Cu-Cr film
Leave the part corresponding to the entire micro lead,
All portions were removed by etching. 23 is that
Shows the removed cavity. Next used micro-lead etching resistant
Adjust resist pattern (not shown) to about pH10.5
NaOH aqueous solution, followed by 15.3% NaOH-soluble
Eliminates lift-off layer Al14 by etching at 55 ℃ for 85min
After washing with water and drying, the microparticles shown in FIG.
A wiring board with leads was obtained. In this figure, 4 is through
Hall conductor, 7 is micro lead, 24 is micro lead
And remove the Al film of the lift-off layer 14 between the wiring board
Between the micro leads and the wiring board
Are shown. Microphone which is one of the main parts of the present invention obtained above
The specifications of the wiring board with lead are as follows. (1) Dimensions of microleads Lead band width: 50 µm Lead band thickness: Approx. 20 µm Lead pitch: 450 µm (2) Number of microleads Per chip connection: 1000 microleads of this size in the horizontal direction Spring constant is 45
It is 0 g / mm and the spring constant in the vertical direction is 65 g / mm. The dimensions of the microlead according to the embodiment of the present invention are as described above.
Is not limited to the example, and the following dimensional range is preferable. The thickness is 10 to 40 μm and the width is 40 to 70 μm.
300-600 g / mm in the horizontal direction and 40-90 g / mm in the sheet direction
Yes, connection point density is 600-1200 pieces / 10mm ^□ It is. Example 2 FIG. Formation of Micro Lead on Wiring Board: Part 2 This embodiment is a modified application of the present invention. Figure 7 is shown
The through-hole conductor 4 is provided vertically on the alumina substrate 42
You. This uses a copper conductor paste on a perforated alumina substrate
It was made by firing. FIG. 4 (a) shows a method of forming a micro lead.
As shown in the figure, the wiring board 42 formed as described above
As shown in FIG. 4 (b), the entire upper surface 1 of the
Al film 14 as a lift-off material of about 6 μm
It is formed with a thickness. Then, an alkali-resistant resist (not shown) is applied to the Al film 14.
Is applied on the top surface of the
The resist on the Al film 14 on the through hole conductor 4 was removed.
Then, with sodium hydroxide (NaOH) solution adjusted to 8%
The Al film 14 on the through-hole conductor 4 is removed, washed with water and dried.
To form a contact hole 15 in the state shown in FIG.
I do. The diameter of the contact hole 15 is about 110 μm.
It is. Then, the remaining resist on the Al film 14 on the wiring board is removed.
After removing, put in copper pyrophosphate plating solution,
As shown in (d), the copper film 18 is formed by electroplating to a thickness of about 20 μm.
It is formed over the entire surface of the Al film 14 with a thickness. At this time,
The through-hole conductor 4 in the contact hole 15 and the copper film 18
It is directly joined at the joining surface 9. Thus, the wiring board 6 on which the copper film 18 is formed is washed with water.
・ After drying, polish on copper film 18 while copper film 18 is not oxidized.
Apply a di-type resist 20 and solder the micro leads 7
A portion of the resist 20 corresponding to the position of the joint 8 has a diameter of about 110 μm.
It is removed to a circular shape of mφ. Then, on the portion where the resist is removed and the copper film 18 is exposed.
First, as shown in FIG.
After forming a Ni layer 25 to a thickness of about 0.5 μm, Au (gold)
Layer 22 is formed to a thickness of 1 μm. Next, a micro lead 7 shown in FIG. 14 was formed.
To remove the remaining resist film on the Cu film 18 on the wiring board 42.
After removing, apply a new negative resist and dry
And a number of micro lead patterns having the shape shown in FIG.
After exposing the resist group, the other resist is removed.
Here, the joint 9 with one through-hole conductor 4 is
Match the center of the circle of the through hole conductor 4 with another solder joint
The part 8 is aligned with the center of the circle of the gold layer 22. Next, the copper film other than the one protected by the negative resist
The exposed part of 18 is made of a ferric chloride aqueous solution (Fecl _Three ・ Cl ^- 35g /)
Using an etching solution, as shown in FIG.
Chloride 7 is formed by etching. Next, the Al film 14 is dissolved using an aqueous sodium hydroxide solution.
After removing the solution, as shown in FIG.
After the space 24 is formed between the wiring board 7 and the wiring board 42,
Dried. Then, the wiring board 42 is moved about in a mixed airflow of air and oxygen.
Heat at 200 ° C for 10 minutes and use a microphone as shown in Fig. 3 (h).
Oxidize all of the surface 26 except the gold layer 22
You. At this time, the surface of the copper film becomes less shiny and the surface of the copper film is oxidized.
That the micro-lead
A wire substrate was created. The microphone created in this way
The specifications of the wiring board with lead are as follows. (1) Micro lead dimensions Lead band width: 50 μm Lead band thickness: Approx. 20 μm Lead pitch: 300 μm (2) Number of micro leads Per chip connection: 1225 1 By the above process, the micro
The lead end (LSI chip connection part 8) of the wiring board with
Solder balls already provided at the connection terminals of the SI chip
Use a half mirror to align 10 with
LSI chips are connected by the down bonding method.
Was. The connection temperature at this time is not provided on the LSI chip.
The measurement was performed at an instantaneous peak temperature of 300 ° C. from the melting point. As described above, the LSI chip 11 is
FIG. 5 shows a state of connection to the node 7. The figure is
6 is a partial cross-sectional view, in which 6 is a wiring board, and 4 is a board.
Through hole conductor, 7 is micro lead, 24 is gap, 10
Indicates solder, and 11 indicates an LSI chip. Embodiment 4. Connection of LSI chip: Part 2 Connection of LSI chip is performed before removing the lift-off layer
You can also. However, in that case, use lift-off material.
Organic substances soluble in organic solvents or substances soluble in water or hot water
Prefer to use quality. FIG. 15 shows an example of such a case.
A heat-resistant organic resist soluble in water was used. Example 5 Cooling / heating cycle test Wiring connected to the LSI chip connected in the above Examples 3 and 4
Place the substrate in the chamber (chamber) of the thermal shock tester, -50 ℃
Perform a thermal test at a rate of 1 cycle per hour at ~ 150 ° C.
Was. Table 1 shows the results. Table 1 shows the conventional CCB
Soldering only method and one of the main parts of the present invention
Difference from the method using a wiring board with micro leads
Points and effects are shown together. The result is a microlith, one of the main parts of the present invention.
The use of a printed circuit board with
The solder joints are sufficiently resistant to the thermal cycling environment
I found out. Example 6: Spring property test Regarding the LSI chips connected in the above Examples 3 and 4,
The microreed was tested for springiness. as a result,
Example in one vertical direction (Z) per chip 28.8 for three samples
Kg / mm, and 30.1 kg in the sample of Example 4. As a result, it was found that the film had a spring property in the vertical direction.
Was. Embodiment 7 Assembly of Electronic Device: Part 1 Micro-chip Connected with LSI Chip Prepared in Embodiment 3
The central control unit of a large computer uses a wiring board with leads.
(CPU) was mounted and assembled. In this logical operation part
In this case, a large number of modules (here, the LSI chip
One board connected with 25 to 100 chips is called one module.)
Is mounted. In FIG. 6, many of the above modules are mounted on the board 30.
It is sectional drawing of a part of one module. This sixth
In the figure, the LSI chip 1 connected to the wiring board 6 with micro leads
The back of 1 has a micro lead on the wall of cooling body 12
It can be pressed sufficiently by the direct spring property
Was. For this reason, the cooling body 12 dissipates heat by the spring mechanism as in the past.
The studs (see FIGS. 19 and 24) could be omitted. Also,
Therefore, the cooling body 12 has a heat exchange efficiency of water cooling inside.
Fins 32 can be provided. This water cooling and fin
Heat exchange efficiency several times higher than conventional cooling methods
Up. In FIG. 6, 11 is an LSI chip and 7 is a micro chip.
6 is a wiring board, 35 is a pin 5 electrical connector, 31
Is the cooling water channel, 32 is the fin, 36 is the brazing filler metal, 33 is
Cooler cover, 34 is cooling water pipe, 30 is board, 37 is module
Shows the power line of Joule. Here, the brazing filler metal 36 is used
Instead of just contacting the LSI chip, it is acceptable. As described above, the structure of the electronic device to be assembled, especially
Simplifies the cooling body and further enhances the cooling effect
Improved way. Example 8 Assembly of Electronic Device: Part 2 Using Wiring Board with Micro Leads Prepared in Example 2
Apply the LSI chip to the package as shown in FIG.
Was. In FIG. 7, 6 is a wiring board having a large coefficient of thermal expansion α, and 7 is a matrix.
Micro lead, 42 is a wiring board with micro leads, 43 is
Bumps, 10 for CCB solder, 41 for package cap
is there. Next, the above compactly packaged module
As shown in the eighth, awake in the enclosure with a large water cooler
Was. In FIG. 8, 11 is an LSI chip and 41 is an LSI chip package.
Cage cap, 12 is cooling body, 32 is fin, 33 is cooler cap
Bar, 31 is a water channel, 34 is a cooling water pipe. As described above, once packaged LSI chip module
The module is controlled by the micro leads on the bottom of the module.
The back of the joule itself (the top of 41) is
I was able to push it enough. As a result,
It is not necessary to provide a heat radiation stat with
Construction and creation were simplified. Also, the elimination of land that was simplified
The fins 32 are provided on the
The rejection effect could be improved several times more than before. As described above, according to the embodiment of the present invention, the linear thermal expansion coefficient
Connection between substrates and electronic components with different lengths and longer life in use
(Improvement of durability) and electronic device
Simplifies assembly and improves the cooling effect,
It is useful in. Table 2 shows the informative numerical comparison
Indicated.

【The invention's effect】

ADVANTAGE OF THE INVENTION According to this invention, the connection structure which has a free deformation property or a spring property at least in a horizontal direction can be implement | achieved using a simplified process.

[Brief description of the drawings]

FIG. 1 is a partial sectional view of a starting wiring board, FIG. 2 is a sectional view showing the principle of the shape, bonding, chip connection structure, mounting of a cooling body, etc. of the micro lead of the present invention, and FIGS. FIG. 5 is a partial sectional view of the principle of the LSI chip connection structure, FIGS. 6, 7 and 8 are partial sectional views of the assembly structure of the electronic device according to the present invention, FIGS. 9 and FIG. 10 is a principle diagram of a method for producing a wiring board with micro leads, which is one of the main parts of the present invention, FIG. 11 is a diagram of stress calculation results of micro leads, FIG. 12 to FIG. Figure 18 shows the chip connection method diagram of the conventional method.
19 is an explanatory diagram of a conventional method, FIG. 20 is a diagram of a result of a CCB connection part life limit test, FIG. 21 is a diagram showing a TAB method, FIG. 22 is a diagram of a wire bonding method, FIG. 23 is a diagram of the number of LSI chip terminals, FIG. 24 is a conventional electronic device mounting diagram, and FIG. 25 is a CCB connection principle diagram. DESCRIPTION OF SYMBOLS 1 ... Board surface 2 ... Insulating layer 3 ... Horizontal wiring 4 ... Through hole conductor 5 ... Pin 6 ... Wiring board 7 ... Micro lead 8 ... Solder connection 9 … Micro lead joint 10… Solder, 11… LSI chip 12 …… Cooler, 13… Joint metal 14… Al lift-off layer, 15… Contact hole 16-19 …… Micro lead material 20… Photoresist, 21 Resist hole 22 Au bump, 23 Space 24 Gap, 26 Cu oxide film 30 Board, 31 Water channel 32 Fin, 33 Water cooling Cover 34… Cooling water pipe, 35… Electrical connector 36… Adhesive brazing filler metal, 37… Module power supply 41… Package cap, 42… Alumina substrate 43… Solder bump

Continuing on the front page (72) Inventor Naoya Isada 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. Production Engineering Laboratory (72) Inventor Masaru Sakaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. In Production Technology Laboratory (72) Inventor Minoru Murata 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Hitachi, Ltd. Kanagawa Plant (56) References JP-A-54-74370 (JP, A) JP-A-56-125864 (JP) JP-A-58-7843 (JP, A) JP-A-61-110441 (JP, A) JP-A-57-28337 (JP, A) JP-A-59-177957 (JP, A) 63-177434 (JP, A) JP-A-63-174328 (JP, A) JP-A-63-310127 (JP, A)

Claims (3)

(57) [Claims] A semiconductor chip having a plurality of first electrodes on a surface thereof; a plurality of second electrodes disposed so as to face the surface of the semiconductor chip; And a plurality of leads electrically connected to the electrodes of the semiconductor chip. The plurality of leads are collectively formed by etching, and each of the plurality of leads is substantially horizontal with respect to the surface of the semiconductor chip. An electronic device characterized by having at least a bent shape or a curved shape in a horizontal direction. 2. The method according to claim 1, wherein the plurality of leads are arranged in a vertical and horizontal direction.
2. The electronic device according to claim 1, wherein the plurality of leads are arranged so as to fit in a region having a size substantially equal to the size of the semiconductor chip. 3. A plurality of first electrodes, a plurality of second electrodes arranged to face a surface having the plurality of first electrodes, and a plurality of first electrodes. A plurality of leads arranged in the vertical and horizontal directions so as to electrically connect the plurality of second electrodes, respectively, the plurality of leads being formed by etching all at once Wherein each of the electronic devices has at least a bent shape or a curved shape in a horizontal direction that is substantially horizontal to a surface having the plurality of first electrodes.