JP2735025B2 - Frequency division multiplex signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency division multiplexing signal generator, and more particularly to an orthogonal frequency division multiplexing (OFD) for a coded digital video signal or the like in a limited frequency band.
M: Orthogonal Frequency Division Multiplex (M) relates to a frequency division multiplex signal generation device that generates a signal by converting the signal.

[0002]

2. Description of the Related Art One method of transmitting coded digital video signals in a limited frequency band is as follows.
6 Quadrature Amplitude Modul (QAM)
An OFDM system that transmits digital information modulated by multi-level modulation such as ation) using a large number of carriers is conventionally known. The OFDM system is a system in which a large number of carriers are arranged orthogonally and independent digital information is transmitted on each carrier. Note that "carriers are orthogonal" means
This means that the spectrum of an adjacent carrier becomes zero at the frequency position of the carrier.

According to the OFDM method, since a guard band period (guard interval) is set and information of the period is transmitted in an overlapping manner, transmission distortion caused by multipath of radio waves can be reduced. That is, the reception of the OFDM signal is to detect the amplitude and phase modulation components of the signal transmitted within the symbol period and to decode the value of the information based on these levels. By decrypting it,
Since the frequency components of the multipath signal in the same symbol section and the signal to be received are the same, decoded digital data with little transmission distortion can be transmitted in a relatively narrow frequency band.

Conventionally, the above-mentioned OFDM signal is generated using a single inverse fast Fourier transform circuit (IFFT circuit). This IFFT circuit performs a multiplexed butterfly operation by decomposing a discrete Fourier transform (DFT) of size N into a DFT of size N / 2 when the length N of the data sequence is a power of 2 2 ^L. When a degree is k, a signal of a value (level) corresponding to a digital value to be transmitted is given to terminals of a real part and an imaginary part of k, and a signal for transmitting a digital value is obtained. It is known that when an inverse DFT with N complex numbers is performed during a time interval T, an OFDM signal can be generated, and each point of the inverse DFT corresponds to a carrier ("Data compression and digital modulation", Nikkei Electronics Book, 233 pages).

[0005] Since a large number of information carriers generated using this IFFT circuit are modulated and transmitted according to information to be transmitted, an OFDM signal which is a frequency division multiplexed signal of these information carriers is converted into a random signal. Take the form.

[0006]

However, in the above-mentioned conventional apparatus, no measures are taken against the OFDM signal formed by combining a large number of information carriers, especially the peak power that occurs instantaneously. May be generated. For example, OFDM using 256 information carriers
Since the power of the signal is a combined average power of 256 times the power of one information carrier, if the maximum amplitude voltage values of all the information carriers are generated in agreement, the power becomes 65536 times, which is the square of 256 times. . Therefore, assuming that the power of one information carrier is 1 mW, the average power obtained by combining these 256 information carriers is about 256 mW, but becomes 65 W when the maximum amplitude positions of all the information carriers match.

For this reason, in the conventional frequency division multiplex signal generator, the probability that the maximum amplitude values of all the information carriers coincide is very small, and it hardly occurs in practice, but the average power value is a low value with a margin. And a transmission power device capable of generating a large output signal with a margin of about 10 to 20 times the average power (a device capable of generating 2.5 W to 5 W when the power of one information carrier is 1 mW). , So that even rarely generated high power signals can be transmitted without being saturated. For this reason, the conventional frequency division multiplex signal generator has a problem that the entire device is expensive and large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and realizes reduction in size and weight of a transmission device including a power supply device of a transmission device by reducing peak power of a generated frequency division multiplexed signal. It is an object of the present invention to provide a frequency division multiplexed signal generating apparatus.

It is another object of the present invention to provide a frequency division multiplex signal generator capable of improving a carrier power to noise power ratio (C / N) at a receiving point.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a data distributor for dividing a digital information signal into a plurality of signals, and a digital information signal which is modulated based on each of the digital information signals divided by the data distributor. A plurality of arithmetic circuits for generating a plurality of frequency division multiplexed signals, a plurality of peak detection circuits for detecting peak powers of the plurality of frequency division multiplexed signals extracted from the plurality of arithmetic circuits, and outputs of the plurality of peak detection circuits A polarity for controlling the polarity of one or more frequency division multiplexed signals other than the frequency division multiplexed signal of the detected peak power exceeding the threshold among the detected peak powers in a direction to cancel the detected peak power exceeding the threshold. It has a configuration having a control means and an addition circuit for adding and outputting a plurality of frequency division multiplexed signals passed through the polarity control means.

Further, according to the present invention, the digital information signal divided by the data distributor is sequentially multiplied by the output of the previous stage and added to the output of the previous stage at each stage for each of a plurality of groups, and modulated by the final stage. A plurality of arithmetic circuits for generating a plurality of frequency-division multiplexed signals, a plurality of polarity switching circuits for switching the polarity of an addition input at the final stage of each of the plurality of arithmetic circuits, and a part of each of the plurality of arithmetic circuits. A polarity judging circuit that detects peak powers and peak positions of a plurality of frequency division multiplexed signals based on the extracted signal and controls a plurality of polarity switching circuits in a direction to cancel a detected peak power exceeding a threshold; And an adder circuit for adding and outputting the frequency division multiplexed signal of the arithmetic circuit.

[0012]

According to the present invention, a modulated frequency division multiplexed signal output from n (n is an integer of 2 or more) arithmetic circuits is added to an adder circuit to generate a frequency division multiplexed signal having a desired number of carrier waves. Therefore, the peak power of the signal can be reduced to 1 / n as compared with a case where a single arithmetic circuit generates a frequency division multiplexed signal having a desired number of carriers. Further, the instantaneous power of the output frequency division multiplexed signal is further reduced by controlling or inverting the polarity of a signal generated from another arithmetic circuit at a peak power position generated by one of the arithmetic circuits. Value.

[0013]

Next, an embodiment of the present invention will be described. First, before describing the frequency division multiplex signal generator of the present invention, an OFDM signal transmitting apparatus and an OFDM signal receiving apparatus to which the frequency division multiplex signal generating apparatus of the present invention is applied will be described.

FIG. 4 is a block diagram showing an example of an OFDM signal transmitting apparatus and a receiving apparatus to which the frequency division multiplex signal generating apparatus according to the present invention is applied. In FIG. 1, digital data to be transmitted is input to an input terminal 1. The digital data is, for example, a digital video signal or an audio signal compressed by an encoding method such as the MPEG method, which is a color moving image encoding and displaying method. The input digital data is supplied to an input circuit 2 and an error correction code is added as necessary based on a clock from a clock frequency divider 3. The clock frequency divider 3 divides the 10.7 MHz intermediate frequency from the intermediate frequency oscillator 8 and
A clock synchronized with this intermediate frequency is generated.

The digital data to which the error correction code has been added is supplied from an input circuit 2 to an inverse fast Fourier transform (IFFT).
It is supplied to the device 4. The IFFT device 4 is a device part which is a main part of the device of the present invention, and uses a plurality of IFFT circuits in the present invention as described later. The IFFT device 4 includes an IFFT circuit in which the data sequence N is 256,
= M = 512 Two examples of the IFFT circuit will be described. When the IFFT circuit constituting the IFFT device 4 is the former IFFT circuit, the number of input terminals of the real part (R) is 256 and the number of input terminals of the imaginary part (I) is 256, and each of the 4-bit digital data Are input to a total of 256 input terminals for both the real part and the imaginary part, so that the input information of the 0th (k = 0) input terminal is transmitted at the center frequency of the carrier to be transmitted, and k = N / 2 , 12
The input information of the seventh (k = N / 2) input terminal is transmitted at both end frequencies equivalent to the Nyquist frequency.

The IFFT constituting the IFFT device 4
When the circuit is the latter IFFT circuit, the number of input terminals of the real part (R) is 512 and the number of input terminals of the imaginary part (I) is 512, and the 4-bit digital data is a real part and an imaginary part, respectively. Both are input to a total of 128 input terminals from the 0th to the 127th and a total of 127 input terminals from the 384th to the 511th, so that the input information of the 0th (k = 0) input terminal becomes The signal is transmitted at the center frequency of the carrier to be transmitted and the 127th (k = M /
The input information of 4) and 384th (k = 3M / 4) input terminals are transmitted at both ends frequencies equivalent to the Nyquist frequency.

Here, a total of 1 from the 1st to the 127th
The input information of the 27 input terminals is transmitted on the carrier for information transmission above the center carrier frequency (high frequency side), and the input information of a total of 127 input terminals from 384th to 511th is below the center carrier frequency. It is transmitted on the carrier wave for information transmission on the side (low frequency side). The input information of the 127th and 384th input terminals is transmitted at both ends frequencies equivalent to the Nyquist frequency. Note that 0 is input to the remaining input terminals.

Here, in any of the above cases, IFFT
Information is transmitted using 248 carriers out of 257 out of 258 sets of outputs from the apparatus 4 except for a set of outputs transmitted at the center carrier frequency of k = 0, and the remaining 9 sets are output.
The waves are used for calibration and for transmission of other auxiliary signals. Therefore, during one symbol period, 24
8-byte digital data, that is, 248 pairs of parallel data of 4 bits each is input from the input circuit 2 to the real part input terminal and the imaginary part input terminal of the IFFT device 4 during one symbol period.

A total of 257 sets of output data obtained by performing an IFFT operation from the IFFT device 4 on the basis of the clock from the clock frequency divider 3 are passed through a guard interval circuit 5 for reducing multipath distortion, and are then subjected to D / A conversion. The signal is supplied to a converter / low-pass filter (LPF) 6 where the clock from the clock divider 3 is converted into an analog signal by using the clock as a sampling clock. The partial components are passed and supplied to the quadrature modulator 7, respectively.

The quadrature modulator 7 uses an intermediate frequency of 10.7 MHz from the intermediate frequency oscillator 8 as a first carrier wave, and shifts the phase of the intermediate frequency to 90 ° by the 90 ° shifter 9.
Using the shifted 10.7 MHz intermediate frequency as a second carrier, the quadrature amplitude of the real part (real part data) and the imaginary part (imaginary part data) of the digital data input from the D / A converter / LPF 6 respectively. Modulation (QAM) is performed to generate an OFDM signal composed of 257 information carriers.

That is, in this embodiment, the quadrature modulator 7 converts the digital / analog converted signal of the 4-bit real part data and the 4-bit imaginary part data indicating 16 levels, respectively.
, An OFDM signal having a center frequency F0 of 10.7 MHz and a frequency spectrum as shown in FIG. 5, for example, is extracted from the orthogonal modulator 7.

The frequency spectrum shown in FIG.
The frequency spectrum of the OFDM signal when the data sequence of the FT device 4 is N (= 256),
There are a total of 257 carriers in kHz, of which 248 carriers are 256 bytes of information data of 1 byte.
The remaining nine carriers, which are M-modulated and include the center frequency F0, are used for transmitting auxiliary signals.

The carrier higher than the center frequency F0 is modulated by data or the like input to the first to 128th real part input terminals and the imaginary part input terminals of the IFFT circuit. The carrier wave lower than the frequency F0 is modulated by data input to the 128th to 255th real part input terminals and the imaginary part input terminals of the IFFT circuit.

FIG. 5A shows "128" and "-1".
A carrier having a Nyquist frequency is generated at the position indicated by reference numeral 28, and is a carrier for transmitting a pilot signal generated based on the fixed voltage data input to the 128th input terminal as described above. That is, the fixed voltage data input to the same 128th input terminal is
It is transmitted by two carriers.

The effective symbol frequency f _S when the IFFT cycle is N (= 256) and the effective symbol period t _S are as follows.

F _s = 99,000 / 256 = 387 (Hz) t _s = 1 / f _s = 2586 (μsec) A guard interval g _i, which is a multipath distortion removal section provided by the guard interval circuit 5, 6
The symbol period t _a and the symbol frequency f _a when added as 0 μsec are as follows.

T _a = t _S + g _i = 2586 + 60 = 264
_{6 (μsec) f a = 1} / t a = 378 (Hz) The data series of the IFFT unit 4 is 2N (= 512)
, The OFDM signal also has a total of 257 carriers in a frequency band of 99 kHz, of which 248 carriers are 256QAM-modulated with 1-byte information data, and the remaining 9 waves including the center frequency F0 Are used for the transmission of the auxiliary signal.

However, the frequency spectrum of the OFDM signal in this case is, as shown in FIG. 5B, the carrier wave higher than the center frequency F0 is the first to 128th real part input terminals of the IFFT circuit. And a carrier wave lower than the center frequency F0 is modulated by the data input to the imaginary part input terminal.
It is modulated with data and the like input to the 511st to 511st real part input terminals and the imaginary part input terminals.

In this case, as shown in FIG.
“128” is a carrier for transmitting a pilot signal generated by the fixed voltage input to the 128th real part input terminal and the imaginary part input terminal of the IFFT circuit, and “−”.
"128" is a carrier for transmitting a pilot signal generated by a fixed voltage input to the 384th real part input terminal and the imaginary part input terminal of the IFFT circuit, and these are carriers having a frequency half the Nyquist frequency. .

The above-mentioned OFDM signal composed of a plurality of carriers arranged adjacent to each other at 387 Hz, which is the symbol frequency of the data before guard interval processing, extracted from the quadrature modulator 7 is converted to the frequency converter 10 shown in FIG. , And is frequency-converted into a transmission frequency band. For example, the central carrier frequency F0 is set to 100 MHz, then linearly amplified by the transmission unit 11, and transmitted from the transmission antenna.

As a result, the specifications of the signal transmitted by the transmitting apparatus of FIG. 4 are as follows: the signal center frequency is 100 MHz, and the transmission bandwidth is 100 kHz (actually, 99 kHz as shown in FIG. 8).
z), the modulation method is 256 QAM, OFDM, the number of used carriers is 257 (of which, the number of carriers for information transmission is 248), and the guard interval is 60 μsec. Also, a pair of 4
Since 248 sets of bit data are transmitted by 248 carrier waves, the transmission rate is 248 kbytes per symbol period, and the transmission rate (transfer rate) per second is about 750 kbps (≒ 8 bits × 378 Hz × 248). $ 1
000).

Next, a frequency division multiplex signal receiving apparatus will be described. The above-mentioned OFDM signal is received by a receiving unit 13 via a receiving antenna via the spatial transmission path 12 shown in FIG. 4 and then high-frequency amplified, further frequency-converted to an intermediate frequency by a frequency converter 14, and After being amplified, it is supplied to a quadrature demodulator 16 and a carrier extraction circuit 17.

The carrier extracting circuit 17 is a circuit for extracting the center carrier (carrier) of the input OFDM signal as accurately as possible with a small phase error. In this embodiment, each carrier for transmitting information is arranged adjacent to every 387 Hz that is a symbol frequency to form an OFDM signal. Therefore, the carrier for information transmission adjacent to the center carrier is also 387 Hz away from the center frequency. Therefore, in order to extract the center carrier, a circuit having a high selectivity is required so as not to be affected by the adjacent carrier for information transmission which is only 387 Hz apart.

Therefore, the carrier extraction circuit 17 extracts the center carrier F0 using a PLL circuit. However, the VCO constituting the PLL circuit in this case has a variable range of about 200 Hz, which is about 1/2 of the adjacent carrier frequency.
A voltage controlled crystal oscillation circuit (VCXO) using a crystal oscillator that oscillates at about the same level is used, and an LPF having a sufficiently low cutoff frequency with respect to 387 Hz is used as an LPF constituting a PLL circuit.

The center carrier F0 extracted by the carrier extracting circuit 17 is supplied to an intermediate frequency oscillator 18 where an intermediate frequency of 10.7 MHz synchronized with the center carrier F0 is generated. The output intermediate frequency of the intermediate frequency oscillator 18 is supplied directly to the quadrature demodulator 16 as a first demodulation carrier, while the phase is shifted by 90 ° by a 90 ° shifter 19 and then quadrature demodulated as a second demodulation carrier. Is supplied to the vessel 16.

Thus, an analog signal (frequency division multiplexed signal) equivalent to each of the real part and imaginary part analog signals input from the quadrature demodulator 16 to the quadrature modulator 7 of the transmitting apparatus.
Is demodulated and taken out, and the sample clock decoding circuit 2
0, while the low-pass filter 21
A signal of a necessary frequency band transmitted as signal information is passed, supplied to the A / D converter 22, and converted into a digital signal.

The sampling timing for the input signal of the A / D converter 22 is determined by the sampling clock decoding circuit 2
0, for example, is generated based on a sample clock having a frequency twice as high as the Nyquist frequency, which is generated from a pilot signal and is set to a predetermined integer ratio with respect to the sample clock frequency and transmitted on a specific carrier. That is, the sample clock decoding circuit 20 receives the intermediate frequency and the demodulated analog signal, and generates a sample clock by a PLL circuit which is phase-synchronized with a pilot signal transmitted as a continuous signal in each symbol period including the guard interval period.

Further, the symbol synchronization signal decoding circuit 23
Using this sample clock, the phase state of the pilot signal is checked, the symbol period is detected, and the symbol synchronization signal is decoded. The system clock generation circuit 24 generates a system clock such as an interval signal for removing a guard interval period from the sample clock and the symbol synchronization signal.

The digital signal extracted from the A / D converter 22 is supplied to a guard interval period processing circuit 25, where the digital signal is less affected by multipath distortion based on the system clock from the system clock generation circuit 24. Is obtained and supplied to the FFT / QAM decoding circuit 26.

The FFT (Fast Fourier Transform) circuit section of the FFT / QAM decoding circuit 26 performs a complex Fourier operation on the basis of the system clock from the system clock generating circuit 24, and outputs an output signal of the guard interval period processing circuit 25 for each frequency. The signal levels of the real part and the imaginary part are calculated.

The real part of each frequency obtained by the above,
Each signal level of the imaginary part is compared with the demodulated output of the reference carrier by the QAM decoding circuit section, whereby the level of the quantized digital signal transmitted by the carrier for digital information transmission is obtained. Decrypted. The decoded digital information signal is subjected to output processing such as parallel-serial conversion by the output circuit 27 and is output to the output terminal 28.

Next, each embodiment of the IFFT device 4 as a main part of the present invention will be described. FIG. 1 is a block diagram showing an embodiment of a main part of the present invention. The IFFT device comprises a data distributor 32 for distributing input digital data into four, and four IFFTs.
T circuits 33 to 36, peak detection circuits 37 to 40, a data polarity determination circuit 41, polarity control circuits 42 to 45,
An adder circuit 46 is provided.

The input digital data input through the input terminal 31 is a 256-byte signal to be transmitted in one symbol period.
After being divided into four digital signals (real part data and imaginary part data) for each byte, IFFT circuits 33 to 36
Respectively.

Assuming that each of the IFFT circuits 33 to 36 is an IFFT circuit in which the data series N is 256, the number of input terminals of the real part (R) is 256 and the imaginary part (I)
Has 256 input terminals, and each of the 4-bit digital data has a total of 256 input terminals for both the real part and the imaginary part. Of these, 64 input terminals are provided for both the real and imaginary parts. 4-bit digital data is input.

Here, these 64 input terminals are I
The FFT circuit 33 is connected to an input terminal for outputting the ± 4 m-th (m is an integer of 0 to 31) -th carrier frequency by an IFFT circuit 34.
Is an input terminal for outputting the ± 4m + 1 (m is an integer from 0 to 31) th carrier frequency, and the IFFT circuit 35
The IFFT circuit 36 supplies ± 4m + 3 (m is 0 to 2) (m is an integer from 0 to 31) to an input terminal for outputting the 2nd carrier frequency.
(Integer of ~ 31) th carrier wave frequency.

As described above, the IFFT circuits 33 to 36 divide the carrier frequency constituting the OFDM signal into four in a comb shape and output. When the OFDM signal is generated by adding these output signals as they are, the problem of the peak power, which has been a conventional problem, remains. Since the amplitude and phase of each carrier constituting the OFDM signal is determined by the modulation signal, when the input signal has little correlation, the output signal is also a set of random carrier signals.

As described above, the average power obtained by synthesizing the 256 random carrier signals is 2 times the power of one carrier wave.
56 times. If the instantaneous peak positions of all carriers match, the power value becomes 65536 times, which is the square of 256. In practice, the probability that the peak values of the 256 carriers coincide is very small and cannot be said to occur. It is said that the peak value of the power that can usually occur is 10 to 20 times the average power. That is, when the average transmission power of the OFDM signal is set to 10 W, the power amplifier of the transmitting unit 11
The ability to transmit power of about 0 W to 200 W without distortion is required (the theoretical maximum power at this time is 2560
W).

Therefore, in this embodiment, the average power is increased and the C / N at the receiving point is improved by suppressing such instantaneous power. That is, IFFT
The output signals of the circuits 33 to 36 are supplied to the corresponding polarity control circuits 42 to 45, respectively, and input to the peak detection circuits 37 to 40, respectively. It is detected where the occurrence time position occurs in the IFFT operation. IFFT circuit 33-
36 operate on 64 carriers each,
Naturally, the peak power value for the average power value is 2
This is a value that is 1/4 times that when the calculation is performed for 56 carrier waves.

The detected data indicating the maximum instantaneous power value of the output signals of the IFFT circuits 33 to 36, the polarity thereof, and the occurrence time position, which are extracted from the four peak detection circuits 37 to 40, are supplied to the data polarity determination circuit 41. . The data polarity judging circuit 41 obtains a combination of polarities in which the peak power value is smaller than the input detection data, and based on the result, I is supplied from the polarity control circuits 42 to 45 to the common adding circuit 46.
The polarity of the output signal of the FFT circuits 33 to 36 is controlled.

The data polarity judging circuit 41 usually has an IFF
The polarity control circuits 42 to 45 are controlled so that the output signals of the T circuits 33 to 36 are output in the same phase, but when a large peak power is detected, the I
Polarity control circuits 42 to 42 so that the polarity of the output signal of another IFFT circuit different from the output signal of the FFT circuit cancels it.
45 is controlled. Thereby, the polarity control circuits 42 to 45
From an adder circuit 46 for adding each of the output signals of the OFs, which comprises 256 carrier waves with peak power suppressed to a predetermined value or less.
A DM signal is output.

By the way, when the length N of the data sequence is a power of 2 2 ^L , the fast Fourier transform (FFT) circuit decomposes the discrete Fourier transform (DFT) of size N into a DFT of size N / 2. And performs a butterfly operation in a multiplexed manner. It is known that this butterfly operation can be represented by a signal flow diagram as shown in FIG. 2 when N = 8 (for example, Seiji Imai, "Signal Processing Engineering", Corona Co., p. 80). .
In the figure, x

[0] to x [7] are data series, W _N ⁱ (where i = 0 to 7) are twiddle factors, X

[0] to X [7] are D
Shows the value of FT. Arrows indicate the direction in which the signal propagates, numbers near the circle indicate values to be multiplied, and circles indicate addition points.

The circuit portion at the last stage in FIG. 2 can be represented as shown in FIG. In FIG.
One of one N = the data from the 4 to be input to the adder circuit ₅₁ 0-51 _7, twiddle factor _^(W 0 N) 52 ₀ twiddle factor _^(W 7 N) 52 ₇ and addition after being multiplied circuits ₅₁ 0 ~ 51
₇ and added. Thereby, the addition circuit 51
_0-51 from ₇ outputs the value X [k] which is represented by the following formula.

[0053]

(Equation 1) This relates to the FFT circuit, but if the sample value of the input signal is replaced with the result of the FFT operation of the output signal, the circuit can be operated as an IFFT circuit. IFFT
Is multiplied by a predetermined twiddle factor to a sample value obtained by IFFT of a value of an even term and a sample value obtained by IFFT of a value of an odd term, and added.

In another embodiment of the present invention, the circuit portion of the last stage has the structure shown in FIG. In FIG. 7B, the same components as those in FIG. 7A are assigned the same reference numerals and explanations thereof will be omitted. In FIG. 3 (B), the sample values from the two N = 4 is input to one input terminal of the adding circuit ₅₁ 0 to 51 _7, each polarity determining circuit with the multiplication result from the rotation factor ₅₂ 0-52 ₇ 55. Multiplication from the rotation factor ₅₂ 0-52 ₇ results also polarity switching circuit ₅₆ 0-56 ₇ via the adder circuit ₅₁ 0
Also supplied to 51 ₇ other input terminal of the.

[0055] polarity determination circuit 55 is the same structure as consisting of peak detection circuit 37 to 40 and a data polarity detection circuit 41. shown in FIG. 1, the sample value input to the addition circuit ₅₁ 0 to 51 ₇ When a value larger than a predetermined threshold value is detected, the polarity switching circuit controls the polarity of the multiplication result of the twiddle factor input to the other input terminal of the addition circuit to which the sample value is supplied. The polarity is switched to the direction in which the signal is canceled. Summing circuit ₅₁ 0-5
The ₁₇ output signals are combined and output.

FIG. 2 shows an FFT system in which three stages of butterfly operations of N = 8 are superimposed, whereas an IFFT of N = 256 performs eight stages of butterfly operations. It should be noted that the method shown in FIG. 3 is not limited to the final stage, and in addition to this, the other stages can be similarly performed to further finely suppress the peak power.

The OFDM signal whose polarity has been switched is also subjected to FFT operation by switching its polarity in the receiving apparatus.
It needs to be decrypted. Therefore, when switching the polarity, it is necessary to inform the receiving device of the information in some form. From this point of view, it is necessary to limit the combination of the polarity switching to a pattern of a predetermined group or the like, and to ensure that the information is transmitted to the receiving device with little information.

When the input terminal voltage of the IFFT is set to 0 for the OFDM signal, the level of the corresponding carrier becomes 0. This is called a carrier hole, and this property is used when the transmission band is shared with other transmission schemes. For example, when an OFDM signal is transmitted in a transmission band overlapping with the NTSC system, a center carrier frequency portion of an NTSC system television signal and a carrier in a band for transmitting a chrominance signal are set to 0.

In each embodiment, the polarity switching information is transmitted at a specific carrier frequency. In each of the above embodiments,
Polarity control circuits 42 to 45 or polarity switching circuit 56
_{0-56 7} is 4 lines, but four arranged a carrier wave corresponding thereto. That is, the voltage of the terminal is kept at 0 in advance so that no output signal is generated from the IFFT circuit at the position of the frequency corresponding to the four carrier waves. In this manner, holes for four carrier waves are formed, and four oscillators that oscillate at the respective frequencies are provided. Normally, the output of this oscillator is kept off, but when the polarity of the IFFT is inverted, the output of the corresponding oscillator is added to the input of the quadrature modulator (FIG. 4), and the output of the oscillator is turned on via the frequency converter.
Transmitted together with FDM signal. The receiving device first checks whether there is a signal in a predetermined carrier hole, and if so, inverts the polarity of the FFT circuit corresponding to the signal and performs demodulation.

[0060]

As described above, according to the present invention,
By adding the modulated frequency division multiplexed signals output from n (n is an integer of 2 or more) arithmetic circuits to an adder circuit to generate a frequency division multiplexed signal having a desired number of carriers, a single frequency division multiplexed signal is generated. The peak power of the signal can be reduced to 1 / n as compared with the case where a frequency division multiplexed signal having a desired number of carriers is generated by the arithmetic circuit, and the peak generated by one of the arithmetic circuits among a plurality of arithmetic circuits can be reduced. By controlling or inverting the polarity of the signal generated from another arithmetic circuit at the power position, the instantaneous power of the output frequency division multiplexed signal can be further suppressed to a low value, so that the frequency division control where the peak power value is managed to be small The multiplexed signal can be input to the power amplifier in the transmission device, so that the margin of the power amplifier can be reduced, and the size and weight of the transmission device can be reduced, including the power supply device of the transmission device. It can be.

Further, according to the present invention, the peak power value of a frequency division multiplexed signal composed of a large number of synthesized information carriers can be suppressed to a small value. The average transmission power can be set large, the carrier power to noise power ratio (C / N) at the reception point can be improved, and the communication quality at a weak electric field position with a lower error rate can be improved. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a signal flow diagram of an example of a commonly used FFT.

FIG. 3 is a diagram showing a conventional example of a circuit at the last stage of an IFFT circuit and another example of the present invention in comparison.

FIG. 4 is a block diagram showing a configuration of a digital data transmitting / receiving apparatus to which the present invention is applied.

FIG. 5 is a diagram illustrating a frequency spectrum of an OFDM signal.

[Explanation of symbols]

2 Input Circuit 3 Clock Divider 4 Inverse Fast Fourier Transform (IFFT) Device 7 Quadrature Modulator 8, 18 Intermediate Frequency Oscillator 9, 19 90 ° Shifter 31 Digital Data Input Terminal 32 Data Distributor 33-36 IFFT Circuit (Operation Circuit ) 37-40 peak detection circuit 41 the data polarity judgment circuit (polarity control means) 42-45 polarity control circuit (polarity control means) 46 and 51 _{0-51 7} adder circuit 52 _{0-52 7} twiddle factor 55 the polarity judgment circuit 56 ₀ ~ 56 ₇ polarity switching circuit

Claims (5)

(57) [Claims] 1. A data divider for dividing a digital information signal into a plurality of signals, and a plurality of arithmetic circuits for generating a plurality of frequency division multiplexed signals modulated based on each of the digital information signals divided by the data divider. A plurality of peak detection circuits for detecting peak powers of a plurality of frequency division multiplexed signals extracted from the plurality of arithmetic circuits; and a detection of a power exceeding a threshold value among output detection peak powers of the plurality of peak detection circuits. Polarity control means for controlling the polarity of one or more frequency division multiplexed signals other than the frequency division multiplexed signal of peak power in a direction to cancel the detected peak power exceeding the threshold, and A frequency division multiplexing signal generator comprising: an addition circuit for adding and outputting a plurality of frequency division multiplexing signals. 2. The frequency division multiplex signal generating apparatus according to claim 1, wherein said plurality of arithmetic circuits are inverse fast Fourier transform circuits, and output an orthogonal frequency division multiplex signal from said addition circuit. 3. A data divider for dividing a digital information signal into a plurality of pieces, and a multiplication result of a previous-stage output and an addition of the preceding-stage output for each of a plurality of groups with respect to the digital information signal divided by the data divider. A plurality of arithmetic circuits for sequentially generating a plurality of frequency division multiplexed signals modulated from the last stage, and a plurality of polarity switching circuits for switching the polarity of the addition input of the last stage of each of the plurality of arithmetic circuits. Detecting a peak power and a peak position of the plurality of frequency division multiplexed signals based on a signal extracted from a part of each of the plurality of arithmetic circuits, and canceling the detected peak power exceeding a threshold. A polarity determining circuit that controls a plurality of polarity switching circuits; and an adding circuit that adds and outputs a frequency division multiplexed signal of the plurality of arithmetic circuits. Frequency division multiplex signal generator for. 4. The plurality of operation circuits are inverse fast Fourier transform circuits for performing butterfly operation, and the plurality of polarity switching circuits output a multiplication result by a twiddle factor input to a final stage addition circuit as an input signal. 4. The frequency division multiplexed signal generating apparatus according to claim 3, wherein the input signal is output with the polarity of the input signal unchanged or inverted based on the output signal of the polarity determination circuit. 5. The frequency division multiplexing system according to claim 1, wherein the polarity switching information is input to a specific input terminal of the arithmetic circuit, and the polarity switching information is output on a specific carrier. Signal generator.