JP2726555B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP2726555B2 JP2726555B2 JP2224694A JP22469490A JP2726555B2 JP 2726555 B2 JP2726555 B2 JP 2726555B2 JP 2224694 A JP2224694 A JP 2224694A JP 22469490 A JP22469490 A JP 22469490A JP 2726555 B2 JP2726555 B2 JP 2726555B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- silicon
- semiconductor device
- layer
- active element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 229920005989 resin Polymers 0.000 claims description 23
- 239000011347 resin Substances 0.000 claims description 23
- 238000007789 sealing Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 32
- 239000002184 metal Substances 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 20
- 229910000679 solder Inorganic materials 0.000 description 10
- 239000010409 thin film Substances 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- -1 that is Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は樹脂封止型半導体装置に係わり、特に、樹脂
製外囲器の内部に設置する半導体能動素子と外部電流端
子以外の樹脂製外囲器表面とが電気的に絶縁されている
樹脂封止型半導体装置に好適なものである。Description: Object of the Invention (Industrial Application Field) The present invention relates to a resin-encapsulated semiconductor device, and particularly to a semiconductor active element and an external current terminal installed inside a resin envelope. It is suitable for a resin-sealed semiconductor device in which the surface of a resin envelope other than the above is electrically insulated.
(従来の技術) 樹脂製外囲器により半導体能動素子を封止して使用す
る型の樹脂封止型半導体装置は多品種が開発市販されて
おり、封入する半導体能動素子の種類によって外囲器の
形状や種類も多岐にわたっている。ところで、樹脂封止
型半導体装置では樹脂製外囲器の内部に設置する半導体
能動素子と外部電流端子以外の樹脂製外囲器表面とが絶
縁された型のものがあり、これを第1図により説明する
と、いわゆるリードフレーム(Lead Frame)のベッド
(Bed)部1に半導体能動素子3が半田層2を介してマ
ウント(Mount)され、半導体能動素子3に設置した電
極(図示せず)に例えば超音波ボンディング(Bondin
g)法により固着した金属細線例えばAlやAu細線4をリ
ードフレームのリード端子5に同じ方法で圧着して封止
樹脂層6外に導出する。この外部に導出したリード端子
を通常アウターリードと呼称している。半導体能動素子
3とは例えばシリコン(Silicon)から成る半導体基板
にモノリシック(Monolythic)に例えばトランジスタ
(Transister)を造り込んだペレット(Pellet)であ
る。図から明らかなように封止樹脂層6により内部の半
導体素子と外部端子以外の樹脂製外囲器表面とが電気的
に絶縁されているので、ユーザ(User)が購入後この装
置を使用する時、この装置と別個の放熱板に取付けるの
にマイカ(Mika)などの絶縁物を使わずに電気的絶縁が
できる。このような機種には第1図の他に第2図に明ら
かにしたものが使われており、これは封止樹脂層6の代
わりに実装基板の一部として使われているセラミック
(Ceramic)により半導体能動素子3が絶縁されてい
る。第1図の樹脂封止型半導体装置がモールドタイプ
(Mold Type)第2図のそれがモジュール(Module)タ
イプと記載する。モジュールタイプではセラミック板7
の両面に金属製薄膜即ち回路パターン(Pattern)を形
成した例えば銅薄膜8、8′を形成して実装基板を構成
し、ここに設置する半田層9により半導体能動素子2を
固着したものである。金属製薄膜8に形成した回路パタ
ーン夫々を他の部分11と今後記載する。(Prior Art) A wide variety of resin-encapsulated semiconductor devices of a type in which a semiconductor active element is sealed and used by a resin envelope have been developed and sold on the market. There are a wide variety of shapes and types. Meanwhile, there is a resin-encapsulated semiconductor device in which a semiconductor active element installed inside a resin envelope and a surface of the resin envelope other than an external current terminal are insulated. The semiconductor active element 3 is mounted on a bed portion 1 of a so-called lead frame via a solder layer 2 and mounted on an electrode (not shown) provided on the semiconductor active element 3. For example, ultrasonic bonding (Bondin
The thin metal wire, for example, the Al or Au thin wire 4 fixed by the method g) is crimped to the lead terminal 5 of the lead frame by the same method and led out of the sealing resin layer 6. This lead terminal led out is usually called an outer lead. The semiconductor active element 3 is a pellet (Pellet) in which, for example, a transistor (Transister) is monolithically (Monolythic) formed on a semiconductor substrate made of silicon (Silicon). As is clear from the figure, since the internal semiconductor element and the surface of the resin envelope other than the external terminals are electrically insulated by the sealing resin layer 6, the user uses the device after purchasing. At this time, electrical insulation can be achieved without using an insulator such as Mika to attach to a heat sink separate from this device. 2 is used in such a model, in addition to FIG. 1, which is used as a part of the mounting substrate instead of the sealing resin layer 6. The semiconductor active element 3 is insulated. The resin-encapsulated semiconductor device in FIG. 1 is described as a mold type (Mold Type) and that in FIG. 2 is described as a module type. Ceramic plate 7 for module type
A mounting substrate is formed by forming metal thin films, that is, copper thin films 8 and 8 'on both sides of which a circuit pattern (Pattern) is formed, and the semiconductor active element 2 is fixed by a solder layer 9 installed here. . Each of the circuit patterns formed on the metal thin film 8 will be described as another portion 11 hereinafter.
なお半導体能動素子3に形成した電極(図示せず)に
はモールドタイプと同じく金属細線例えばAlやAu細線10
を例えば超音波ボンディング法により圧着後、いわゆる
2′nd超音波ボンディングにより細線10の他端を金属製
薄膜8の他の部分11に固着する。ところでモジュールタ
イプと他の機器との電気的導通を図るために金属製薄膜
8の他の部分11にリード12を設置するのには金属製リー
ドホルダー(Holder)12′を利用するが詳細は後述す
る。一方セセラミック基板7の他面に設置された金属製
薄膜8′には低融点の半田層13により銅製の放熱板14を
固着する。The electrodes (not shown) formed on the semiconductor active element 3 have thin metal wires such as Al and Au thin wires 10 as in the mold type.
Is bonded by, for example, an ultrasonic bonding method, and the other end of the fine wire 10 is fixed to the other portion 11 of the metal thin film 8 by so-called 2'nd ultrasonic bonding. By the way, a metal lead holder (Holder) 12 'is used to install the lead 12 on the other part 11 of the metal thin film 8 in order to achieve electrical conduction between the module type and other devices. I do. On the other hand, a heat radiating plate 14 made of copper is fixed to the metal thin film 8 ′ provided on the other surface of the ceramic substrate 7 by a solder layer 13 having a low melting point.
ところで、図示するように金属製リード12は樹脂製外
囲器15を突抜けて設置されているのは予め樹脂製ホルダ
ー12′及び金属製リード12を一体に成型しておいてから
金属製薄膜8の他の部分11と金属製リード12間に配置し
た低融点の半田層13を介して固着する方式を採ってい
る。これによりモジュール構体が得られるが樹脂製外囲
器15との関係を説明する。By the way, as shown in the figure, the metal lead 12 is provided so as to protrude through the resin envelope 15 because the resin holder 12 'and the metal lead 12 are integrally molded in advance and then the metal thin film is formed. In this method, a low-melting-point solder layer 13 arranged between the other portion 11 and the metal lead 12 is used. Thus, a module structure is obtained. The relationship with the resin envelope 15 will be described.
第2図に明らかなように樹脂製外囲器15は側面部分A
と蓋部分Bとで構成されており、蓋部分Bの金属製リー
ド12を一体化した樹脂製ホルダー12′が金属製薄膜8の
他の部分11に半田層13を介して固着され、その後銅製の
放熱板14と側面部分Aを接着剤層16によって固着し、最
後に側面部分Aと樹脂製ホルダー12′とを熱硬化製樹脂
15′により封止してモジュールタイプを完成する。この
結果モジュールタイプでは銅製の放熱板14が露出した構
造となっており、酸化を防止の観点からNiメッキ層を被
覆している。なお、モールドタイプ及びモジュールタイ
プのような外囲器の内部と表面の電気的絶縁がなされて
いない型の樹脂封止型半導体装置として第3図のタイプ
が知られており、ベッド部1を露出した点が異なってい
る。As is apparent from FIG. 2, the resin envelope 15 has a side portion A.
And a lid portion B, and a resin holder 12 ′ in which the metal lead 12 of the lid portion B is integrated is fixed to the other portion 11 of the metal thin film 8 via a solder layer 13 and then made of copper. The heat radiating plate 14 and the side portion A are fixed by an adhesive layer 16, and finally, the side portion A and the resin holder 12 'are joined by a thermosetting resin.
Seal with 15 'to complete the module type. As a result, the module type has a structure in which the copper radiator plate 14 is exposed, and covers the Ni plating layer from the viewpoint of preventing oxidation. The type shown in FIG. 3 is known as a resin-encapsulated semiconductor device of a type in which the inside and the surface of the envelope are not electrically insulated, such as a mold type and a module type. Is different.
(発明が解決しようとする課題) 樹脂封止型半導体装置に相当するモールドタイプ及び
モジュールタイプの問題点としては第3図に示したよう
に能動素子をマウントしたベッド部が絶縁されていない
種類に比べて、外囲器の飽和熱抵抗値Rth(j−c)が
大きいので、同じ能動素子を搭載した場合、半導体装置
として許容できるパワー損失値Pcが小さくなる点が上げ
られる。即ち、モールドタイプではベッド部の裏側を被
覆する封止樹脂層の厚さがどうしても薄くなるために絶
縁耐圧が弱くなり、その上薄い封止樹脂層内には巣が発
生し易くて信頼性が悪化して歩留りが低下する。従って
熱抵抗上薄い封止樹脂層が望ましくても限界がある。ま
た同じくモジュールタイプに使用するセラミックの熱伝
導率は金属や半田のそれよりも小さく、しかもセラミッ
ク層の厚さは製造技術上の制約から金属などと同等の熱
伝導率が得られるだけ薄くできないのが原因である。(Problems to be Solved by the Invention) The problems of the mold type and the module type corresponding to the resin-encapsulated semiconductor device are as follows. As shown in FIG. 3, the bed on which the active element is mounted is not insulated. In comparison, since the envelope has a large saturation thermal resistance value Rth (j−c), when the same active element is mounted, the power loss value Pc allowable as a semiconductor device is reduced. In other words, in the mold type, the thickness of the sealing resin layer covering the back side of the bed portion is inevitably thin, so that the withstand voltage is weak. In addition, nests are easily generated in the thin sealing resin layer, and the reliability is low. Deterioration decreases yield. Therefore, there is a limit even if a thin sealing resin layer is desirable in terms of thermal resistance. Also, the thermal conductivity of the ceramic used for the module type is smaller than that of metal or solder, and the thickness of the ceramic layer can not be thin enough to obtain the same thermal conductivity as that of metal due to manufacturing technology restrictions. Is the cause.
例えば現在使われている厚さ0.5mmの銅製リードフレ
ームと同等な熱伝導率を保持するには使用するセラミッ
クの厚さを0.02mm以下にしなければならないが、現状で
は0.6mm位が限界である。For example, in order to maintain the same thermal conductivity as the 0.5 mm thick copper lead frame currently used, the thickness of the ceramic used must be less than 0.02 mm, but currently the limit is about 0.6 mm .
本発明はこのような事情により成されたもので、特
に、飽和熱抵抗抵抗を改善することを目的とするもので
ある。The present invention has been made in view of such circumstances, and has as its object to improve, in particular, the saturation thermal resistance.
[発明の構成] (課題を解決するための手段) 本発明に係る樹脂封止型半導体装置は、表裏面を有す
る第1のシリコン製放熱板と,前記第1のシリコン製放
熱板の表面に設けられた絶縁層と,前記絶縁層上に設け
られた第2のシリコン製放熱板と,前記第2のシリコン
製放熱板上に接続された半導体素子と,前記第1のシリ
コン製放熱板の裏面を除き、この放熱板及び前記半導体
素子を覆う樹脂封体とに特徴がある。[Structure of the Invention] (Means for Solving the Problems) A resin-encapsulated semiconductor device according to the present invention includes a first silicon radiator plate having front and rear surfaces, and a first silicon radiator plate having a front surface and a back surface. An insulating layer provided, a second silicon radiator provided on the insulating layer, a semiconductor element connected on the second silicon radiator, and a first silicon radiator. Except for the back surface, there is a characteristic in the heat sink and the resin sealing body that covers the semiconductor element.
(作用) 本発明に適用する半導体能動素子には直流または交流
を長時間印加することが多く、動作時に150℃程度に発
熱するので、過渡熱抵抗でなく飽和熱抵抗値を制御する
ことが不可欠であるために、熱伝導率の良いシリコンを
選定して効果的な放熱を実施するものである。しかも、
放熱板を構成するシリコン板の厚さ方向に主表面に対応
する電気的分離層を形成して要求される耐DC2500V、AC3
500Vを保障しており、しかも銅に比較して軽量である。(Action) DC or AC is often applied to the semiconductor active element applied to the present invention for a long time, and generates about 150 ° C. during operation. Therefore, it is essential to control not the transient thermal resistance but the saturation thermal resistance. Therefore, effective heat dissipation is performed by selecting silicon having good thermal conductivity. Moreover,
DC2500V, AC3 required by forming an electrical isolation layer corresponding to the main surface in the thickness direction of the silicon plate that constitutes the heat sink
It guarantees 500V and is lighter than copper.
更に電気的分離層の設置により互いに隔てられたシリ
コン板の中外部に露出する部分を放熱板として機能さ
せ、他方には半導体能動素子の外に電子回路構成に必要
な各種の回路部品を設置することができる利点もある。Further, a portion exposed to the inside and outside of the silicon plate separated from each other by providing an electrical separation layer is made to function as a heat sink, and on the other side, various circuit components necessary for electronic circuit configuration are provided outside the semiconductor active element. There are also advantages that can be.
(実施例) 本発明に係わる実施例を第4図及び第5図を参照して
説明するが、理解を助けるために従来技術と同じ部品に
も新しい番号を付ける。両図に示すようにリードフレー
ム20のアウターリード(Outer Lead)21は水平方向に延
長して樹脂封止型半導体装置の高さ方向を縮小してコン
パクト(Compact)にして他の機器への取付けに便利な
ように配慮している。(Embodiment) An embodiment according to the present invention will be described with reference to FIGS. 4 and 5, but the same parts as those in the prior art will be given new numbers to facilitate understanding. As shown in both figures, the outer lead (Outer Lead) 21 of the lead frame 20 is extended in the horizontal direction to reduce the height direction of the resin-encapsulated semiconductor device to be compact and attached to other devices. Consideration for convenience.
本発明の基本的な構造を明らかにした第4図にあるよ
うに、鉄、鉄ニッケル合金またはクラッド層を備えた鉄
や鉄ニッケル合金などの材料で構成するリードフレーム
20には常法通りにベッド部22やインナーリード(Inner
Lead)23を設け、ベッド部22には半導体能動素子24例え
ばパワー(Power)トランジスタを半田層25を介してマ
ウント(Mount)固着する。更にシリコン製放熱板を用
意するが、その厚さの中程には表面に対応して珪素酸化
物から成る電気的分離層26を厚さ5〜6μmに設置する
ので、いわゆるIPD(Inteligent Power Device)も形成
可能になる。即ち、シリコン製放熱板を構成する上側27
−Aに半導体能動素子24などを形成し、下側の27−Bが
放熱板として機能することになる。これらの形成にはシ
リコン板と、シリコン板に被覆した酸化物層を密着させ
ていわゆる接着工程により形成することもできる。この
接着とは清浄な被覆着面を密着させることによりもとの
組織と多少違ったものが形成され、しかも、一体化した
ものの機械的強度は十分でかつ、電気的な障害は全くな
いものである。As shown in FIG. 4 which clarifies the basic structure of the present invention, a lead frame made of a material such as iron, iron-nickel alloy or iron or iron-nickel alloy having a cladding layer.
20 has a bed 22 and an inner lead (Inner
A lead 23 is provided, and a semiconductor active element 24, for example, a power transistor is fixed to the bed 22 via a solder layer 25. Further, a silicon radiator plate is prepared. In the middle of the thickness, the electrical isolation layer 26 made of silicon oxide is set to a thickness of 5 to 6 μm corresponding to the surface. ) Can also be formed. That is, the upper side 27 constituting the silicon radiator plate
The semiconductor active element 24 and the like are formed on -A, and the lower 27-B functions as a heat sink. These can be formed by a so-called bonding step in which a silicon plate and an oxide layer coated on the silicon plate are brought into close contact with each other. This adhesion means that a slightly different structure from the original structure is formed by bringing the clean coated surface into close contact, and the mechanical strength of the integrated structure is sufficient and there is no electrical obstacle at all. is there.
更に、半導体能動素子24例えばジャイアントランジス
タの電極(図示せず)とインナーリード23を金属細線例
えばAlやAu28の一端と超音波ボンディングにより固着す
るが、通常前記電極との超音波ボンディングがいわゆる
1′stボンディングで、インナーリード23とのそれが
2′ndボンディングとして行われる。Further, the semiconductor active element 24, for example, an electrode (not shown) of a giant transistor, and the inner lead 23 are fixed to one end of a thin metal wire, for example, Al or Au 28 by ultrasonic bonding. By st bonding, the bonding with the inner lead 23 is performed as 2'nd bonding.
話が前後するがシリコン製放熱板の上側27−Aの半導
体能動素子24搭載面は半田付けが可能になるようにラッ
ピング(Lapping)処理とNiメッキ処理を行ってから半
導体能動素子24の半田付け工程を行う。Before and after, the semiconductor active element 24 mounting surface on the upper side 27-A of the silicon radiator plate is subjected to lapping and Ni plating so that soldering is possible, and then the semiconductor active element 24 is soldered. Perform the process.
前記のようなボンディング工程を終えたリードフレー
ムマウント構体と、電気的分離層26を形成したシリコン
製放熱板27−A、27−Bは低融点半田層29により両者を
一体としてから、樹脂製外囲器31の側面Bをシリコン製
放熱板27−A、27−Bに接着剤層30により接着する。更
にまた、樹脂製外囲器28の蓋部Cを側面Bに保護材31例
えばゲル(Gel)状高分子樹脂と共に封止して樹脂封止
型半導体装置が完成される。The lead frame mount structure after the above-described bonding process and the silicon radiating plates 27-A and 27-B on which the electrical isolation layer 26 is formed are integrated with each other by the low melting point solder layer 29. The side surface B of the enclosure 31 is bonded to the silicon radiating plates 27-A and 27-B by the adhesive layer 30. Furthermore, the lid portion C of the resin envelope 28 is sealed on the side surface B together with the protective material 31, for example, a gel-like polymer resin, to complete the resin-encapsulated semiconductor device.
第5図には他の実施例用に提出したもので、第4図に
使用した番号はそのまま付けているが、違う点はシリコ
ン製放熱板の上側27−Aの厚さ方向にも電気的分離層26
を形成していわゆる島領域D、E、Fが形成されている
点である。In FIG. 5, the same reference numerals as in FIG. 4 are used, but the difference is that the electrical direction is also applied to the thickness direction of the upper side 27-A of the silicon radiator plate. Separation layer 26
Is formed to form so-called island regions D, E, and F.
即ち、島領域Dにはモノリシックに例えばパワートラ
ンジスタ(図示せず)を形成し、電気的分離層26により
区分された領域Gを中継点とし、ここにリードフレーム
20のインナーリード23を低融点半田層29により固着す
る。そしてパワートランジスタの電極(図示せず)とイ
ンナーリード23間にはAlまたはAuなどの金属細線28を例
えば超音波ボンディング法により固着する。That is, for example, a power transistor (not shown) is monolithically formed in the island region D, and the region G divided by the electrical isolation layer 26 is used as a relay point, and a lead frame is formed here.
The 20 inner leads 23 are fixed by the low melting point solder layer 29. Then, a thin metal wire 28 such as Al or Au is fixed between an electrode (not shown) of the power transistor and the inner lead 23 by, for example, an ultrasonic bonding method.
パワートランジスタに代えて例えば集積回路素子を造
り込み、領域Gにいわゆる個別半導体素子を取付けてい
わゆるIPD素子とすることも可能である。更にシリコン
製放熱板の上側27−Aを上から見て中心付近から周縁に
向けて複数の電気的分離層26を形成して、区分されたシ
リコン製放熱板の上側27−A部分に各種の回路成分を形
成することも可能になる。この場合シリコン製放熱板の
下側27−Bは当然放熱作用を受持つことになる。For example, an integrated circuit element may be formed instead of the power transistor, and a so-called individual semiconductor element may be attached to the region G to form a so-called IPD element. Further, a plurality of electrical isolation layers 26 are formed from the vicinity of the center to the periphery when the upper side 27-A of the silicon radiator plate is viewed from above, and various portions are formed on the upper 27-A portion of the divided silicon radiator plate. It is also possible to form circuit components. In this case, the lower side 27-B of the silicon heat radiating plate naturally takes charge of the heat radiating action.
[発明の効果] このように本発明に係わる樹脂封止型半導体装置は絶
縁がされていない半導体装置と同等な低い飽和熱抵抗特
性が得られる。と言うのは、電気的分離層を構成する酸
化物層の厚さが5〜6μmと薄く形成できるので従来製
品に比べて飽和熱抵抗特性が得られる。従って、半導体
能動素子としてパワートランジスタ素子を搭載したモー
タの連続運転においてシリコン製放熱板の機能により低
い飽和熱抵抗特性が得られるとためにパワー素子本来の
実力を引出すと共にモータその物の信頼性と寿命も延ば
すことができる。電気的分離層に利用する珪素酸化物例
えば3μm厚の二酸化珪素の熱伝導性は0.6μm厚のAl2
O3セラミックの約20倍であることを付記する。[Effect of the Invention] As described above, the resin-encapsulated semiconductor device according to the present invention can obtain a low saturation thermal resistance characteristic equivalent to that of a non-insulated semiconductor device. This is because the oxide layer constituting the electrical isolation layer can be formed as thin as 5 to 6 μm, so that a saturated thermal resistance characteristic can be obtained as compared with a conventional product. Therefore, in the continuous operation of a motor equipped with a power transistor element as a semiconductor active element, the function of the silicon radiator plate enables low saturation thermal resistance characteristics to be obtained. Life can be extended. The thermal conductivity of silicon oxide used for the electrical isolation layer, for example, silicon dioxide having a thickness of 3 μm is Al 2 having a thickness of 0.6 μm.
Note that it is about 20 times that of O 3 ceramic.
第1図乃至第3図は従来の樹脂封止型半導体装置の断面
図、第4図及び第5図は本発明の実施例を示す断面図で
ある。 1,22:ベッド部、 2、9、13、25、29:半田層、 3、24:半導体能動素子、 4、10、28:金属細線、 7:セラミック板、8、8′:金属製薄膜、 14、27−A、27−B:放熱板、 12:リード、12′:リードホルダー、 15、31、B、C:外囲器、 15′熱硬化製樹脂、16、30:接着材層、 26:電気的分離層。1 to 3 are sectional views of a conventional resin-encapsulated semiconductor device, and FIGS. 4 and 5 are sectional views showing an embodiment of the present invention. 1,22: bed part, 2, 9, 13, 25, 29: solder layer, 3, 24: semiconductor active element, 4, 10, 28: thin metal wire, 7: ceramic plate, 8, 8 ': metal thin film , 14, 27-A, 27-B: heat sink, 12: lead, 12 ': lead holder, 15, 31, B, C: envelope, 15' thermosetting resin, 16, 30: adhesive layer , 26: electrical isolation layer.
Claims (1)
と,前記第1のシリコン製放熱板の表面に設けられた絶
縁層と,前記絶縁層上に設けられた第2のシリコン製放
熱板と,前記第2のシリコン製放熱板上に接続された半
導体素子と,前記第1のシリコン製放熱板の裏面を除
き、この放熱板及び前記半導体素子を覆う樹脂封体とを
有することを特徴とする樹脂封止型半導体装置1. A first silicon radiator plate having front and rear surfaces, an insulating layer provided on a surface of the first silicon radiator plate, and a second silicon radiator provided on the insulating layer. A plate, a semiconductor element connected on the second silicon radiator plate, and a resin sealing body covering the radiator plate and the semiconductor element except for the back surface of the first silicon radiator plate. Characteristic resin-encapsulated semiconductor device
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2224694A JP2726555B2 (en) | 1990-08-27 | 1990-08-27 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2224694A JP2726555B2 (en) | 1990-08-27 | 1990-08-27 | Resin-sealed semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04106962A JPH04106962A (en) | 1992-04-08 |
JP2726555B2 true JP2726555B2 (en) | 1998-03-11 |
Family
ID=16817778
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2224694A Expired - Fee Related JP2726555B2 (en) | 1990-08-27 | 1990-08-27 | Resin-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2726555B2 (en) |
-
1990
- 1990-08-27 JP JP2224694A patent/JP2726555B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH04106962A (en) | 1992-04-08 |
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