JP2702259B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device with improved test efficiency of operation functions.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional semiconductor integrated circuit device in which different types of memories are integrated into one chip. In the figure, reference numeral 1 denotes an EPROM (Electrically Programmable ROM: electrically writable read-only memory); SRAM (Stat
3 and 4 are write / read control circuits for the EPROM block 1 and the SRAM block 2, 5 are input buffer circuits for address signals A1 to A8, and 6 are various control signals [ In this example, CE (chip select signal), OE (data output enable signal), R /
W (read / write signal)] and the like, a control signal generating circuit for generating write / read control signals 7 to 10 for the memory blocks 1 and 2; 11 is an address signal; and 12 selects each memory block 1 and 2. Is a data bus for inputting and outputting data between the memory blocks 1 and 2 and the outside. 14, 15 are select signals for each memory block generated by the decode circuit 12,
In this example, when the signal is at the “Low” level, it is a low active signal for selecting the memory blocks 1 and 2.

Further, as a power supply of the semiconductor integrated circuit device, V is used as a write voltage for a memory cell in the EPROM block 1.
_PP is V _CC as a power supply for the SRAM block, V _DD is a power supply for peripheral circuits including the EPROM block 1 (however, the SRAM block 2 is not included), and GND is a reference potential (ground level).

 Next, the operation will be described.

First, in a semiconductor integrated circuit device (hereinafter, referred to as a composite IC) using such heterogeneous memory blocks, an address region is allocated to each of them as an operation region in order to perform a write / read operation independently. An example of this state will be described with reference to FIG. As shown in the figure, a hatched area 31 is an address area (20 _{H to} 3 _{F H in} hexadecimal) for the SRAM block 2, while an area 32 is an address area ( _1H for the EPROM block 1).
Expressed in hexadecimal number greater than 80 _H ~FF _H). The above address is A
When inputted to 1 to A8, the signal is decoded by the decode circuit 12, and a low active select signal is generated for each memory block. For the address 20 _H ~3F _H
Select signal 15 of SRAM block 2 (hereinafter referred to as CSRAM)
But so that the select signal 14 of the EPROM block 1 (hereinafter referred to as CSROM) is generated for the same 80 _H ~FF _H.

On the other hand, write / read control signals for each memory block include external input signals, for example, CE, OE, R / W
The signal is generated by the control signal generation circuit 6 based on the above.
A write pulse signal 7 (hereinafter referred to as PRGROM) and a read signal 8 (hereinafter referred to as RDROM) are generated for the EPROM block 1, and similarly, a write pulse signal 9 (hereinafter referred to as WRRAM) for the SRAM block 2. ) And readout signal 10
(Hereinafter referred to as RDRAM). Further, data exchange between each of the memory blocks 1 and 2 and the outside of the composite IC is performed via the data bus 13.

 Next, the operation of the composite IC will be described.

First, a method for writing to a memory cell of the EPROM block 1, a low active the CSROM14 set to any address between the address A1~A8 80 _H ~FF _H, but at this time, the CSRAM15 "High "Level, and the SRAM block 2 does not operate. Furthermore, CE, O input from outside
Each signal such as E and each power supply (V _PP is 12.5V at writing, V _DD = 6.0
V) in combination with PRGROM in the control signal generation circuit 6.
A signal 7 is generated, data to be written is set, and data is written to a desired EPROM memory cell via the data bus 13.

As for the verify method at the time of writing, addresses A1 to A8 are set in the same manner as at the time of writing, and each power supply (V _PP = 12.5V, V _DD = 6.
0V) and the control signals CE and OE to establish the verify mode, thereby generating the RDROM signal 8, reading out the data of the desired EPROM memory cell, and outputting it via the data bus 13 for confirmation.

EPROM for writing / reading operation to SRAM block 2
As in the case of the block 1, first set to any of the corresponding address 20 _H ~3F _H in the address A1 to A8, CSRAM signal 1
5 is set to low active. The power supply is SRAM block 2
And V _CC = V _DD = 5.0V so that the peripheral circuits can operate. Further, by inputting control signals CE, OE, R / W, etc., the control signal generation circuit 6 generates a WRRAM signal 9 and writes the set data to a desired memory cell via the data bus 13.

At the time of reading, the same addresses A1 to A8 as at the time of writing are set, and by setting the control signals CE, OE, R / W, etc., the RDR
An AM signal 10 is generated, data of a desired SRAM memory cell is read, and output via a data bus 13.

Further, in such a complex IC device, in order to easily perform a writing operation and a reading operation to the built-in EPROM memory cell, the same memory capacity is used for the memory capacity of the EPROM memory block, the number of control signals, the timing setting, and the like. It is often designed to be equivalent to a general-purpose EPROM device.

Next, consider a test method for a composite IC device having the above-described EPROM block 1 and SRAM block 2.
In the composite IC composed of the EPROM block 1 and the SRAM block 2 having the above configuration, it is considered that a large-scale LSI tester with sufficient functions is required to sufficiently inspect each memory block and related peripheral circuits. Regarding the EPROM block 1 as described above, its write / read operation can be confirmed by using a commercially available write device and an appropriate pin conversion device.

[Problems to be solved by the invention]

Since the conventional semiconductor integrated circuit device is configured as described above, on the EPROM block side, a write / verify operation is performed using a commercially available writing device to check the basic operation and the test of each EPROM memory cell. However, since there is no such simple means on the SRAM block side, a large LSI test apparatus is required to confirm basic operation, and in particular, we do not own such a large test apparatus The general customer has a problem in that the operation of the EPROM block can be confirmed, but no test can be performed on the SRAM block, especially on the important SRAM memory cells.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and is a semiconductor integrated circuit device capable of performing a write / read test on each memory cell block incorporating a composite IC using a simple device. The purpose is to obtain.

[Means for solving the problem]

The semiconductor integrated circuit device according to the present invention includes, for example, an EPRO
In a composite IC composed of different types of memory blocks such as M and SRAM, means for inputting a test mode setting signal and control for outputting a control signal for writing / reading to / from each memory block A signal generation circuit;
A decode circuit for selecting any one of the memory blocks, an output of the control signal generation circuit and the test mode setting signal are input, and converted to be compatible with write / read control signals of various memories. And a test mode generating circuit for outputting a test mode setting signal, and when a test mode setting signal is inputted, a memory cell of the corresponding EPROM block or the corresponding SRAM block among the memory blocks is selected by a predetermined select signal. In addition to the selection, a write / read control signal to be output to the EPROM block is converted and output to the SRAM block as a write / control signal for the SRAM block.

[Action]

In the present invention, an EPROM
A part of the pulse signal used for writing / reading the block is converted in the chip and applied to the writing / reading of the SRAM block, so that it is used for each memory cell block with a built-in composite IC. The write / read test can be performed using a simple device.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. The same reference numerals as in FIG. 2 denote the same or corresponding parts, 16 denotes an input terminal of a test mode setting signal 17, and 18 denotes an address. The decoder circuit 19 receives the signals A1 to A8 as inputs and receives the test mode setting signal 17 as an input. The decoder 19 receives the test mode setting signal 17 and the write / read control signals 7 to 10 for each memory block as inputs. A test mode generating circuit for generating a test mode signal, which is configured by combining logic circuits.

 Next, the operation will be described.

First, when the test mode setting signal 17 is a "Low" level input, each signal CSROM14, CSRAM15, control signal PRGROM7, RDROM8, WRRAM9, RDRA of each signal in the conventional example.
Since the signal system is the same as that of M10, in this case, the operation is exactly the same as that of the conventional example, and the detailed description thereof will be omitted.

On the other hand, when the test mode setting signal 16 is a “High” level input, that is, in the test mode, the decoding circuit
18 sets CSROM14 to “H” regardless of address inputs A1 to A8.
Since the level is the level, the EPROM block 1 is always unselected. On the other hand, since the CSRAM 15 also becomes the “L” level regardless of the address input, the SRAM block 2 is in the selected state.

Further, in the test mode generating circuit 19, the write / verify control signals PRGROM7 and R
The output is converted between the DROM 8 and the write / read control signals WRRAM9 and RDRAM10 for the SRAM block, and the PRGROM7 is transmitted to the signal that should be originally WRRAM9 (indicated by 20 in the figure). Similarly, RDROM 8 is transmitted to the signal which should originally be RDRAM 10 (this is indicated at 21 in FIG. 1).

As described above, the signals PRGROM7 and RDROM8 are applied to both the EPROM block 1 and the SRAM block 2. However, since the SRAM block 2 side is selected by the above-described CSROM 14 and CSRAM 15, only the SRAM block 2 is written / written.
The read operation is enabled.

Therefore, the control signal PRGROM7 and the basic pulse waveform and timing of the RDROM8 at the time of the write / verify operation of the EPROM block 1 correspond to the control signal WRRAM9 and the basic pulse waveform and timing of the RDRAM10 at the time of the write and read operation of the SRAM block 2, respectively. If the compatible signals are compatible, the write / verify operation of EPROM block 1
Writing / reading to / from the RAM block 2 can be executed.

In the above embodiment, EPROM is used as the ROM, and SRAM is used as the RAM.
However, the same effect can be obtained with a storage device having another memory structure.

Further, the configuration of the test mode generation circuit and the generation circuit of the select signal for each memory may be configured using other logic circuits.

〔The invention's effect〕

As described above, according to the semiconductor integrated circuit device of the present invention, the pulse signal used for writing / reading of the EPROM block is partially converted in the chip and applied to the writing / reading of the SRAM block. I decided to use
Particularly, there is an effect that the basic operation of writing and reading can be easily confirmed even for various memory cells of a complex IC for which a function test is difficult without using a large-scale LSI test apparatus which is an expensive test apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to one embodiment of the present invention, FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit device, and FIG. 3 is a built-in memory (EPROM) in the conventional semiconductor integrated circuit device. , SRAM) are shown. 1 ... EPROM block, 2 ... SRAM block, 3 ... EPR
OM write / read circuit, 4 ... SRAM write / read circuit, 5 ... input buffer circuit, 6 ... control signal generation circuit, 7 ... PRGROM (ROM write signal), 8 ... RDROM (RO
M verify signal), 9 WRRAM (RAM write signal), 1
0: RDRAM (RAM read signal), 11: Address signal, 1
2,18 …… decoding circuit, 13 …… data bus, 14 …… CSRO
M (ROM select signal), 15: CSRAM (RAM select signal), 16: Test mode setting signal input terminal, 17 ...
Test mode setting signal, 19: Test mode generation circuit, 20: PRGROM signal in test mode, 21: RDROM signal in test mode, 31: SRAM address area, 32: EPR
OM address area, V _PP …… EPROM writing power supply, V _CC …… S
Independent power supply for RAM, V _DD …… EPROM, power supply for peripheral circuits, GND…
... Reference potential (ground level). In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A semiconductor memory device comprising a plurality of memory blocks each composed of an EPROM and an SRAM operable independently, arranged on a single chip, comprising: means for inputting a test mode setting signal; A write / read circuit for the memory block, a control signal generating circuit for outputting a write / read control signal for performing a write / read to each of the write / read circuits, and when the test mode setting signal is input, A decode circuit that generates a predetermined select signal and selects either the corresponding EPROM block or the corresponding SRAM block from among the memory blocks, and receives the output of the control signal generation circuit and the test mode setting signal as input and performs a test. When the mode setting signal is input, the write / read control signal to be output to the EPROM block A semiconductor integrated circuit device comprising: a test mode generating circuit that outputs a write / control signal of an M block to the SRAM block side.