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JPH01151100A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device

Info

Publication number
JPH01151100A
JPH01151100A JP62310303A JP31030387A JPH01151100A JP H01151100 A JPH01151100 A JP H01151100A JP 62310303 A JP62310303 A JP 62310303A JP 31030387 A JP31030387 A JP 31030387A JP H01151100 A JPH01151100 A JP H01151100A
Authority
JP
Japan
Prior art keywords
semiconductor memory
memory device
word lines
time
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62310303A
Other languages
Japanese (ja)
Inventor
Yasushi Terada
寺田 康
Takeshi Nakayama
武志 中山
Kazuo Kobayashi
和男 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62310303A priority Critical patent/JPH01151100A/en
Publication of JPH01151100A publication Critical patent/JPH01151100A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To shorten the time necessary to write a word line and to shorten a test time by selecting simultaneously plural word lines at the time of the test. CONSTITUTION:At the time of the test, writing is simultaneously executed to plural word lines. Namely, when a signal TE to show a test mode is outputted, namely, when a signal to inverse of TE is 'L', outputs xi and the inverse of xi of an address buffer become 'H'. Thus, when a pair of address signals (xi, the inverse of xi) is made into 'H', two word lines wi and the inverse of wi are selected and when two pairs of the address signals are made into the 'H', four word lines are simultaneously selected. Thus, the testing time can be shortened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は電気的に消去・書込みが可能な不揮発性半導
体記憶装置(EEFROM)に関し、特にそのテストモ
ードの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically erasable/programmable nonvolatile semiconductor memory device (EEFROM), and particularly relates to an improvement in its test mode.

〔従来の技術〕[Conventional technology]

第3図は従来のE E P ROMのブロック図を示す
。メモリアレイlの周辺に入力アドレスデータに対応し
て1ビツトもしくは1バイトのメモリセルを選択するロ
ウデコーダ2.コラムデコーダ3が配置されている。、
Yゲート4はコラムデコーダ3により選択されたYアド
レスのビット線をI/O線(図示せず)に接続するため
のものである。
FIG. 3 shows a block diagram of a conventional EEPROM. A row decoder 2 that selects a 1-bit or 1-byte memory cell in response to input address data around the memory array l. A column decoder 3 is arranged. ,
The Y gate 4 is for connecting the bit line of the Y address selected by the column decoder 3 to an I/O line (not shown).

コラムラッチ5は入力データをランデし、1本のワード
線に接続されているすべてのメモリセルについて一括書
込みを行なうためのものである。Vppスイッチ6は書
込み時に選択されたワード線、ビット線を高圧に立ち上
げる回路である。入力XアドレスはXアドレスバッファ
7に入力され、レベル変換(TTLレベル→MOSレベ
ル)されるとともに、相補的な信号(xi、xT)を生
成する。Xアドレスバッファ7の入出力波形を第5図に
示す。また、従来のロウデコーダ2の具体的な回路の一
例を第4図に示す。これは多入力のANDゲートから成
り、各入力はxiもしくはマゴ(i=1−n−1)であ
る。
The column latch 5 is used to land input data and perform batch writing to all memory cells connected to one word line. The Vpp switch 6 is a circuit that raises the word line and bit line selected at the time of writing to a high voltage. The input X address is input to the X address buffer 7, where it undergoes level conversion (from TTL level to MOS level) and generates complementary signals (xi, xT). FIG. 5 shows input and output waveforms of the X address buffer 7. Further, an example of a specific circuit of the conventional row decoder 2 is shown in FIG. It consists of a multi-input AND gate, each input being xi or mago (i=1-n-1).

次に動作について説明する。ウェハプロセスを完了した
メモリについて正常な動作をするか否か判定するために
各種テストが梅される。テストモードを示す信号に応じ
てメモリセルに各種のテストパターンを書込み、読出し
データが該アドレスに書込んだデータと一致するか否か
見るわけであるが、書込みはワード線単位で行われるた
め、チャネル全体の書込みを行なうためには非常に長い
時間を要する。1本のワード線の書込みにほぼ/Oミリ
秒要するため256kEEPROMでは1つのテストパ
ターンの書込みにほぼ5秒必要である。
Next, the operation will be explained. Various tests are performed on the memory that has completed the wafer process to determine whether it operates normally. Various test patterns are written to memory cells in accordance with the signal indicating the test mode, and it is checked whether the read data matches the data written to the address, but since writing is performed in word line units, It takes a very long time to write the entire channel. Since it takes approximately /0 milliseconds to write one word line, approximately 5 seconds are required to write one test pattern in a 256kEEPROM.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の不揮発性半導体記’fl’t装置は上記のように
テストに非常に長い時間を要するという欠点があった。
Conventional non-volatile semiconductor memory devices have the drawback of requiring a very long time for testing, as described above.

この発明は上記のような問題点に鑑みてなされたもので
、テスト時間の短縮を図ることのできる不揮発性半導体
記憶装置を提供することを目的とする。
The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can shorten test time.

〔問題点を解決するための手段〕[Means for solving problems]

この発明にかかる不揮発性半導体記憶装置はテスト時に
、複数のワード線を同時に選択するようにしたものであ
る。
A nonvolatile semiconductor memory device according to the present invention is configured to simultaneously select a plurality of word lines during testing.

〔作用〕[Effect]

この発明においては、テスト時に複数のワード線を同時
に選択するようにしたから、ワード線の書込みに要する
時間が短縮され、テスト時間が短縮される。
In this invention, since a plurality of word lines are simultaneously selected during testing, the time required to write word lines is shortened, and the test time is shortened.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例による不揮発性半導体記憶装
置を示し、第6図は本実施例のアドレスバッファの構成
を示す。
FIG. 1 shows a nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIG. 6 shows the structure of an address buffer of this embodiment.

第1図の本実施例装置の全体構成は第3図の従来装置の
全体構成と同じであるが、本実施例ではテスト時、複数
のワード線に同時に書込みを行なうようになっている。
The overall configuration of the device of this embodiment shown in FIG. 1 is the same as that of the conventional device shown in FIG. 3, but in this embodiment, writing is performed simultaneously on a plurality of word lines during testing.

即ち、本実施例のアドレスバッファの構成を示す第6図
において、NANDはNAND回路、NORはNOR回
路、INVはインバータ、CEはチップイネーブル信号
、T1はテストモードを示す信号であり、テストモード
を示す信号TEが出力された時、即ちflが“L”の時
アドレスバッファの出力xi、xiはともに第2図に示
すようにH″となる。このように1組のアドレス信号(
xi、xi)を“H”にすれば2木のワード41w1.
wiが、また2組のアドレス信号を“H”にすれば4本
のワード線が同時に選択される。
That is, in FIG. 6 showing the configuration of the address buffer of this embodiment, NAND is a NAND circuit, NOR is a NOR circuit, INV is an inverter, CE is a chip enable signal, and T1 is a signal indicating the test mode. When the signal TE shown in FIG.
xi, xi) to "H", the word 41w1.
If wi also sets two sets of address signals to "H", four word lines are selected at the same time.

ここで、Xアドレスバッファ回路は通常は上記回路にさ
らにインバータが付加されたり、ラッチが含まれたりす
るものである。またテストモードを示す信号TEはパッ
ドから入力してもよいし、あるパッドにVcc以上の電
圧を印加することにより発生してもよい。また他の方法
により発生してもよい。
Here, the X address buffer circuit is usually one in which an inverter is further added to the above circuit, or a latch is included. Further, the signal TE indicating the test mode may be input from a pad, or may be generated by applying a voltage higher than Vcc to a certain pad. It may also be generated by other methods.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明に係る不揮発性半導体記憶装置に
よれば、テスト時には複数本のワード線を同時に選択す
るように構成したので、テスト時間を短縮できるという
効果がある。
As described above, according to the nonvolatile semiconductor memory device according to the present invention, since a plurality of word lines are selected simultaneously during testing, there is an effect that the testing time can be shortened.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による不揮発性半導体記憶装
置を示す構成図、第2図は上記実施例のアドレスバッフ
ァの出力波形図、第3図は従来の不揮発性半導体記憶装
置のブロック図、第4図はそのロウデコーダの回路図、
第5図は従来例の7ドレスバツフアの出力波形図、第6
図は上記本発明の実施例のXアドレスバッファの構成図
である。 ■はメモリアレイ、2はロウデコーダ、3はコラムデコ
ーダ、4はYゲート、5はコラムランチ、6はVlll
l)スイッチ、7はアドレスバッファである。 なお、図中同一符号は同−又は相当部分を示す。
FIG. 1 is a block diagram showing a nonvolatile semiconductor memory device according to an embodiment of the present invention, FIG. 2 is an output waveform diagram of the address buffer of the above embodiment, and FIG. 3 is a block diagram of a conventional nonvolatile semiconductor memory device. , Figure 4 is the circuit diagram of the row decoder,
Figure 5 is an output waveform diagram of a conventional 7-dress buffer;
The figure is a configuration diagram of the X address buffer according to the embodiment of the present invention. ■ is a memory array, 2 is a row decoder, 3 is a column decoder, 4 is a Y gate, 5 is a column launch, 6 is a Vllll
l) Switch 7 is an address buffer. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

【特許請求の範囲】[Claims] (1)メモリセルが行方向、列方向にアレイ配置され、
行の選択はロウデコーダにより入力アドレスに対応して
1本のワード線を選択することにより行い、列の選択は
入力アドレスに対応して1本もしくは1組のビット線を
I/O線に接続することにより行なう不揮発性半導体記
憶装置において、テストモード時に複数のワード線を同
時に選択する手段を備えたことを特徴とする不揮発性半
導体記憶装置。
(1) Memory cells are arranged in an array in the row and column directions,
Row selection is performed by selecting one word line according to the input address using a row decoder, and column selection is performed by connecting one bit line or one set of bit lines to the I/O line according to the input address. What is claimed is: 1. A nonvolatile semiconductor memory device characterized by comprising means for simultaneously selecting a plurality of word lines in a test mode.
(2)上記テストモード時に複数のワード線を同時に選
択する手段はアドレスバッファ内に設けられており、該
アドレスバッファはそのiビット目の出力xi、■iを
入力アドレスデータのあるビットの“H”/“L”にか
かわらずともに“H”とするものであることを特徴とす
る特許請求の範囲第1項記載の不揮発性半導体記憶装置
(2) Means for simultaneously selecting a plurality of word lines in the above test mode is provided in the address buffer, and the address buffer uses the i-th output xi, i of the bit of the input address data as "H". 2. The nonvolatile semiconductor memory device according to claim 1, wherein both of the signals are set to "H" regardless of "/"L".
(3)上記半導体記憶装置は、EEPROMであり、上
記ワード線の複数選択を書込み時のみ行なうことを特徴
とする特許請求の範囲第1項または第2項記載の不揮発
性半導体記憶装置。
(3) The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is an EEPROM, and the plurality of word lines are selected only during writing.
JP62310303A 1987-12-08 1987-12-08 Non-volatile semiconductor memory device Pending JPH01151100A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62310303A JPH01151100A (en) 1987-12-08 1987-12-08 Non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62310303A JPH01151100A (en) 1987-12-08 1987-12-08 Non-volatile semiconductor memory device

Publications (1)

Publication Number Publication Date
JPH01151100A true JPH01151100A (en) 1989-06-13

Family

ID=18003598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62310303A Pending JPH01151100A (en) 1987-12-08 1987-12-08 Non-volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH01151100A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03137900A (en) * 1989-07-27 1991-06-12 Nec Corp Nonvolatile semiconductor memory
JPH0419899A (en) * 1990-05-11 1992-01-23 Mitsubishi Electric Corp Test device for semiconductor memory
US5375083A (en) * 1993-02-04 1994-12-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit including a substrate having a memory cell array surrounded by a well structure
US5535160A (en) * 1993-07-05 1996-07-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
JP2000124792A (en) * 1998-10-20 2000-04-28 New Japan Radio Co Ltd Level shift circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107493A (en) * 1982-12-09 1984-06-21 Ricoh Co Ltd Eprom memory device with test circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107493A (en) * 1982-12-09 1984-06-21 Ricoh Co Ltd Eprom memory device with test circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03137900A (en) * 1989-07-27 1991-06-12 Nec Corp Nonvolatile semiconductor memory
JPH0419899A (en) * 1990-05-11 1992-01-23 Mitsubishi Electric Corp Test device for semiconductor memory
US5375083A (en) * 1993-02-04 1994-12-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit including a substrate having a memory cell array surrounded by a well structure
US5535160A (en) * 1993-07-05 1996-07-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
JP2000124792A (en) * 1998-10-20 2000-04-28 New Japan Radio Co Ltd Level shift circuit

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