JP2697164B2 - Field memory - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a field memory used as a delay line for television image data.

[Prior Art] A conventional synchronous operation type field memory is used as a delay line for a memory capacity by simultaneously writing and reading data in synchronization with a serial clock.

Hereinafter, the prior art will be described with reference to FIGS. 4, 5, and 6. FIG.

FIG. 4 is a block diagram of a conventional field memory.

Each of the memory cells 4 and 5 has a capacity capable of storing N lines of divided line data obtained by dividing one line of data. These memory cells 4 and 5 are additionally provided with write data registers 1 and 2, read data registers 10 and 11, and line selectors 7 and 8, respectively. The write data registers 1 and 2 use the clock signal C
According to the LK, the data is serially taken in from the outside, stored, and transferred to the memory cell arrays 4 and 5 collectively. The read data registers 10 and 11 receive the data for the divided lines stored in the memory cell arrays 4 and 5 by batch transfer and serially output the data to the outside according to the clock signal CLK. The line selectors 7 and 8 activate the data transfer target lines of the memory cell arrays 4 and 5 at the time of writing and reading.

Further, an address generation circuit 17 is provided as a means for supplying a write data transfer address and a read data transfer address to these line selectors 7 and 8. The address generation circuit 17 includes a write data transfer address generation counter 14 for generating an address corresponding to a data transfer target line when writing to the memory cell arrays 4 and 5, and a data transfer target counter when reading from the memory cell arrays 4 and 5. A read data transfer address generation counter 15 for generating an address corresponding to a line, and a data transfer address selection / distribution circuit 13 for selecting addresses from both counters 14 and 15 and supplying the addresses to line selectors 7 and 8
It is composed of

Note that the controller 16 has a write data register 1
2. It controls the read data registers 10 and 11, the data transfer address generation counters 14 and 15, and the data transfer address selection / distribution circuit 13.

Next, the operation of the field memory will be described with reference to FIG.

FIG. 5 is a timing chart for explaining the operation of the field memory. In FIG. 5, a serial write line is a line to be written when data is written to the field memories 4 and 5, CLK is a serial clock, and Din is a field memory. Dout is the data string of the data read from the field memories 4 and 5, DDT is the contents of the write data transfer address generation counter 14, and RDT counter is the read data transfer address generation counter. 15, WDT indicates the execution timing of the write data transfer, and RDT indicates the execution timing of the read data transfer.

FIG. 6 shows the enlarged portions of CLK, Din, and Dout. Also, K (A), K + 1 (B), etc. shown in the Din and Dout portions in FIG. 5 indicate the lines (blocks) of the memory cell arrays 4 and 5 where the data strings are to be stored. R
K (A), K + 1 (B) and the like shown in the DT part indicate data transfer target lines (blocks) of the memory cell arrays 4 and 5. Note that the blocks are (A) and (B) in which a data register, a memory cell array, and the like are divided and configured.

The write and read operations of this field memory will be described with reference to the portion of FIG. 5 where the serial write line is K and the serial read line is K + 2.

As a write operation, first, data indicated by K (A) input to the data input terminal Din is input to the write data register (A) 1 in synchronization with the serial clock CLK (hereinafter, this operation is referred to as serial write ).
When the write data register (A) 1 is full of input data, serial writing to the write data register (B) 2 is continued as indicated by K (B) of Din. At this time, the full write data register (A) 1
Are transferred to the K line of the memory cell array (A) 1 at the timing indicated by K (A) of the WDT.

Further, as the serial write is continued, the write data register (B) 2 becomes full. When it ’s full,
As shown by K + 1 (A) of Din, the serial write is transferred to the write data register (A) 1 and all the data of the write data register (B) 2 that has become full are written in KDT of WDT.
At the timing indicated by (B), batch transfer is performed to the K line of the memory cell array (B) 2.

In the read operation, the data of the read data register (A) 10 is output from the data output terminal in synchronization with the serial clock CLK. Hereinafter, this operation is called a serial read (indicated by K + 2 (A) of Dout: the data of the K + 2 line of the memory cell array (A) 4 has already been transferred to the read data register (A) 10). During the serial read of this data string K + 2 (A), K + 2 of RDT
As shown in (B), the data string K + 2 to be read next
The read data transfer of (B) is performed. That is, all the data on the K + 2 line of the memory cell array (B) 5 is transferred to the read data register (B) 11 at once.

When the serial read of the read data register (A) 10 is completed, the process proceeds to the serial read of the read data register (B) 11 as shown by K + 2 (B) of Dout. During the serial read of the data string K + 2 (B), the read data transfer of the data string K + 3 (A) to be read next is performed as indicated by K + 3 (A) of the RDT. That is, all the data of the K + 3 line of the memory cell array (A) 4 is transferred to the read data register (A) 10 at a time.
However, these read data transfers are performed after the end of the write data transfer. For example, the RDT of K + 2 (B) is K
This is performed after the WDT of -1 (B) ends.

As the data transfer address corresponding to the data transfer target line of the memory cell array when performing these data transfers, the counter value of the write data transfer address generation counter 14 is used at the time of write data transfer, and the read value is read at the time of read data transfer. The counter value of the data transfer address generation counter 15 is used. That is, at the time of write data transfer, the write data transfer address generation counter 14
During the read data transfer, the counter value of the read data transfer address generation counter 15 is transferred to the line selector 7 or 8 via the data transfer address selection / distribution circuit 13 so that only the data transfer target Activate the line. These controls are controllers
16 do.

As described above, the serial write / read and the write / read data transfer are alternately and continuously performed, thereby realizing the uninterrupted serial access.

In the operation diagram shown in FIG. 5, writing to the K line of the field memory and reading from the K + 2 line are simultaneously performed. That is, the serial read is two lines ahead of the serial write line.

As a result, when the number of lines in the field memory is N, the field memory operates as a delay line for N-2 lines. That is, there is generally an N-line field memory, and when the serial read line is ahead of the serial write line by R lines, the field memory becomes an NR line delay line.

[Problems to be Solved by the Invention] However, in the above-described conventional field memory, there are two counters for data transfer address generation, one for write data transfer and the other for read data transfer, and these counters are used as addresses for data transfer. Since the values were used as they were, there were the following problems.

That is, the serial write line and the serial read line are uniquely determined according to the operation of the counter (counter value). When this field memory is used as a delay line, the delay amount of all pixels in one line, that is, The delay amount of each pixel constituting each line of the field memory becomes the same, and each block divided in the line direction cannot have a different delay amount.

Also, one or both of the two counters may malfunction due to noise or the like that enters from outside the field memory via the power supply and the ground, and so the synchronization of the two counters is periodically performed. It is necessary to take measures such as taking.

Further, since an area for two data transfer address generation counters is required, there is a disadvantage that the area occupied by the address generation circuit increases.

On the other hand, in a high-definition television system using a communication satellite which has been recently developed, it is necessary to make the delay amount different for each field, for each line, or for each divided line. There is a problem that the field memory cannot cope with such an application.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a field memory capable of making a delay amount different for each field, for each line, or for each divided line.

Means for Solving the Problems A field memory according to the present invention includes a memory cell array for storing data, and externally fetching and accumulating data corresponding to a data read / write length for the memory cell array. A write data register for batch transfer to a cell array, a batch transfer of data corresponding to the read / write length accumulated in the memory cell array, a read data register for storing, outputting to the outside, and a batch transfer of the data A plurality of blocks each consisting of a set of line selectors for activating a data transfer target line of the memory cell array, a data transfer basic address generation counter for generating a basic address, and a basic address output from the counter. An arithmetic circuit that performs a predetermined operation for each block; A data transfer address selection / distribution circuit that selects the output of the arithmetic circuit and the basic address as an address of the data transfer target line and supplies the data transfer address selection / distribution circuit to each line selector of the plurality of blocks, and a controller that controls these circuits. It is characterized by the following.

[Operation] In the present invention, the arithmetic circuit generates a different data transfer target line address for each block based on the basic address output from the data transfer basic address generation counter. This makes it possible to set a different delay amount for each block.

Further, since various addresses are generated using only one counter that outputs a basic address as a counter, there is no problem of synchronization between counters when a plurality of counters are provided. In addition, the area occupied by the counter on the chip can be reduced.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a field memory according to a first embodiment of the present invention.

Each of the memory cell arrays 104, 105, and 106 has a capacity capable of storing N lines of data of O pixels, P pixels, and Q pixels obtained by dividing one line of data. These memory cell arrays 104, 105, 106 have write data registers 101, 102, 103, and read data registers 11 respectively.
0, 111, 112 and line selectors 107, 108, 109 are additionally provided. Here, the memory cell array 104 for O pixels,
The data registers 101 and 110 and the line selector 107 are block (A), the memory cell array 105 for P pixels, the data registers 102 and 111 and the line selector 108 are block (B), the memory cell array 106, and the data registers 103 and 112.
And the line selector 109 is a block (C).

The write data registers 101, 102, and 103 write data of O, P, and Q pixels corresponding to the divided lines to the clock signal C.
According to the LK, the data is serially captured from the outside, stored, and transferred collectively to the memory cell arrays 104, 105, and 106. The read data registers 110, 111, and 112 receive the data of the divided lines stored in the memory cell arrays 104, 105, and 106 by batch transfer, and serially output the data to the outside according to a clock signal CLK. Line selectors 107, 108, and 109 are memory cell arrays 104, 105, and 106 at the time of writing and reading.
Is activated.

Further, an address generating circuit 117 is provided as means for supplying a write data transfer address and a read data transfer address to these line selectors 107, 108, 109. The address generating circuit 117 includes a data transfer basic address generation counter 114 that generates an address corresponding to a data transfer target line as a basic address when writing to the memory cell arrays 104, 105, and 106.
An arithmetic circuit 115 for performing predetermined arithmetic processing on the basic address from the counter 114 to generate an address corresponding to a data transfer target line at the time of reading from the memory cell arrays 104, 105, and 106; Output from the counter 114 and the arithmetic circuit 115
And output from each of the line selectors 107, 108, and 109.
And a data transfer address selection / distribution circuit 113 for distributing the data.

The controller 116 controls these units.

 Next, the operation of this embodiment will be described with reference to FIG.

FIG. 2 is a timing chart for explaining the operation of the field memory. In FIG. 2, a serial write line is a line to be written when data in the field memory is written, and a serial read line is a read line when data is read from the field memory. Target line, CLK is serial clock, Din is data string of data to be written to field memory, Dout is data string of data read from field memory, DT counter is contents of counter 114 for generating basic address for data transfer, operand is read data An added value that is added to the output value of the data transfer basic address generation counter 114 to generate a data transfer address used at the time of transfer, WDT indicates the execution timing of the write data transfer, and RDT indicates the execution timing of the read data transfer. Show.

FIG. 6 shows enlarged portions of CLK, Din, and Dout. Also, K (A), K + 1 (B), etc. shown in the Din and Dout portions in FIG. 2 indicate the lines of the memory cell array in which the data string is to be stored, and the parentheses indicate the blocks. I have. Also, K (A), K + 1 (B) and the like shown in the WDT and RDT portions indicate data transfer target lines of the cell array, and the parentheses indicate blocks.

The write and read operations of this field memory will be described with reference to the case where the serial write line in FIG. 2 is K and the serial read lines are K + 2, K + 3, K + 4.

As a write operation, first, the data indicated by K (A) of Din is input to the data input terminal Din, and the write data register (A) 101 is synchronized with the serial clock CLK.
Serial write to Write data register (A)
When 101 becomes full of input data, the next data is continuously written to the write data register (B) 102 as indicated by K (B) of Din. At this time, K of WDT
At the timing indicated by (A), all data of the write data register (A) 101 which is full is transferred to the K-th line of the memory cell array (A) 104 at a time.

Further, as the serial write is continued, the write data register (B) 102 becomes full. Register (B) 102
When is full, as shown by K (C) of Din, serial write is transferred to the write data register (C) 103, and the write data register (B) becomes full.
All data 102 is transferred to the K-th line of the memory cell array (B) 105 at a timing indicated by K (B) of the WDT.

Further, as the serial write is continued, the write data register (C) 103 becomes full. Register (C) 1
When 03 becomes full, the serial write is again shifted to the write data register (A) 101 as shown by K + 1 (A) of Din, and all the data in the full write data register (C) 103 is transferred. Batch transfer to the K-th line of the memory cell array (C) 106 at the timing indicated by K (C) of the WDT.

As a read operation, the data of the read data register (A) 110 is serially read from the data output terminal in synchronization with the serial clock CLK as indicated by K + 2 (A) of Dout. At this time, the data of the K + 2 line of the memory cell array (A) 104 has already been transferred to the read data register (A) 110. During the serial read of this data string K + 2 (A), K + 2 of RDT
At the timing shown by (B), the read data of the data string K + 2 (B) of the memory cell array (B) 105 to be read next is transferred to the read data register (B) 111 at once.

When the serial read of the read data register (A) 110 is completed, the process proceeds to the serial read of the read data register (B) 111 as shown by K + 3 (B) of Dout. During the serial read of the data string K + 3 (B), the data string K + of the memory cell array (C) 106 to be read next is read at the timing indicated by K + 4 (C) of the RDT.
4 (C) is transferred collectively to the read data register (C) 112.

When the serial read of the read data register (B) 111 is completed, the process proceeds to the serial read of the read data register (C) 112 as indicated by K + 4 (C) of Dout. During the serial read of the data string K + 4 (C), the read data of the data string K + 3 (A) of the memory cell array (A) 104 to be read next is transferred to the read data register (A) 110 at a time.

However, these read data transfers are performed after the end of the write data transfer. For example, RDT of K + 3 (B)
Is performed after the WDT of K-1 (C) ends.

The memory cell array 10 for performing these data transfers
The data transfer addresses corresponding to the data transfer target lines 4, 105, 106 are the basic address generation circuit 114 for data transfer.
And output from the arithmetic circuit 115. More specifically, the counter value of the data transfer basic address generation counter 114 is used as it is at the time of write data transfer, and the data transfer basic address generation counter is used at the time of read data transfer.
The serial read line is generated by adding 4 to the counter value of 114 when the block is the (A) block, 4 when the serial read line is the (B) block, and 3 when the serial read line is the (C) block. Where the sum is
The numbers 4, 4, and 3 represent the number of preceding lines of the serial read line of each block with respect to the serial write line (A).
This is because the block is 2, the block (B) is 3, and the block (C) is 4. Also, K + 2 (A), K + 3
This is because the values of the DT counter in FIG. 2 at the timing of determining the read data transfer addresses of (B) and K + 4 (C) are K-2, K-1, and K-1, respectively.

As described above, in the case of write data transfer, the counter value of the data transfer basic address generation counter 114 is directly transferred to the line selector 107, 108 or 109 via the data transfer address selection distribution circuit 113, and the data transfer is performed. In the case of read data transfer, the counter value of the data transfer basic address generation counter 114 and the addition value output from the controller 116 are added and calculated by the calculation circuit 115, Line selectors 107, 1 via data transfer address selection distribution circuit 113
Transfer to 08 or 109 to activate the only line to be transferred. These controls are performed by the controller 116.

As described above, the serial write / read and the write / read data transfer are alternately and continuously performed, thereby realizing the uninterrupted serial access.

In the timing chart of FIG. 2, each block, that is, the (A) block has a leading O pixel, the (B) block has a succeeding P pixel, and the (C) block has a final Q pixel. 2
Line, line 3 and line 4 are ahead.

As a result, when the number of lines in the field memory is N, each block has N-2, N-3 and N, respectively.
It operates as a delay line for -4 lines.

In other words, generally speaking, in a field memory having a number N of lines obtained by dividing a data register and a memory cell array into three in the line direction, if the serial read line of each block is advanced by R, S, T lines from the serial write line, The first O pixel of the field memory has the NR line, the next P pixel has the NS line, and the last Q pixel has the NT line delay.

FIG. 3 is a block diagram of a field memory according to a second embodiment of the present invention. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description of the overlapping portions will be omitted.

The field memory of this embodiment differs from the field memory of FIG. 1 in that a refresh address counter 119 is newly provided in the address generation circuit 118.

In this embodiment, since the refresh address counter 118 is provided in the address generation circuit 118, when the memory cell arrays 104, 105, and 106 are of a dynamic type, there is no need to externally consider a refresh operation. In addition, a dynamic memory cell can realize a large-capacity memory at low cost, and thus has an advantage that it is suitable for large-capacity storage.

[Effect of the Invention] As described above, according to the present invention, an arithmetic circuit generates a different address of a data transfer target line for each block based on a basic address output from a data transfer basic address generation counter. Therefore, each block divided in the line direction can have a different delay amount.

Also, since there is only one counter, there is a problem when there are a plurality of counters, that is, power supply from outside the field memory,
The conventional problem caused by noise entering through the ground or the like can be fundamentally solved.

Further, there is an effect that the area occupied by the address generation circuit on the chip can be reduced as compared with the case where there are a plurality of counters.

[Brief description of the drawings]

FIG. 1 is a block diagram of a field memory according to a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the field memory, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a block diagram showing a conventional field memory, FIG. 5 is a timing chart for explaining the operation of the conventional field memory, and FIG. 6 is a block diagram of FIG. 2 and FIG. FIG. 4 is a timing chart showing details of CLK, Din, and Dout. 1,2,101,102,103; write data register, 4,5,104,10
5,106; memory cell array, 7, 8, 107, 108, 109; line selector, 10, 11, 110, 111, 112; read data register, 1
3,113; data transfer address selection distribution circuit, 14; write data transfer address generation counter, 15; read data transfer address generation counter, 16, 116; controller, 17, 117, 118; address generation circuit, 114; data transfer basic address generation counter, 115; arithmetic circuit, 119; refresh address counter

Claims (1)

(57) [Claims] 1. A memory cell array for storing data, a write data register for taking in data corresponding to a read / write length of data from / to the memory cell array from outside, storing the data, and collectively transferring the data to the memory cell array; The reading / accumulation stored in the cell array
A read data register for collectively transferring, receiving, accumulating, and outputting data corresponding to a write length, and a line selector for activating a data transfer target line of the memory cell array during the collective transfer of the data. And a counter for generating a basic address for data transfer for generating a basic address, an arithmetic circuit for performing a predetermined operation for each block on the basic address output from the counter, an output of the arithmetic circuit and the basic address A data transfer address selection / distribution circuit that selects the address of the data transfer target line and supplies the address to each line selector of the plurality of blocks, and a controller that controls these.