JPH06266607A - Data processing system and method for programming of its memory timing - Google Patents

Abstract

PURPOSE: To attain a programmable memory timing by using a RAM in a memory controller device in a data processing system. CONSTITUTION: The timing information of a memory operating is stored by using an MCRAM. The MCRAM stores information related with RAS, CAS, LD, and AD timing signals by each memory operation of reading, writing, and reproduction. At first, general timing information enabling access to all possible DRAM memory modules is loaded to the MCRAM. Then, a processor searches for the ID number of the DRAM in a specific memory module, and a lookup table searches for an optimal timing designated by a seller related with the DRAM corresponding to this ID number by using the number, and the optimal timing information is written in the MCRAM. Afterwards, all memory operations for this specific memory module use this optimal timing information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of computer memory, and more particularly to a memory controller timing controller used to generate timing signals for a memory module coupled to the memory controller. The present invention relates to a device and a process for effectively programming data.

[0002]

2. Description of the Related Art Computer systems typically store dynamic random access access to store data and computer programs for various tasks.
A bank of memory (DRAM) is used. For example, in a bit map computer display system, each pixel located in a cathode ray tube (CRT) display has a single bit digital value to represent that pixel in memory, or to represent color. Is assigned a multi-bit digital value of. Computers have traditionally been addressed in their memory in 8-bit, 16-bit, 32-bit, 64-bit, or more increments. Generally, one memory cycle has the ability to transfer a predetermined number of bits. In the years since the advent of digital computers, to maximize the performance of data processing systems,
Various memory structures and architectures have been developed.

The assignee of this application, Sun Mi
crosystems, Inc. Some computer systems, such as the engineering workstations manufactured by, utilize a DRAM module plugged into the workstation's main printed circuit board ("mother board") to provide dynamic RAM. Memory is provided. These DRAM
The modules allow a known amount of storage per module for a given cycle time and mode of operation. For example, in the case of a DRAM module provided by Toshiba, 72 megabits, 36 megabits, and other combinations of RAMs can be provided by a printed circuit board that is inserted into a memory expansion slot of a computer motherboard.
Storage capacity is obtained.

Patent application 07 / 554,283, filed Jul. 17, 1990, which is a continuation-in-part of this application, discloses an improved form that includes a plurality of DRAMs used in digital computer systems. A single in-line memory module is disclosed. The data processing system disclosed in this application utilizes multiple memory modules known as SIMMs. Each of these SIMMs contains a DRAM and these DRAMs
Each provide a known amount of storage for a given cycle time and mode of operation.

Generally, in a system using a plurality of memory modules, the operation timing of the memory is fixed or hard wired. If a DRAM replacement or replacement is desired, this fixed timing is
May cause problems. As a general matter, the market currently has a variety of D's with varying timing requirements.
RAM is available. The timing requirements of the DRAM of the first seller are different from the timing requirements of the DRAM of the second seller. Therefore, in a fixed timing data processing system, an individual may not always be able to replace the first seller's DRAM with the second seller's DRAM. Above all, in the SIMM system, the fixed timing is the DRAM of the first seller.
It is not easy to exchange the first group of SIMMs including the second group of SIMMs and the second group of SIMMs including the second seller DRAM.

Perhaps most importantly for fixed timing, the data processing system cannot take advantage of the DRAM timing advance. Each new generation DRAM tends to have a faster cycle time than the previous generation DRAM. Therefore, the data processing system should ideally be adaptable to each new high speed generation DRAM.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus that enables programmable memory timing in a data processing system. With proper programming, programmable memory timing provides optimal timing signals for all memory operations. Therefore, another object of the present invention is to allow a data processing system to easily accommodate and utilize DRAMs with different timing requirements.

[0008]

The present invention operates in a data processing system that includes a memory module. The data processing system of the present invention includes a processor coupled to the system bus. The memory controller is also coupled to the system bus and a memory bus leading to a group of single in-line memory modules (SIMMs). Within the memory controller, RAM is utilized for programmable memory timing in the data processing system. M
This RAM, called the CRAM, is used to store timing data for memory operations. That is, M
The CRAM stores associated timing data used to generate the RAS, CAS, LD, and AD timing signals for each read, write, and play memory operation. M when a memory cycle starts
Words in CRAM are sequentially clocked by RAS, CAS,
The LD and AD lines each receive a particular data stream from these words and generate the required timing signals. MCRAM is the first SIMM
It is possible to effectively program the timing data required for memory operations for a group, followed by the timing data required for memory operations for a second SIMM group having different timing requirements. Thus, programmable MCRAM allows adaptation to different SIMM groups with different timing requirements without requiring corresponding changes in the memory controller architecture.

In operation, the MCRAM is first loaded with general timing data that allows access to SIMM groups available to the data processing system.
Following this loading operation, the processor
I for identifying the type of DRAM used in the M group
Request a memory operation to get D bytes. The processor uses this ID byte to cross-reference the look-up table stored in memory. This look-up table contains optimal timing data for all DRAMs potentially used within the SIMM group. From the look-up table, the processor reads the optimum timing data for the DRAM corresponding to the ID byte and writes this data to MCRAM. Thereafter, all memory operations will utilize the timing signals generated from this optimal timing data stored in MCRAM.

[0010]

DETAILED DESCRIPTION OF THE INVENTION As will be described below, the present invention is utilized in a system using multiple memory modules. In particular, the present invention is applicable to the system described in co-pending patent application Ser. No. 07 / 554,283 filed Jul. 17, 1990. This patent application describes a dynamic application with specific applications used by digital computers to store and retrieve data and programs.
Improved single in-line memory module (SIM) using random access memory (DRAM)
M) is disclosed.

In the following description for purposes of explanation, many details are set forth, such as specific memory sizes, bandwidths, data paths, etc., to complete the understanding of the present invention. However, these particular details are not necessary for implementation of the SIMM system, as will be apparent to those skilled in the art. In another example, SIM
Known electrical structures and circuits are shown in block diagrams in order not to unnecessarily obscure the M system.

Referring now to FIG. 1, processor 10
Are input / output devices 14 and system bus 12
System bus 1 for communication with various system components including a memory controller 16 coupled to
Is bound to 2. As described more fully below, the processor 10 is comprised of programs and / or alphanumeric data and / or other data within a single in-line memory module (SIMM) 20, 21, 22, and 23. Memorize and retrieve the data. As illustrated, SIMMs 20-23 communicate with memory controller 16 via memory bus 24. In addition, the clock 26 is coupled to the SIMM2 via the memory bus 24.
Add a timed digital clock signal to 0-23. Figure 1
Includes four single ins coupled to the memory bus 24.
Although a line memory module is shown, SIMM systems can be used for various numbers of SIMMs coupled to memory bus 24, as will be apparent to those skilled in the art.

In operation, the processor 10 uses the SIMM 20
Data is stored in a dynamic random access memory (DRAM) arranged in each of the memory cells 23 to 23.
The data to be stored by the processor 10 is provided to the memory controller 16 via the system bus 12.
The memory controller then couples the address of the data storage location within the SIMM, along with the data to be stored, to the memory bus. Various control signals are applied by the memory controller 16 to store and retrieve data in the SIMM, as described below.
Furthermore, it should be noted that the memory controller 16 provides the row and column address strobes for the DRAMs located in the SIMM, and also the memory controller 16 relates to storing and retrieving data in the SIMM. It means that the timing signal of is also added. Therefore, since all timing signals originate from the memory controller 16, the single in-line memory module of the present invention can utilize dynamic random access memory with varying storage capabilities. .

In the presently preferred embodiment of the SIMM system, SIMMs 20-23 are utilized in a memory system with a data transfer size of 64 data bytes for each transaction. In addition, 64
Eight error check bits are provided for each bit data. Each SIMM (20-23) provides 16 bits of data and 2 bits for error checking. In the presently preferred embodiment, four SIMMs are utilized to provide 72 bits for one data transfer transaction. Currently SIMM 20-23
Used by the SIMM system located at
RAM is operating with an access speed of 100 nanoseconds, and two consecutive accesses are required to get 64 bytes of data. However, SI for each SIMM
By utilizing the crossbar switch (CBS) of the MM system, a conversion of 32 bytes to 100 nanoseconds is performed, so the data transfer rate to the controller 16 via the memory bus 24 is actually 25. 8 in nanoseconds
That means a part-time job.

Next, referring to FIG. 2, each S shown in FIG.
The IMMs (20 to 23) are CBS0 and CBS shown in FIG.
1 and 16 DRAMs coupled to four crossbar switches (CBS) including CBS3. Each SIMM (eg, SIMM 20 shown in FIG. 2) has four crossbar switches (CBS0-CBS).
3) is included and each crossbar switch is coupled to the memory bus 24 as shown. 16
Dynamic RAM (DRAM) is coupled to the address and control bus 50 and, as shown, a total of six.
Sends 4-bit data onto the data bus. further,
2 shown as DRAM 52 and DRAM 55 in FIG.
Each of the two DRAMs supplies four error check bits to two of the crossbar switches (in the case shown in FIG. 2, DRAM 52 supplies four error check bits to CBS0 and DRAM 55 to CBS2). Supply 4 error check bits to. As shown, the data provided by the 16 DRAMs is provided on the data bus 60.
, And thus are fed to each of the crossbar switches and ultimately sent out to the memory bus 24. In the presently preferred embodiment, each CBS
Although constructed from an ASIC, it should be apparent that standard cell, custom or semi-custom fabrication techniques could be utilized to fabricate the crossbar switch.

In the preferred embodiment, each SIMM (see FIG.
(See) sends 16-bit data, so SIM
The sum of the outputs of M20-23 is a total of 64 bits of data that make up one "word" in the computer system. Furthermore, each SIMM (20-23)
Provides 2 error check bits, resulting in 8 error check bits. Each SIM
Of the 16-bit data obtained by M, each cross-bar switch provides 4 bits of data (see FIG. 2), and each cross-bar switch has four data bits, as shown in FIG. Lines are provided to the memory bus 24 and three address lines
It is coupled to the bus 24. The function of each crossbar switch within the SIMM will be described in more detail below.

In operation, the processor 10 uses the SIMM 20
23 to 23 to provide addresses for reading or writing data to them. The address is coupled to the memory controller 16 via the memory system bus 12. The memory controller 16 couples the address to the memory bus 24 and decomposes the address bits for each respective crossbar switch in each SIMM, based on the bit value of the address (currently). 3 bits at a time). As will be described below, each crossbar switch amplifies the address and couples that portion of the address to the address and control bus 50 so that the address bits are 16 bits in FIG.
Will be supplied to the DRAM. The address associated with DRAM 52 or DRAM 55 for error checking is also CBS0 or CBS, as shown in FIG.
2 to a compatible DRAM. In the presently preferred embodiment, the error detection and error correction methods utilized are "single bit error correction / double error correction".
Bit error detection / single 4-bit byte error detection "(SEC-DED-S4ED). However, as is apparent to those skilled in the art, S
Various error detection and correction mechanisms can be utilized in accordance with the teachings of the IMM system. Further, although error detection and correction is performed by the memory controller 16 in the present embodiment, it is also possible to utilize the processor 10 to perform these functions in other applications.

Referring now to FIG. 3, each crossbar switch (CBS) is made up of the components shown. As shown, the 3-bit memory address (ME
The three lines that make up MADDR) are coupled from memory bus 24 to memory address register 70. Similarly, two lines of memory control (each C in FIG.
(Shown as a single line to the BS) are coupled to registers 72 and 74, respectively. An LD_L control line is also coupled to the memory bus 24 to provide a signal for initiating a memory access cycle, as shown in FIG.
The _L line is coupled to register 76. The Directed Read (Direc. RD) line provides signals that specify the operation as a read or write operation to the DRAM. The read instruction signal is sent to the memory bus 24.
To Direc. It is provided through the RD line, which is coupled to register 78 as shown.

In operation, the CBS receives over the memory bus 24 a memory address (MEMADDR) corresponding to an address in one of the SIMM DRAMs.
Address and memory control signals (CTRL1 and CTRL
0) is received by each CBS and stored in registers 70, 72 and 74, respectively. The CBS amplifies the memory address to generate the address and control bus 50.
(See FIGS. 2 and 3).

For purposes of illustration, assume that processor 10 initiates a read operation to retrieve the data stored in SIMMs 20-23. The processor 10
The address of the stored data (MEMADDR) is sent to the system bus 12, and the memory controller 16 receives this address and sends it to the memory bus 24. As mentioned above, four crossbar switches are arranged in each SIMM. Each S
Each CBS in the IMM has a register 7
It receives a 3-bit address with control signals (including row address strobe (RAS) and column address strobe (CAS) signals) stored at 0, 72, and 74. Address (MEMADDR) is for each CB
It is shifted out of the register 70 of S and sent out to the address and control bus 50.
It is bound to AM (see Figure 2). As best shown in FIG. 5, the timing of various signals applied to the CBS causes the memory controller 16 to
c. Add RD signal (high) to each CBS. Direc.
The RD signal is stored in the register 78.

As shown in FIG. 3, counter and decoder circuit 90 is coupled to both register 76 and register 78. Generally, the memory controller 16 is
irec. At the same time as applying the RD signal, the LD_L signal (low) is applied to the register 76. During a read operation, the counter and decoder 90 enables the output buffer 95 and is read from the DRAM to the data bus 60.
Each error check and correction bit (EC
C) together with buffers 100, 101, 102, and
It holds the data sent to 103. The retrieved data is further stored in the buffer 100 after a predetermined number of cycles.
-10. RA utilized by the present invention
S, CAS, LD_L, and Direc. For specific signal sequences, including RD signal sequences, refer to the timing diagram of FIG.

The counter and decoder 90 further controls the multiplexer 110 to perform subsequent steps when the data read from the DRAM is received by the buffers 100-103. When the first 4-bit data is received in the buffer 100, the buffer 10
The data of 0 is transferred through the multiplexer 110 and stored in the register A _R. At the same time, the data received by the buffers 101, 102, and 103 are stored in the registers B _R , C _R , and D _R. At substantially the same time as the reception of data in the register A _R, the register A _R
4-bit data stored in memory bus 2
Shifted out via the MEM DATA line parallel to 4. As the data bits stored in register A _R shift through output buffer 95, multiplexer 110 controlled by counter and decoder 90 sequentially selects registers B _R , C _R , and D _R The contents of these registers will also be shifted out to the memory bus 24 via the output buffer 95. In addition to the 4 bits of data that are shifted through the output buffer 95 in each CBS of the SIMM, an error check bit (ECC) is also added. Each SIMM
As is clear from the above description regarding the structure and operation of the CBS, the 16-bit data output from each CBS is
Together with one check bit (ECC), it forms a 64-bit data word.

Referring again to FIGS. 2, 3 and 4, the sequence of operations performed by the SIMM system will be described in connection with writing data to the DRAM located in each SIMM. When the processor 10 or other I / O device writes data to the SIMM memory array, the data, and
The address of the memory location in DRAM memory is coupled to memory controller 16 via bus 12.
The memory controller 16 sends out the address to write the data to the memory bus 24, which will be further coupled to the SIMMs 20-23. In addition, memory controller 16 drives control signals (RAS and CAS) onto memory bus 24, which are received by each CBS in each SIMM. As with the read operation, each CBS located in the SIMM receives a 3-bit address with two control bits CTL1 and CTL0. Each CB
S clocks the address and control bits respectively,
The signals are sent to the registers 70, 72, and 74, these signals are amplified, and D is transmitted via the address and control bus 50.
Retransmit to RAM. As best shown in FIGS. 3 and 4, the memory controller 16 includes Direc.
The RD line is held low and the LD_L pulse is sent out to start the write operation. Upon receiving the LD_L signal, counter and decoder 90 disables output buffer 95 and enables input buffer 120. The data to be stored is then applied to the memory bus 24 by the memory controller 16 and each CB is
Four bits for each S are provided to input buffer 120 sequentially (along with one ECC check bit). Each CBS (see FIG. 3) progressively stores each 4-bit data group in registers A ′ _W , B ′ _W , and C ′ _W , but on the fourth receive side.
The cycle is stored directly in the register D _W.
The last group of 4-bit data is stored in register D
_When stored in _W , the CBS is _A'W , _B'W , and _C'W.
Data stored in the register A _W , respectively
Shift to B _W and C _W. As soon as they are shifted into these registers, the data is transferred to the buffer 125,
Will occur at the output of the data and control bus 50 via 126, 127 and 128. See FIG. 4 for identification of the various signals and sequences of signals provided by the memory controller 16 to utilize the SIMM system for write operations.

Referring to FIGS. 2 and 3, the use of an ID number to identify a particular DRAM vendor in a SIMM system, as well as DRAM size and speed, is described.
It is reported as part of the 8-bit identification byte. Di
rec. When the RD signal is applied to the register 78 and counter and decoder 90 without a corresponding LD_L pulse, the counter and decoder 90 signal causes
ID logic circuit 150 is enabled and 2-bit ID
A value is bound to each CBS. The 2-bit ID value is determined by hard-wiring each of the bit lines to ground or Vcc (see Figure 2). This 2-bit ID value is coupled as data to memory bus 24 via multiplexer 110,
It is shifted via the register A _R and the output buffer 95. Since there are 4 CBS devices for each SIMM,
Since each CBS reports a 2-bit ID byte, it is clear that a total of 8 bits will be reported for each SIMM.

Referring to FIG. 6, in the presently preferred embodiment, memory controller 16 uses SIMM
Initiate the playback mode required according to the particular DRAM utilized in. The SIMM system includes a memory controller 16 each time a regeneration cycle is generated.
Circuitry is incorporated to allow the ID byte to be coupled to the memory bus data lines as described above. The use of the identification byte by the SIMM system allows different types of DRAMs to be SIM
It becomes possible to incorporate in M. In addition, all timing will be taken entirely through the memory controller 16, based on the type of DRAM being used, as reported by the ID byte, as described below. It is not necessary to provide a specific timing circuit configuration.

The timing of memory operations through the memory controller 16 based on the type of DRAM used in the SIMM will be described. Referring to FIG. 8, a block diagram of the memory controller 16 in the data processing system is shown. In general, system bus control logic 162 couples memory controller 16 to system bus 12. The commands sent to the system bus 12 and coupled by the system bus control logic 162 to the memory controller 16 are placed in a command queue 164. For example, in a write operation, data sent to the system bus 12 and coupled to the memory controller 16 via the system bus control logic 162 is placed in the data-in queue 166.

As illustrated, the command queue 164 and the data-in queue 166 are memory controller 1
6 to memory control logic circuit 168 which serves to couple 6 to memory bus 24. As mentioned above, multiple memory modules SIMM20, SIMM21, SIMM
22 and SIMM 23 are coupled to a memory bus 24. For example, in the case of a read operation, SIMM20-
Data sent to memory bus 24 from 23 is coupled to data out queue 167. The data out queue 167 is further coupled to the system bus control logic 162 from which the system bus 1
The read data is sent to 2.

The memory controller 16 utilizes programmable memory timing means to provide the timing signals necessary for memory operation. The programmable memory timing means comprises programmable storage elements. In the presently preferred embodiment, the programmable memory timing means comprises a RAM device shown in FIG. 8 as MCRAM 160. In the presently preferred embodiment, MCRAM 160 includes memory controller 16
Placed inside. As an alternative, the MCRAM 160 is
It should be noted that it may be composed of a separate chip outside the memory controller 16 or a storage element other than the RAM device.

The MCRAM 160 has SIMMs 20-23.
The timing signals for the memory module, shown in FIG. That is, as will be described later, for each memory operation such as read, write, or play, the MCRAM 160 has RAS, CAS,
It contains the LD and AD timing signals. These timing signals are generated by sequentially reading words from MCRAM 160. The reading of words is under the control of the MCRAM control counter 170 and the memory control logic 168. MCRAM
The words in 160 are read sequentially, so RAS,
The CAS, LD, and AD lines each receive a particular data stream from these words. These data streams consist of a sequence of 1's and 0's, which can be further used for RAS, C
The sequence of pulses required for the AS, LD and AD timing signals is generated.

In the presently preferred embodiment, MC
The RAM 160 has a bit width of 11 and a word length of 20. However, it is clear that the present invention allows for many alternative dimensions for MCRAM 160. In FIG. 9A, the virtual timing signal data is MCRA.
An example of the timing loaded into M160 is shown.
Referring to FIG. 9A, the first 3 bits, RDRAS, W
RRAS and RFRAS correspond to RAS pulses for read, write, and replay operations, respectively.
Second 3 bits, RDCAS, WRCAS, RFCAS
Correspond to CAS pulses for read, write, and replay operations, respectively. The third 3 bits correspond to AD pulses for read, write, and replay operations, respectively. And the last 2 bit RDL
D and WRLD correspond to LD pulses for read and write operations, respectively. Note that the playback operation does not require an LD signal.
Of course, the invention is in no way limited to this particular bit arrangement. It is possible to easily read a large number of alternative bit arrays, and these arrays serve equally well for the purposes of the invention.

Obviously, FIG. 9A shows only the 11 words required to perform these operations. The remaining words in MCRAM 160, words 11 to 19, are all zeros. Typically, the MCRAM 160 word following the last AD pulse is all zeros to prevent spurious pulses at the end of the memory operation.
Must be, and the remaining words are currently unused.

FIG. 9B shows the resulting timing signal from the virtual timing signal data of FIG. 9A. All signals are actually shown as low. As mentioned above, the RAS pulse corresponds to the row address strobe and the CAS pulse corresponds to the column address strobe. In the presently preferred embodiment, two CAS pulses, CAS0 (octal word 0) and CAS1.
A fast page mode is implemented using (octal word 1). The LD pulse determines the timing of data loading in a read or write operation.
The first AD pulse drives the memory address line RA
Switch from the S address to the first CAS0 address. The second AD pulse switches to the second CAS1 address for the second page mode access. The third AD pulse terminates the operation (3 clock cycles after the pulse). The first two AD pulses for reading and writing which allow the CAS address are C
Since it occurs two clocks before AS, one clock address setup time is allowed. The final AD occurs during the last RAS clock cycle to allow 3 cycles of RAS precharge for the fold operation.

Note that words in MCRAM 160 are assigned a particular set of addresses within the data processing system. Thus, in the preferred embodiment, this set of addresses would consist of 20 addresses corresponding to 20 words in MCRAM 160. Clearly, the inventive approach is not limited to the use of 20 words. MCRA
The number of words in M160 is read, written,
And is only minimally limited by the need to generate timing signals to complete the memory operation of playback. For the presently preferred embodiment, 2
Zero words is more than enough to get timing signals for read, write, and replay operations.

Of course, the timing related to the data processing system is MCR which is a programmable device.
Since it is taken by the AM 160, it is possible to program the timing itself. Thus, the data processing system is able to address timing requirements for different groups of SIMMs with different DRAMs without requiring architectural redesign within the memory controller. Next, regarding the timing programming of the currently preferred embodiment,
I will explain.

Referring to FIGS. 8 and 10, after startup and prior to memory operation, the system is unaware of the type of DRAM contained in SIMMs 20-23. Therefore, the system is also unaware of the optimal timing for these DRAMs. Therefore, in MCRAM160,
First, the timing data is loaded, which will probably generate the appropriate timing signals for the DRAMs that may be used in SIMMs 20-23. This general timing data can be considered a default type or a worst case timing scenario. Similarly, this general timing data has the drawback of providing a slower suboptimal timing signal for DRAMs with much faster capability.

Loading of general timing signal data is performed in a series of I / O write operations. For example, by the system bus control logic 162, the first
I / O write operation is directed to the address corresponding to the first word in MCRAM 160.
The second I / O write operation is then MCRAM 160.
Is addressed to the address corresponding to the second word in. Based on the number of words "n" required to generate the timing signal, this series of I / O write operations is
Continue until "n" is reached. Therefore, the timing signal data related to the generation of a general timing signal is sequentially written in the MCRAM 160.

Thus, the general timing data stored in MCRAM 160 allows the memory operation to begin. Processor 10 initiates an I / 0 read operation to cause SIMMs 20-2 to
3. Determine the identity of the particular DRAM used in 3. The read I / O is the system bus 12
Sent to the address of the ID register in the SIMM. The system bus control logic 162 then adds this command to the command queue 164. When this operation occurs in the command queue 164, the command is coupled to the memory control logic 168. The memory control logic circuit 168 incorporates circuitry to recognize this command as sent to a particular pseudo address, i.e., the ID register. (See Figure 2)

In the presently preferred embodiment, the play operation is then used to determine the ID number. Figure 6
As described above in connection with the present invention, in the present invention, the DRAM ID number in the SIMM is coupled to the data line of the memory bus 24 each time the memory controller 16 issues a read or recycle cycle. . Thus, as an alternative, it is clear that a read operation can be used to obtain the ID number. Furthermore, in this case,
It can be seen that using the reproduction cycle not only for reproduction of the DRAM but for obtaining the ID number represents a kind of "dummy reproduction".

By the ID number on the data line of the memory bus 24, the ID number is coupled to the data out queue 167 and the system bus control logic 1
Via 62 to the system bus 12 to be read by the processor 10. The processor 10
When this ID number is received from the system bus 12, this I
Utilizing the D number, the timing data for the DRAM corresponding to this ID number is obtained from the look-up table. When the lookup table is found in memory 180, it is accessible to processor 10 via system bus 12. The lookup table in memory 180 contains SIM
Includes optimal, vendor-specified timing data for all DRAMs available to M20-23. The memory 180 is a magnetic disk or RO
Including M, it can take any form of several external memories accessible to the processor 10. The memory 180 may be located within the memory controller 16 and may, for example, take the form of a register array.

The processor 10 reads the I from the memory 180.
Timing unique to the particular DRAM corresponding to the D number
Read the data. Processor 10 then proceeds to a series of I
In the / O write operation, the optimum timing data is written in the MCRAM 160. In this case, M
This sequence of operations is similar to the sequence of write operations described above with respect to general timing data, except that the optimal timing data is written to CRAM 160. From this point, the MCRAM 160 has S
Contains optimized timing data that is specific to the DRAM used in the IMM. Therefore, all future memory operations can utilize this optimized timing data.

The prior method is summarized in FIG. 10 as a flowchart of the programming process. Four major stages are utilized in this programming process. First, general timing data is loaded into the MCRAM. Second, SIMM
The ID number of the DRAM used within is required. Third, from the lookup table, this ID
DRAM used in SIMM by using number
Optimal timing data is required. Fourth, this optimal timing data is written to the MCRAM to generate the optimal timing signal.

Thus, it is possible to program the data processing system with the DRAM-specific timing data contained in the SIMM. In the future, instead of this SIMM, the user will have different timing,
If it is desired to utilize a new memory module group with a different DRAM, the pre-programming process allows the data processing system to easily adapt and adapt to this new memory module group. Of course, the method of the present invention utilizes a plurality of MCRAMs, each corresponding to a different SIMM, for example a first type DRAM in the first SIMM and a second type DRAM in the second SIMM. Can be modified to allow The programming process is modified to obtain a DRAM ID number for each individual SIMM. The look-up table then uses these ID numbers to write the optimal timing data to each of the corresponding MCRAMs.

The discussion of the present invention has been made with particular emphasis on certain memory system architectures, with particular reference to FIGS. 1-10, which, of course, are for illustration purposes only. Nothing should be considered as limiting the invention. Further, it is clear that the method and apparatus of the present invention are useful in applications where a data processing system accesses multiple data levels or generates multi-bit words. A person skilled in the art, without departing from the spirit and scope of the invention described above,
It is intended that many changes and modifications can be made.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an exemplary data processing system utilizing the teachings of the present invention.

FIG. 2 shows each single in-line memory module (S
FIG. 3 is a functional block diagram showing a crossbar switch (CBS) of the present invention located in an IMM).

FIG. 3 is a functional block diagram of each crossbar switch used in the present invention.

FIG. 4 is a timing diagram illustrating a sequence of various signals used by the present invention during a write operation.

FIG. 5 is a timing diagram of various signals used by the present invention during a read operation.

FIG. 6 is a timing diagram showing a sequence of operations utilized by the present invention during a playback operation.

FIG. 7 is a diagram showing the concept of bit distribution used in the present invention in order to minimize data loss in the case of malfunction of DRAM.

FIG. 8 is a functional block diagram showing the use of MCRAM in the memory controller.

FIG. 9 is a diagram showing an example of a method of loading into MCRAM and a timing diagram showing timing signals resulting from these particular contents.

FIG. 10 is a flow chart showing the steps for programming the MCRAM to generate the optimal timing signals for memory operation.

[Explanation of symbols]

 10 processor 12 system bus 14 input / output device 16 memory controller 20 single inline memory module 21 single inline memory module 22 single inline memory module 23 single inline memory module 24 memory Bus 26 Clock 50 Address and Control Bus 52 Dynamic RAM 55 Dynamic RAM 60 Data Bus 70 Register 72 Register 74 Register 76 Register 78 Register 90 Counter and Decoder Circuit 95 Output Buffer 100 Buffer 101 Buffer 102 Buffer 103 Buffer 110 Multiplexer 120 Input Buffer 125 Buffer 126 Buffer 127 Buffer 128 Buffer 160 MCRAM 162 System Bus control logic 164 command queue 166 data-in queue 167 data out queue 168 memory control logic circuit 180 memory

Front Page Continuation (71) Applicant 591174933 Xerox Corporation United States 06904-1600 Stamford Long Ridge Road, Connecticut 800 (72) Inventor Gilman Chesley United States 95060 Santa Cruz Pelton Aveniyu 1010 California (72) Inventor Jean A. Gastinel, United States 94043 California, Mountain View, Starlight Court, 47 (72) Inventor Fred Sellowskis United States, 94043 California, Mountain View, Rock Street No. 15, 1921

Claims (3)

[Claims] 1. A processor, a memory means, and a programmable memory timing coupled to said memory means and said processor for applying a timing signal to said memory means. A data processing system having a memory controller means having means. 2. A processor, a memory means for storing and retrieving data according to a timing signal, and a memory means coupled to the memory means and the processor for applying data and timing signals to the memory means. , A memory processing means comprising programmable memory timing means for applying the timing signal. 3. A processor, memory means for storing and retrieving data according to a timing signal, and programmable memory adapted to apply the timing signal to the memory means to generate the timing signal from timing data. A method for programming memory timing in a data processing system having a memory controller means with timing means, the programmable memory timing means being programmed with timing data and generating timing signals from the timing data Then
A method of programming memory timing in a data processing system comprising applying the timing signal to the memory means.