JP2694615B2 - Method for forming single crystal semiconductor thin film - Google Patents
Method for forming single crystal semiconductor thin filmInfo
- Publication number
- JP2694615B2 JP2694615B2 JP1283389A JP1283389A JP2694615B2 JP 2694615 B2 JP2694615 B2 JP 2694615B2 JP 1283389 A JP1283389 A JP 1283389A JP 1283389 A JP1283389 A JP 1283389A JP 2694615 B2 JP2694615 B2 JP 2694615B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- single crystal
- semiconductor thin
- groove
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁膜上に単結晶半導体薄膜を形成する単
結晶半導体薄膜の形成方法に関する。The present invention relates to a method for forming a single crystal semiconductor thin film for forming a single crystal semiconductor thin film on an insulating film.
一般に、単結晶半導体基板上に絶縁膜を形成し、この
絶縁膜に基板が露出した溝を形成し、絶縁膜上及び溝上
に非晶質半導体薄膜を形成し、溝に露出した基板を種と
して、熱処理によりこの薄膜を固相にて溝から順次単結
晶化する方法があり、これは再結晶化法と呼ばれ、SOI
(Silicon On Insulator)技術において有用な手法であ
り、注目されている。Generally, an insulating film is formed on a single crystal semiconductor substrate, a groove in which the substrate is exposed is formed in the insulating film, an amorphous semiconductor thin film is formed on the insulating film and the groove, and the substrate exposed in the groove is used as a seed. There is a method of sequentially monocrystallizing this thin film from the groove in the solid phase by heat treatment, which is called recrystallization method,
(Silicon On Insulator) It is a useful technique in the technology and is drawing attention.
ところで、このような固相成長による単結晶半導体薄
膜の形成の場合、Siを例にとると、非晶質Si薄膜は溝内
の基板との接触部から単結晶に相転位し、まず基板上面
に垂直方向(縦方向)に単結晶化が進み、次に基板上面
に平行方向(横方向)に単結晶化が進み、非晶質Si薄膜
が全域にわたつて単結晶化する。By the way, in the case of forming a single crystal semiconductor thin film by such solid phase growth, taking Si as an example, the amorphous Si thin film undergoes a phase transition from the contact portion with the substrate in the groove to the single crystal, and first, the upper surface of the substrate is In the vertical direction (vertical direction), single crystallization progresses, and then in the parallel direction (horizontal direction) parallel to the upper surface of the substrate, the amorphous Si thin film becomes single crystallization over the entire area.
しかし、非晶質Si薄膜が不純物を含む場合と含まない
場合とで、固相成長距離が大きく異なり、不純物を含ま
ないノンドープの場合、固相成長距離は小さいため、不
純物の高濃度領域を設け、この領域を種として固相成長
距離の拡大を図ることが従来行なわれており、その1例
として特開昭63−60517号公報(H01L21/20)に記載の方
法がある。However, the solid-phase growth distance greatly differs between the case where the amorphous Si thin film contains impurities and the case where the amorphous Si thin film does not contain impurities. It has been conventionally practiced to increase the solid-phase growth distance by using this region as a seed, and an example thereof is a method described in JP-A-63-60517 (H01L21 / 20).
これは、絶縁膜上及び溝上に形成したノンドープの非
晶質半導体薄膜に、溝に直交する方向に不純物の高濃度
領域を複数平行に設け、溝内の基板とこの高濃度領域を
種としてノンドープの非晶質半導体薄膜を単結晶化する
ものである。This is because a plurality of high-concentration regions of impurities are provided in parallel in a direction orthogonal to the groove on a non-doped amorphous semiconductor thin film formed on the insulating film and on the groove, and the substrate in the groove and this high-concentration region are used as seeds for non-doping. The amorphous semiconductor thin film is crystallized into a single crystal.
前記公報に記載の方法では、2条の高濃度領域と溝と
で囲まれたノンドープ領域において、V字状に単結晶化
が進行するため、最終的に菱形状の複雑なパターンの結
晶亜粒界が形成され、デバイスの特性上この結晶亜粒界
を避けてデバイスのチヤネルを形成する必要があること
から、有効にデバイスを形成し得る面積が限られてしま
うという問題点がある。In the method described in the above-mentioned publication, in the non-doped region surrounded by the two high-concentration regions and the groove, single crystallization proceeds in a V shape, so that finally the crystal subgrains of a rhombic complicated pattern are formed. Since a boundary is formed and it is necessary to form the channel of the device while avoiding this crystal sub-grain boundary in terms of the characteristics of the device, there is a problem that the area where the device can be effectively formed is limited.
本発明は、前記の点に留意してなされ、ノンドープの
非晶質半導体領域の固相成長距離を拡大し、デバイスを
形成し得る有効面積の拡張を図れるようにすることを目
的とする。The present invention has been made with the above points in mind, and it is an object of the present invention to extend the solid phase growth distance of a non-doped amorphous semiconductor region so that the effective area for forming a device can be expanded.
前記目的を達成するために、本発明の単結晶半導体薄
膜の形成方法では、単結晶半導体基板上に絶縁膜を形成
し、前記絶縁膜に前記基板が露出した溝を形成し、前記
絶縁膜上及び前記溝上に第1の非晶質半導体薄膜を形成
し、前記第1の非晶質半導体薄膜に不純物を高濃度にド
ープしたのち、前記第1の非晶質半導体薄膜を単結晶化
して単結晶半導体薄膜を形成し、エツチングにより前記
溝上及び前記溝に平行な帯状部を残して前記単結晶半導
体薄膜を除去し、前記絶縁膜上及び残存した前記単結晶
半導体薄膜上にノンドープの第2の非晶質半導体薄膜を
形成し、前記第2の非晶質半導体薄膜を単結晶化するこ
とを特徴としている。In order to achieve the above object, in the method for forming a single crystal semiconductor thin film of the present invention, an insulating film is formed on a single crystal semiconductor substrate, a groove in which the substrate is exposed is formed in the insulating film, and the insulating film is formed on the insulating film. And forming a first amorphous semiconductor thin film on the groove, doping the first amorphous semiconductor thin film with a high concentration of impurities, and then crystallizing the first amorphous semiconductor thin film into a single film. A crystalline semiconductor thin film is formed, and the single crystalline semiconductor thin film is removed by etching, leaving a strip-shaped portion parallel to the groove and a groove parallel to the groove. An amorphous semiconductor thin film is formed, and the second amorphous semiconductor thin film is monocrystallized.
以上のように構成されているため、平坦化した第2の
非晶質半導体薄膜を単結晶化する場合に、溝上及び帯状
部の単結晶化した不純物の高濃度領域を種にして単結晶
化が進み、固相成長距離の拡大が図れ、しかも溝と帯状
部のほぼ中間位置に,溝に平行に結晶亜粒界が形成さ
れ、結晶亜粒界が従来のように複雑なパターンになら
ず、デバイス形成の為の有効面積の拡張が図れる。With the above-described structure, when the flattened second amorphous semiconductor thin film is single-crystallized, the high-concentration regions of the single-crystallized impurities on the groove and the strip are used as seeds for single-crystallization. , The solid-phase growth distance can be increased, and a crystal sub-grain boundary is formed in parallel with the groove at an almost intermediate position between the groove and the band-like portion, and the crystal sub-grain boundary does not have a complicated pattern as in the past. The effective area for device formation can be expanded.
実施例について図面を参照して説明する。 Embodiments will be described with reference to the drawings.
まず、単結晶Si薄膜の形成工程について第1図及び第
2図を用いて説明する。なお、第1図は最終的に単結晶
Si薄膜を形成した状態の斜視図、第2図(a),(b)
はそれぞれ形成途中における斜視図である。First, the step of forming a single crystal Si thin film will be described with reference to FIGS. 1 and 2. Note that Fig. 1 shows the final single crystal.
Perspective view of a state in which a Si thin film is formed, FIG. 2 (a), (b)
[Fig. 3] is a perspective view in the middle of formation.
いま、第2図(a)に示すように、単結晶Si基板
(1)上に絶縁膜としてSiO2膜(2)を形成し、SiO2膜
(2)に基板(1)が露出した溝(3)を形成し、SiO2
膜(2)上及び溝(3)上に第1の非晶質Si薄膜(以下
第1のa−Si膜という)(4)を形成する。Now, as shown in FIG. 2 (a), a SiO 2 film (2) is formed as an insulating film on a single crystal Si substrate (1), and a groove in which the substrate (1) is exposed is formed in the SiO 2 film (2). Forming (3), SiO 2
A first amorphous Si thin film (hereinafter referred to as a first a-Si film) (4) is formed on the film (2) and the groove (3).
そして、イオン注入法により、第1のa−Si膜(4)
にリン〔P〕を3〜5×1020(cm-3)の高濃度にドープ
したのち、窒素雰囲気中において、600℃,16時間の熱処
理を施し、第1のa−Si膜(4)を単結晶化して第1の
単結晶Si薄膜(5)を形成する。Then, the first a-Si film (4) is formed by the ion implantation method.
After doping phosphorus [P] with a high concentration of 3 to 5 × 10 20 (cm -3 ), heat treatment is performed at 600 ° C. for 16 hours in a nitrogen atmosphere to form a first a-Si film (4). Is crystallized to form a first single crystal Si thin film (5).
ここで、第1のa−Si膜(4)が高濃度にドープされ
ているため、固相成長距離は熱処理時間に応じて第3図
中の実線に示すように変化し、第3図から、成長距離が
最も長くなる熱処理時間として16時間を設定し、このと
きの固相成長距離は約30μmである。なお、第3図の飽
和領域は多結晶化する領域である。Here, since the first a-Si film (4) is heavily doped, the solid phase growth distance changes according to the heat treatment time as shown by the solid line in FIG. The heat treatment time that maximizes the growth distance is set to 16 hours, and the solid-phase growth distance at this time is about 30 μm. The saturated region in FIG. 3 is a region where polycrystallization occurs.
つぎに、第2図(b)に示すように、エツチングによ
り溝(3)上及び溝(3)に平行な帯状部のSi薄膜
(5)を残してSi薄膜(5)を除去し、その後第1図に
示すように、SiO2膜(2)上及び残存したSi薄膜(5)
上にノンドープの第2の非晶質Si薄膜(以下第2のa−
Si膜という)を形成し、この第2のa−Si膜に対して窒
素雰囲気中において600℃,8時間の熱処理を施し、第2
のa−Si膜を単結晶化して第2の単結晶Si薄膜(6)を
形成し、その後このSi薄膜(6)を平坦化し、第1,第2
の単結晶Si薄膜(5),(6)をSiO2膜(2)上に形成
してSOI膜(7)を形成する。Next, as shown in FIG. 2 (b), the Si thin film (5) is removed by etching, leaving the band-shaped Si thin film (5) on the groove (3) and parallel to the groove (3). As shown in FIG. 1, Si thin film (5) on the SiO 2 film (2) and remaining
An undoped second amorphous Si thin film (hereinafter referred to as the second a-
Si film) is formed, and the second a-Si film is subjected to heat treatment at 600 ° C. for 8 hours in a nitrogen atmosphere.
The a-Si film of 1 is crystallized to form a second single crystal Si thin film (6), and then the Si thin film (6) is flattened,
The single crystal Si thin films (5) and (6) are formed on the SiO 2 film (2) to form the SOI film (7).
ところで、ノンドープの第2のa−Si膜を単結晶化す
る場合、溝(3)上及び帯状部のハイドープの単結晶Si
薄膜(5)を種にして単結晶化が進むため、固相成長距
離は熱処理時間に応じて第3図中の1点鎖線に示すよう
に変化し、最大成長距離は600℃,8時間の熱処理で約8
μmとなり、従来の4〜5μmに比べてほぼ2倍に拡大
する。By the way, when the non-doped second a-Si film is single-crystallized, the high-doped single-crystal Si on the groove (3) and on the strip portion is used.
As single crystallization progresses using the thin film (5) as a seed, the solid phase growth distance changes according to the heat treatment time as shown by the one-dot chain line in Fig. 3, and the maximum growth distance is 600 ° C for 8 hours. About 8 by heat treatment
.mu.m, which is almost twice as large as that of the conventional 4-5 .mu.m.
このとき、溝(3)上のSi薄膜(5)と帯状部のSi薄
膜(5)とに平行に、両側から第2のa−Si膜の単結晶
化が進むため、第1図中の破線に示すように、溝(3)
と帯状部とのほぼ中間位置に,溝(3)に平行な直線状
に結晶亜粒界(8)が形成され、亜粒界(8)が従来の
ように複雑なパターンにならない。At this time, single crystallization of the second a-Si film progresses from both sides in parallel with the Si thin film (5) on the groove (3) and the Si thin film (5) in the band-shaped portion, and therefore, in FIG. The groove (3), as shown by the dashed line
A crystal sub-grain boundary (8) is formed in a straight line parallel to the groove (3) at a substantially intermediate position between the sub-grain boundary and the strip portion, and the sub-grain boundary (8) does not have a complicated pattern as in the conventional case.
そして、得られたSOI膜(7)上にMOSトランジスタを
形成する場合のゲート(G),ドレイン(D),ソース
(S)の配置は、例えば第4図に示すようになり、n−
MOSトランジスタ(9)を、帯状部の第1の単結晶Si薄
膜(5)の近辺に,帯状部に直角方向を長尺方向として
形成し、p−MOSトランジスタ(10)を、溝(3)上の
第1の単結晶Si薄膜(5)の近辺に,溝に平行に形成
し、溝(3)と帯状部の中間の結晶亜粒界(8)を避け
てチヤネルを形成すればよく、このような配置によつて
SOI膜(7)のデバイス形成領域の有効利用が図れる。The layout of the gate (G), drain (D), and source (S) when forming a MOS transistor on the obtained SOI film (7) is as shown in FIG.
A MOS transistor (9) is formed in the vicinity of the first single crystal Si thin film (5) in the band-shaped portion with the direction perpendicular to the band-shaped portion as a long direction, and the p-MOS transistor (10) is formed in the groove (3). The channel may be formed in the vicinity of the first single crystal Si thin film (5) in parallel with the groove, and the channel may be formed while avoiding the crystal sub-grain boundary (8) in the middle of the groove (3) and the band portion. With such an arrangement
The device formation region of the SOI film (7) can be effectively used.
このとき、n−MOSトランジスタ(9)のソースコン
タクト領域(Cs)を帯状部のハイドープの第1の単結晶
Si薄膜(5)上に形成し、ソースコンタクト抵抗の低減
を図つている。At this time, the source contact region (Cs) of the n-MOS transistor (9) is a highly doped first single crystal of the band-shaped portion.
It is formed on the Si thin film (5) to reduce the source contact resistance.
従つて、前記実施例によると、ノンドープの第2のa
−Si膜の単結晶化する場合に、溝(3)上及び帯状部の
ハイドープの第1の単結晶Si薄膜(5)を種にしたた
め、第2のa−Si膜の固相成長距離を従来よりも大幅に
拡大することができ、結晶亜粒界が従来のように複雑な
パターンにならず、デバイス形状の為の有効面積の拡張
を図ることができる。Therefore, according to the above embodiment, the undoped second a
Since the highly doped first single crystal Si thin film (5) on the groove (3) and the band portion is used as a seed when the -Si film is single-crystallized, the solid phase growth distance of the second a-Si film is It is possible to greatly expand the size compared to the conventional one, and the crystal grain boundary does not have a complicated pattern as in the conventional one, and the effective area for the device shape can be expanded.
なお、前記実施例では、単結晶Si薄膜を形成する場合
について説明したが、これに限るものではない。In addition, in the above-described embodiment, the case of forming the single crystal Si thin film has been described, but the present invention is not limited to this.
本発明は、以上説明したように構成されているので、
以下に記載する効果を奏する。Since the present invention is configured as described above,
The following effects are obtained.
溝上及び帯状部に残存したハイドープの単結晶半導体
薄膜を種にして第2の非晶質半導体薄膜を単結晶化する
ため、ノンドープの第2の非晶質半導体薄膜の固相成長
距離を従来よりも大幅に拡大することができ、しかも結
晶亜粒界が溝と帯状部とのほぼ中間位置に溝に平行な直
線状に形成されることになり、結晶亜粒界が従来のよう
に複雑なパターンにならず、デバイス形成の為の有効面
積の拡張を図ることができ、デバイス用有効面積の大き
なSOI膜を得る上で非常に有利である。Since the second amorphous semiconductor thin film is single-crystallized by using the high-doped single crystal semiconductor thin film remaining on the groove and the strip portion as a seed, the solid-phase growth distance of the non-doped second amorphous semiconductor thin film is set to Can be greatly expanded, and the crystal sub-grain boundary is formed in a straight line parallel to the groove at an almost intermediate position between the groove and the band-shaped portion. It is possible to expand an effective area for forming a device without forming a pattern, which is very advantageous in obtaining an SOI film having a large effective area for a device.
図面は、本発明の単結晶半導体薄膜の形成方法の1実施
例を示し、第1図は単結晶半導体薄膜を形成した状態の
斜視図、第2図(a),(b)はそれぞれ形成途中にお
ける斜視図、第3図は熱処理時間と固相成長距離との関
係図、第4図はデバイスの配置パターンを示す平面図で
ある。 (1)……単結晶Si基板、(2)……SiO2膜、(3)…
…溝、(5),(6)……第1,第2の単結晶Si薄膜。The drawings show one embodiment of the method for forming a single crystal semiconductor thin film of the present invention. FIG. 1 is a perspective view of a state in which a single crystal semiconductor thin film is formed, and FIGS. 2 (a) and 2 (b) are in the process of being formed. 3 is a perspective view of FIG. 3, FIG. 3 is a relationship diagram between a heat treatment time and a solid phase growth distance, and FIG. 4 is a plan view showing a device arrangement pattern. (1) ... Single-crystal Si substrate, (2) ... SiO 2 film, (3) ...
… Grooves, (5), (6) …… First and second single crystal Si thin films.
Claims (1)
記絶縁膜に前記基板が露出した溝を形成し、前記絶縁膜
上及び前記溝上に第1の非晶質半導体薄膜を形成し、前
記第1の非晶質半導体薄膜に不純物を高濃度にドープし
たのち、前記第1の非晶質半導体薄膜を単結晶化して単
結晶半導体薄膜を形成し、エツチングにより前記溝上及
び前記溝に平行な帯状部を残して前記単結晶半導体薄膜
を除去し、前記絶縁膜上及び残存した前記単結晶半導体
薄膜上にノンドープの第2の非晶質半導体薄膜を形成
し、前記第2の非晶質半導体薄膜を単結晶化することを
特徴とする単結晶半導体薄膜の形成方法。1. An insulating film is formed on a single crystal semiconductor substrate, a groove in which the substrate is exposed is formed in the insulating film, and a first amorphous semiconductor thin film is formed on the insulating film and the groove. After doping the first amorphous semiconductor thin film with a high concentration of impurities, the first amorphous semiconductor thin film is monocrystallized to form a single crystal semiconductor thin film, and the single crystal semiconductor thin film is formed on the groove and the groove by etching. The single crystal semiconductor thin film is removed leaving parallel strips, a non-doped second amorphous semiconductor thin film is formed on the insulating film and the remaining single crystal semiconductor thin film, and the second amorphous is formed. A method for forming a single crystal semiconductor thin film, which comprises crystallizing a thin semiconductor film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1283389A JP2694615B2 (en) | 1989-01-20 | 1989-01-20 | Method for forming single crystal semiconductor thin film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1283389A JP2694615B2 (en) | 1989-01-20 | 1989-01-20 | Method for forming single crystal semiconductor thin film |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02192719A JPH02192719A (en) | 1990-07-30 |
JP2694615B2 true JP2694615B2 (en) | 1997-12-24 |
Family
ID=11816376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1283389A Expired - Fee Related JP2694615B2 (en) | 1989-01-20 | 1989-01-20 | Method for forming single crystal semiconductor thin film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2694615B2 (en) |
-
1989
- 1989-01-20 JP JP1283389A patent/JP2694615B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH02192719A (en) | 1990-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH02140915A (en) | Manufacturing method of semiconductor device | |
JP4203141B2 (en) | Method for crystallizing amorphous silicon layer and method for producing thin film transistor using the same | |
JPH08102543A (en) | Crystallization method and thin film transistor manufacturing method using the same | |
JPH1168109A (en) | Production of polycrystalline thin film and production of thin-film transistor | |
JPS6158879A (en) | Preparation of silicon thin film crystal | |
JP2694615B2 (en) | Method for forming single crystal semiconductor thin film | |
US6346462B1 (en) | Method of fabricating a thin film transistor | |
JPH0252419A (en) | Manufacture of semiconductor substrate | |
JP2638868B2 (en) | Method for manufacturing semiconductor device | |
JPH03104210A (en) | Manufacture of semiconductor device | |
JP2687393B2 (en) | Method for manufacturing semiconductor device | |
JP2002368013A (en) | CMOS thin film transistor and method of manufacturing the same | |
JPS62202559A (en) | Semiconductor device and its manufacture | |
JP2505764B2 (en) | Method for forming single crystal semiconductor thin film | |
JP3141909B2 (en) | Semiconductor device manufacturing method | |
JPH05190449A (en) | Manufacture of semiconductor film | |
JP3468781B2 (en) | Method for manufacturing thin film transistor | |
JP2503626B2 (en) | Method of manufacturing MOS field effect transistor | |
JPS59184517A (en) | Manufacture of lamination-type semiconductor device | |
JP2807296B2 (en) | Manufacturing method of semiconductor single crystal layer | |
JPS60164316A (en) | Formation of semiconductor thin film | |
JPS61116821A (en) | Formation of single crystal thin film | |
JP2867402B2 (en) | Method for manufacturing semiconductor device | |
JPH0799258A (en) | Manufacture of semiconductor device | |
JPS60235445A (en) | Manufacture of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313115 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |