JP2679718B2 - Memory circuit using floating gate field effect transistor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit using a floating gate type field effect transistor used in a battery-operated small computer, a memory card or the like.

2. Description of the Related Art In recent years, a memory using a floating gate field effect transistor (abbreviated as FG type FET hereinafter) has been used as a substitute for a floppy disk of a battery-operated small computer and for a memory card with a long data retention period.
Great demand is expected. Among them, the non-volatile RAM that can operate as a random access memory (hereinafter referred to as RAM) when the power is turned on is suitable as a memory for a microcomputer because of its high-speed write operation, and active development is underway.

An example of a conventional RAM using the above conventional FG type FET
Description will be made based on the circuit diagram of the figure.

The drain of the memory transistor 1 formed of an FG type FET that stores data in a nonvolatile manner is the first control input terminal 7
, The gate is connected to the first electrode of the capacitor 4 used for dynamic RAM operation, and the source is RA
It is connected to the drain of the pass transistor 2 which separates the M operation and the non-volatile operation. The gate of the pass transistor 2 is connected to the third control input terminal 9, and the source is connected to the first electrode of the capacitor 4 and the drain of the word selecting transistor 3. The gate of the word selecting transistor 3 is connected to the word line terminal 5, the source is connected to the bit line terminal 6, and the capacitor 4
The second electrode of is connected to the second control input terminal 8.

The FG type FET forming the memory transistor 1
Allows a charge to be exchanged by a tunnel current between the floating gate and the capacitor 4.

 The operation of the RAM configured as above will be described.

In this RAM, the pass transistor 2 is off when the power is turned on, and the word selecting transistor 3 and the capacitor 4 operate as a normal dynamic RAM.

However, immediately before the power is turned off, the data non-volatile operation, that is, the store operation is performed as follows.

First, with the pass transistor 2 turned off, a high voltage is applied to the first control input terminal 7 and at the same time the second control input terminal 8 is grounded, and then the first control input terminal 7 is grounded. At the same time, a high voltage is applied to the second control input terminal 8.
Then, when there is no charge stored in the capacitor 4, that is, in the case of data “0”, electrons are injected from the first control input terminal 7 to the floating gate of the memory transistor 1,
The threshold voltage of memory transistor 1 increases. On the other hand, when the capacitor 4 has an electric charge as shown in FIG. 4, that is, in the case of data “1”, the electrons of the floating gate of the memory transistor 1 are extracted to the first control input terminal 7 and the The threshold voltage drops. In this way, the memory data is converted into high and low threshold voltages, and the data is stored in a nonvolatile manner.

Then, when the power is turned on again, the recall operation is performed.

First, the pass transistor 2 is turned on, the first control input terminal 7 is set to a high voltage, and at the same time, the second control input terminal 8 is grounded. Then, when the threshold voltage of the memory transistor 1 is low, the capacitor 4 is charged in the state where the polarities of the charges shown in FIG. 4 are opposite and becomes a high voltage, that is, the data “0” is written, and the memory transistor 1 When the threshold voltage of 1 is high, the capacitor 4 is not charged, that is, the charge state of the capacitor 4 shown in FIG. 4 is set, and the data becomes "1". By this recall operation, the memory state immediately before the power is turned off is reproduced, and the operation as the nonvolatile memory is realized.

However, in the configuration of the memory using the FG type FET described above, three transistors of the memory transistor 1, the word selection transistor 3 and the pass transistor 2 are required, and one transistor is used. Compared to the dynamic RAM and EPROM that can be configured, the cell size is more than double,
There was a problem that large integration was extremely difficult.

The present invention solves the above problem, and an object of the present invention is to provide a memory circuit using a floating gate type field effect transistor which can be easily integrated into a large size and which can be composed of two transistors. .

Means for Solving the Problems In order to solve the above problems, a memory circuit using a floating gate field effect transistor of the present invention has a drain-source connection in which a gate is connected to a word line and a drain is connected to a bit line. A first gate electrode of a floating gate type having a thickness of a gate insulating film located under the floating gate formed on the drain gate and capable of tunneling electrons on both the drain and source regions, and a first electrode. A capacitor connected to the source of the first field effect transistor, having a second electrode connected to the control input line, a gate connected to the reset line, a drain connected to the first electrode of the capacitor, and a source Consists of a second field effect transistor connected to the second electrode of the capacitor. is there.

Operation The following operation is performed by the configuration of the memory circuit.

First, when the power is turned on, the memory transistor, which is the first field effect transistor, acts as a word selection transistor to perform a normal dynamic RAM operation. Immediately before power-off, charge is exchanged between the capacitor and the floating gate of the memory transistor by a tunnel current, and the threshold voltage of the memory transistor is changed to make data non-volatile. Immediately after the power is turned on, the capacitor is charged through the memory transistor to reproduce the data before the power is turned off. In addition, a tunnel current is passed between the floating gate and drain of the memory transistor to extract electrons from the floating gate, lowering the threshold voltage of the memory transistor and making it function as a word selection gate. Is realized.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a memory circuit using a floating gate field effect transistor (hereinafter abbreviated as FG type FET) in one embodiment of the present invention.

The word line terminal 25 is connected to the gate of the memory transistor 21 using the FG type FET, the bit line terminal 26 is connected to the drain, and the source is the drain of the reset transistor 22 and the first of the capacitors 24 which are field effect transistors. , The reset transistor 22 gate is connected to the reset terminal 23, and the source is a capacitor.
The second electrode of 24 and the control input terminal 27 are commonly connected.

The operation of the memory circuit configured as described above will be described with reference to the operation explanatory diagram of FIG. This memory circuit turns off the reset transistor 22 when the power is turned on, and operates as a normal dynamic RAM.

Immediately before the power is turned off, data is stored in the dynamic RAM in a non-volatile manner, and therefore a store operation is performed as shown in FIG.

The bit line terminal 26 is opened, and positive voltage pulses are applied to the word line terminal 25 and the control input terminal 27 with a phase shift. Then, as shown in FIG. 2 (a), when the capacitor 24 is in a charged state, when a pulse is applied to the control input terminal 27, electrons in the floating gate 11 are extracted, so that the memory transistor 21 The threshold voltage becomes low. On the other hand, when the capacitor 24 is discharged, electrons are injected into the floating gate 11 when a pulse is applied to the word line terminal 25, and the memory transistor
The threshold voltage of 11 becomes high. Therefore, the memory data stored in the capacitor 24 is converted as a difference in threshold voltage of the memory transistor 21, and the data can be stored in a nonvolatile manner.

Immediately after the power is turned on, the capacitor 24 is restored to the state before the power is turned off by the recall operation as shown in FIG. 2 (b).

First, the reset transistor 22 is turned on, the capacitor 24 is discharged, the control input terminal 27 is grounded, and a positive voltage is applied to the bit line terminal 26. Then, when the threshold voltage of the memory transistor 21 is low, the voltage of the bit line terminal 26 is applied to the capacitor 24 and charged. When the threshold voltage of the memory transistor 21 is high, the capacitor 24 is not charged and remains discharged. By performing the recall operation in this way, the capacitor
24 can be restored to the state before the power was turned off.

Next, the threshold voltage of the memory transistor 21 is lowered so that the dynamic RAM operation can be performed.

As shown in FIG. 2 (c), a positive voltage is applied to the bit line terminal 26 and a negative voltage is applied to the word line terminal 25, the electrons of the floating gate 11 are extracted toward the bit line terminal 26, and the memory transistor 21 Lower the threshold voltage so that it can operate as a transfer gate. Since the memory transistor 21 has the tunnel oxide film 16 on both the source 13 and the drain 14, the source 13 of the memory transistor 21 is
The threshold voltage can be reduced for the transfer gate without damaging the data in the capacitor 24 connected to.

Figure 3 shows the FG used as the memory transistor 21.
It is a sectional view of a type FET.

In this FG type FET, a source (region) 13 and a drain (region) 14 which are separated from each other are formed in a surface region of a silicon substrate 17, and thereafter an oxide film 15, a floating gate 11 between the source 13 and the drain 14 is formed on the surface, A gate (electrode) 12 located above the oxide film 15 and the floating gate 11 is formed in order. Also drain 14 and source 13
The thickness of a gate insulating film (hereinafter referred to as a tunnel oxide film) 16 made of an oxide film located under the floating gate 11 on both regions is set to a thickness capable of tunneling electrons of about 50Å.

With the above FG-type FET configuration, a tunnel current flows between both the source 13 and the floating gate 11 and between the drain 14 and the floating gate 11, so that charge is transferred between the source 13 and the floating gate 11 and between the drain 14 and the floating gate 11. Can interact.

As described above, according to this embodiment, the memory transistor
By providing the tunnel insulating film 16 on both the source 13 and the drain 14 of 21, it becomes possible to use one memory transistor 21 for both data nonvolatility and dynamic RAM transfer gate. What you needed a dedicated transistor can be done with one transistor. As a result, the cell area can be reduced by about 30% or more as compared with the conventional one, and a large-scale semiconductor nonvolatile memory can be realized.

As described above, according to the memory circuit using the floating gate field effect transistor of the present invention, the threshold voltage of the memory transistor is changed according to the charge amount of the capacitor by the tunnel current of the source, and the data is stored. In addition to making it non-volatile, the tunnel current in the drain part pulls out electrons from the floating gate, lowers the threshold voltage of the memory transistor, and makes it operate as a word selection gate. The number of required transistors can be reduced by one.
Therefore, the cell area of the memory circuit can be reduced, and a memory using a large-scale floating gate field effect transistor can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory circuit using a floating gate type field effect transistor in one embodiment of the present invention, FIG. 2 is an operation explanatory diagram of the memory circuit of FIG. 1, and FIG. 3 is a memory of FIG. FIG. 4 is a sectional view showing the structure of a floating gate field effect transistor of the circuit, and FIG. 4 is a circuit diagram of a conventional memory circuit. 11 …… floating gate, 12 …… gate, 13 …… source, 14 …… drain, 15 …… oxide film, 16 …… tunnel oxide film (gate insulating film), 17 …… silicon substrate, 21 ……
A memory transistor (first field effect transistor),
22 ... Reset transistor (second field effect transistor), 23 ... Reset terminal, 24 ... Capacitor, 25
...... Word line terminal, 26 …… bit line terminal, 27 …… control input terminal.

Claims (1)

(57) [Claims] 1. The thickness of a gate insulating film located under a floating gate formed between a drain and a source, the gate of which is connected to a word line and the drain of which is connected to a bit line, on both the drain and source regions. A floating gate type first field effect transistor having a thickness capable of tunneling electrons, a first electrode connected to a source of the first field effect transistor, and a second electrode connected to a control input line. And a second field-effect transistor having a gate connected to the reset line, a drain connected to the first electrode of the capacitor, and a source connected to the second electrode of the capacitor. A memory circuit that uses field effect transistors.