JP2672438B2 - Chopper type comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chopper type comparator having a CMOS transmission gate.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a configuration of a conventional chopper type comparator having a CMOS transmission gate. In the figure, the first input terminal 40 to which the analog voltage VIN to be compared is applied is the first CMOS.
Via the transmission gate 45, the reference voltage Vre
The second input terminal 41 to which f is applied is connected to the input point 42 of the coupling capacitor 47 via the second CMOS transmission gate 46.
The output point of the coupling capacitor 47 is connected to the input terminal 43 of the inverter 48, and the output terminal 44 of the inverter 48 is fed back to the input terminal 43 of the inverter 48 via the third CMOS transmission gate 49.

The first CMOS transmission gate 45 is a P-type MOS transistor (P in the following description, P
The type MOS transistor is referred to as PchTr. ) 50
And N-type MOS transistor (in the following description, N-type MO transistor
The S transistor is referred to as NchTr. ) 51, each source and drain are commonly connected, and an inverted clock signal ~ φ is applied to the gate of the PchTr 50.
However, the inverted clock signal is applied to the gate of NchTr51.
A non-inverted clock signal φ that does not overlap φ is provided. As a result, when the PchTr 50 becomes conductive, the NchTr 51 also becomes conductive, and the conductive state of the first CMOS transmission gate 45 is realized. Conversely, when the PchTr 50 becomes non-conductive, the NchTr 51 also becomes non-conductive, and the non-conductive state of the first CMOS transmission gate 45 is realized.

On / off of the second CMOS transmission gate 46 is also controlled by the non-inverted and inverted clock signals φ, ˜φ. However, when the first CMOS transmission gate 45 becomes conductive, the second CMOS transmission gate 46 becomes non-conductive, and when the first CMOS transmission gate 45 becomes non-conductive, the second CMOS transmission gate 46. So that it becomes conductive,
Both clock signals φ, φ are provided to the second CMOS transmission gate 46.

The third CMOS transmission gate 49 is connected to the first CMOS transmission gate 45.
To turn on / off at the same timing, that is, when the first CMOS transmission gate 45 becomes conductive, it also becomes conductive, and the first C
Non-inverted and inverted clock signals φ, ˜φ are applied so that when MOS transmission gate 45 is turned off, it is also turned off.

Coupling capacitor 47, inverter 48 and third CMOS transmission gate 49
Constitutes one AC amplifier. Reference numeral 55 is an output point of the AC amplifier, that is, an output point of the chopper type comparator.

FIG. 6 is a timing diagram of clock signals of the conventional chopper type comparator described above. The operation of the chopper type comparator will be described with reference to FIGS. However, in the first CMOS transmission gate 45, the floating capacitance 52 between the gate and drain of the PchTr50 is set to CSP1, and the gate capacitance of the NchTr51 is
The stray capacitance 53 between the drains is CSN1. The capacitance of the coupling capacitor 47 is Cc, and the parasitic capacitance 54 attached to it is Csub.

First, when the non-inverted clock signal φ becomes a logical value "H" (the inverted clock signal ~ φ is a logical value "L"), both the first and third CMOS transmission gates 45 and 49 are conductive. State, the second CMOS transmission gate 46 becomes non-conductive. FIG.
This period is called a "bias period" as shown in FIG.
In this "bias period", the coupling capacitor 4
7 input points (referred to as the first node in the following description) 4
An analog input voltage VIN is applied to 2 from the first input terminal 40 via the first CMOS transmission gate 45. An output terminal 44 and an input terminal 43 of the inverter 48 are short-circuited via a third CMOS transmission gate 49, and the input terminal (hereinafter referred to as a second node) 43 is an inverter 48. Is biased to the switching voltage VB. Therefore,
Coupling capacitor 47 in "bias period"
Is applied to the voltage difference (VIN-VB), and the electric charge corresponding to the voltage difference is stored in the coupling capacitor 47.

Next, when the non-inverted clock signal φ becomes the logical value "L" (the inverted clock signal ~ φ is the logical value "H"), the first and third CMOS transmission gates 45 and 49 will be either. Also non-conducting, second CMO
The S transmission gate 46 becomes conductive. As shown in FIG. 6, this period is called a “comparison period”. In this “comparison period”, the reference voltage Vref is newly applied to the first node 42 from the second input terminal 41 via the second CMOS transmission gate 46. On the other hand, since the third CMOS transmission gate 49 becomes non-conductive, the charge of the second node 43 is stored. Therefore, the voltage change ΔV43 of the second node 43
a represents the voltage change of the first node 42 by ΔV42 (= Vref
−VIN), ΔV43a = Cc · ΔV42 / (Cc + Csub) (1)

The biased inverter 48 amplifies the voltage change ΔV43a of the second node 43 and compares the magnitude relationship of the analog input voltage VIN with the reference voltage Vref as a logical value "H" or a logical value "L". Output point 55
Output from

[0011]

Although the above description does not take into consideration the feedthrough of the clock signal,
When the feed-through of the clock signal of the first CMOS transmission gate 45 connected to the first input terminal 40 is taken into consideration, the problem of malfunction occurs as described below.

When the transition from the "bias period" to the "comparison period" takes place, the voltage change of the non-inverted clock signal φ that switches from the logical value "H" to the logical value "L" is -ΔVφ, and vice versa. The voltage change of the inverted clock signal ~ φ that switches from L "to the logical value" H "is + ΔVφ. However, ΔVφ
> 0.

The amount of charge ΔQφ injected into the first node 42 by switching between these clock signals φ, ∼φ.
42 is given by ΔQφ42 = − (CSP1−CSN1) · ΔVφ (2). Therefore, the voltage change .DELTA.V43b of the second node 43 due to this injected charge is .DELTA.V43b = .DELTA.Q.phi.42 / (Cc + Csub) =-(CSP1-CSN1) .multidot..DELTA.V.phi ./ (Cc + Csub) (3). Therefore, the total voltage change ΔV43 of the second node 43 when the feedthrough of the clock signal is taken into consideration.
From the expressions (1) and (3), ΔV43 = ΔV43a + ΔV43b = {Cc · ΔV42− (CSP1−CSN1) · ΔVφ} / (Cc + Csub) (4)

In this equation (4), if | CcΔV42│> │ (CSP1 -CSN1) ΔVφ│ (5), the effect of the clock signal feedthrough can be ignored. However, if not so, the following problems occur. That is, (A) CSP1-CSN1>
When it is 0, ΔV42> 0 and Cc · ΔV42 <(CSP1-
When CSN1) · ΔVφ holds, ΔV43 <0,
(B) When CSP1−CSN1 <0, when ΔV42 <0 and | Cc · ΔV42 | <| (CSP1−CSN1) · ΔVφ |, then ΔV43> 0.

That is, the voltage change ΔV of the first node 42
The voltage change Δ of the second node 43 caused by 42
A voltage change ΔV43b of the second node 43 caused by the switching of the clock signal as compared with the absolute value of V43a.
When the absolute value of is large, the voltage change ΔV43 of the second node 43 becomes negative or the voltage change of the first node 42 is negative although the voltage change ΔV42 of the first node 42 is positive. The second node 4 despite the change ΔV42 being negative
The voltage change ΔV43 of 3 may become positive, and an incorrect comparison result will be output from the comparator output point 55.

An object of the present invention is, in a chopper type comparator having a CMOS transmission gate, to eliminate the influence of the feedthrough of the clock signal and to make the output of the comparator accurate.

[0017]

In order to achieve the above object, the present invention corrects the imbalance of the gate-drain stray capacitance between the PchTr and the NchTr forming the input side CMOS transmission gate. In addition, a configuration in which NchTr is added to the CMOS transmission gate is adopted. As another solution, a PchT with uniform gate-drain stray capacitance
A CMOS transmission gate provided with r and NchTr is additionally connected in parallel to the CMOS transmission gate on the input side, and the former is switched to the non-conducting state later than the latter.

More specifically, the invention of claim 1 is
As shown in FIG. 1, first and second switch means 18 and 19 each of which is on / off controlled so that when one becomes conductive, the other becomes non-conductive, and an analog voltage to be compared. Is applied to the first input terminal 1
Of the coupling capacitor 8 whose one end is connected to the second input terminal 2 to which the reference voltage is applied and whose one end is connected to the second input terminal 4 via the second switch means 19. When an inverter 9 connected to the other end of the coupling capacitor 8 is interposed between an output end 5 of the inverter 9 and an input end 4 of the inverter 9 and the first switch means 18 is in a conductive state, the same applies. A chopper type comparator including a third switch means 10 which is on / off controlled so as to be in the non-conductive state when the first switch means 18 is in the conductive state and the first switch means 18 is also in the non-conductive state. The first switch means 18 on the side of the input terminal 1 of is connected to each source and drain in common, and when one is conductive, the other is conductive and one is non-conductive. When a state the other also the voltage applied to the gate of each to be non-conductive is controlled, CMO with PchTr11 and NchTr12
The S transmission gate 6 has the following compensation N
This is a configuration in which chTr13 is added.

That is, the compensating NchTr 13 has the gate of the NchT of the CMOS transmission gate 6.
The source is connected to the gate of r12 and the source is PchTr11 and NchT of the CMOS transmission gate 6.
It is connected to the commonly connected drains of r12. Moreover, the PchTr11 and NchTr12 of the CMOS transmission gate 6 and the compensation Nch
Tr13 is the CMOS transmission gate 6
Stray capacitance CSP between the gate and drain of PchTr11
1 and Nch of the CMOS transmission gate 6
Stray capacitance CSN1 between the gate and drain of Tr12 and stray capacitance C between the gate and source of the compensation NchTr13
Each has a geometric dimension such that the relationship with SN2 satisfies CSP1 = CSN1 + CSN2.

Further, according to a second aspect of the invention, as shown in FIG. 2, the first switch means 1 on the side of the first input terminal 1 is provided.
Similarly to 8, the second switch means 19 on the side of the second input terminal 2 also has a source and a drain connected in common, and when one is conductive, the other is conductive and one is non-conductive. At times, the voltage applied to each gate is controlled so that the other also becomes non-conductive.
Another CMOS transmission gate 7 having r22 and NchTr23, a gate connected to the gate of the NchTr23 of the other CMOS transmission gate 7, and a source commonly connected to each of the PchTr22 and NchTr23 of the other CMOS transmission gate 7. Another compensation Nch connected to the drain
A configuration having a Tr24 is adopted, and the other CMO
S transmission gate 7 PchTr22 and N
The chTr23 and the other NchTr24 for compensation are the PchTr2 of the other CMOS transmission gate 7.
2 gate-drain stray capacitance CSP2 and other C
The geometrical dimensions are set such that the relationship between the gate-drain stray capacitance CSN3 of the NchTr23 of the MOS transmission gate 7 and the gate-source stray capacitance CSN4 of the other compensation NchTr24 satisfies CSP2 = CSN3 + CSN4. I have.

According to the third aspect of the present invention, as shown in FIG. 3, each of the first and second switch means 18 is ON / OFF controlled so that when one is in a conducting state, the other is in a non-conducting state. , 19 and a second input terminal 2 to which a reference voltage is applied and one end of which is connected to the first input terminal 1 to which an analog voltage to be compared is applied via the first switch means 18. Of the coupling capacitor 8, the input end 4 of which is connected to the other end of the coupling capacitor 8, the output end 5 of the inverter 9, and the inverter 9 Is connected to the input terminal 4 of the first switch means 18 and becomes conductive when the first switch means 18 becomes conductive, and becomes non-conductive when the first switch means 18 becomes non-conductive. In the chopper type comparator including the third switch means 10 which is on / off controlled, the fourth switch means 20 is additionally connected in parallel to the first switch means 18 on the side of the first input terminal 1. This is the configuration adopted. However, as can be seen from FIGS. 3 and 4, the fourth switch means 20 is also in the conductive state when the first switch means 18 is in the conductive state,
Further, the first switch means 18 is on / off controlled so as to be in the non-conductive state after being in the non-conductive state. The first and fourth switch means 18 and 20 are CMs, respectively.
Equipped with OS transmission gates 6 and 28, each CM
The OS transmission gates 6 and 28 have their sources and drains connected in common, and when one is in a conducting state, the other is in a conducting state, and when one is in a non-conducting state, the other is also in a non-conducting state. It has PchTr11,29 and NchTr12,30 in which the voltage applied to the gate of is controlled. Moreover, the CMOS transmission gate 28 of the fourth switch means 20
The PchTr29 and NchTr30 in the
The stray capacitance CSP3 between the gate and drain of r29 and the N
The chTr30 has geometrical dimensions such that the relationship between the gate-drain stray capacitance CSN5 satisfies CSP3 = CSN5.

[0022]

Operation: Generally in a MOS transistor, the gate length L
When the ratio W / L of the gate width W to the gate width is referred to as “gate size ratio”, the geometrical size of each of the PchTr and NchTr forming the CMOS transmission gate is P
It is customary that the gate size ratio (W / L) _{P of the} chTr is determined to be larger than the gate size ratio (W / L) _{N of the} NchTr. Therefore, the gate of the PchTr
The floating capacitance between the drains is larger than the floating capacitance between the gate and drain of the NchTr, and the fact is that there is an imbalance between the floating capacitances.

However, according to the invention of claim 1, the first
C in the first switch means 18 on the side of the input terminal 1 of
By adding a compensation NchTr 13 having a gate-source stray capacitance CSN2 to the MOS transmission gate 6, the CMOS transmission gate 6
Stray capacitance CSP between the gate and drain of PchTr11
1 and NchT of the CMOS transmission gate 6
The imbalance between the gate-drain stray capacitance CSN1 of r12 is corrected. Therefore, the Pch
The charges injected into the coupling capacitor 8 due to the switching of the voltage applied to the gates of the Tr11 and the NchTr12 can be canceled, and a correct comparison result can always be obtained.

According to the second aspect of the present invention, the other CMOS transmission gate 7 constituting the second switch means 19 on the second input terminal 2 side also has a gate-source stray capacitance CSN4. NchTr24 for compensation
Is added, the unbalance between the gate-drain stray capacitance CSP2 of the PchTr22 of the other CMOS transmission gate 7 and the gate-drain stray capacitance CSN3 of the NchTr23 of the other CMOS transmission gate 7 is also added. Will be corrected. Therefore, the charges injected into the coupling capacitor 8 due to the switching of the voltage applied to the gates of the PchTr 22 and the NchTr 23 can also be canceled.
It will ensure that the correct comparison results are always obtained.

According to the third aspect of the invention, when the PchTr11 and the NchTr12 of the CMOS transmission gate 6 constituting the first switch means 18 transit from the conducting state to the non-conducting state, the fourth channel is connected in parallel to the PchTr11 and the NchTr12. The PchTr 29 and the NchTr 30 of the CMOS transmission gate 28 forming the switch means 20 maintain the conductive state. Therefore, even if there is an imbalance between the stray capacitance between the gate and drain of the PchTr 11 and the stray capacitance between the gate and drain of the NchTr 12 on the side of the first switch means 18, the PchT
The charges injected into the coupling capacitor 8 due to the switching of the voltage applied to the gates of the r11 and the NchTr12 are PchT on the side of the fourth switch means 20.
It is released to the first input terminal 1 through r29 and NchTr30. That is, the PchTr1 of the CMOS transmission gate 6 that constitutes the first switch means 18
The imbalance of the gate-drain stray capacitance of 1 and NchTr12 can be ignored. Moreover, the PchTr 29 and the NchT of the CMOS transmission gate 28 forming the fourth switch means 20.
r30 is stray capacitance between gate and drain CSP3, CSN5
Are designed to be equal to each other, the Pch
When the Tr 29 and the Nch Tr 30 make a transition from the conducting state to the non-conducting state, electric charges are not injected into the coupling capacitor 8 due to the switching of the voltage applied to the gate. Therefore, the influence of the feedthrough of the clock signal for driving the first and fourth switch means 18, 20 can be eliminated, and a correct comparison result can always be obtained.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Three embodiments according to the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 is a circuit diagram showing an embodiment of a chopper type comparator according to the present invention.
In the figure, the first input terminal 1 to which the analog voltage VIN to be compared is applied is the first CMOS transmission gate 6, and the second input terminal 2 to which the reference voltage Vref is applied is the second input terminal 2. Through the CMOS transmission gate 7, both are coupling capacitors 8
Connected to the input point 3 of. The output point of this coupling capacitor 8 is connected to the input terminal 4 of the inverter 9,
The output terminal 5 of the inverter 9 is fed back to the input terminal 4 of the inverter 9 via the third CMOS transmission gate 10.

The first CMOS transmission gate 6 has a gate Pc to which an inverted clock signal ~ φ is applied.
It is composed of an hTr11 and an NchTr12 whose gate is supplied with a non-inverted clock signal φ, and each source and drain are commonly connected. A compensating NchTr 13 is connected to the first CMOS transmission gate 6, and the compensating NchTr 13 has a gate having the NchTr 13 of the first CMOS transmission gate 6.
12 is connected to the gate and the source is the PchTr11 and Nch of the first CMOS transmission gate 6.
It is connected to the commonly connected drains of Tr12. However, the drain of the compensation NchTr 13 is open without being connected to anything.

Turning on / off of the second CMOS transmission gate 7 also applies to the non-inverted and inverted clock signals φ, ...
controlled by φ. However, when the first CMOS transmission gate 6 becomes conductive, the second C
The MOS transmission gate 7 is non-conductive, and when the first CMOS transmission gate 6 is non-conductive, the second CMOS transmission gate 7 is conductive. Of the CMOS transmission gate 7. The third CMOS transmission gate 10 is supplied with non-inverted and inverted clock signals φ, ˜φ so as to be turned on / off at the same timing as the first CMOS transmission gate 6.

Coupling capacitor 8, inverter 9
And the third CMOS transmission gate 10 is
It constitutes one AC amplifier. Reference numeral 21 is an output point of the AC amplifier, that is, an output point of the chopper type comparator.

Next, the operation of the chopper type comparator described above will be described. However, in the first CMOS transmission gate 6, the gate of PchTr11
The stray capacitance 14 between the drains is CSP1 and NchTr1
The stray capacitance 15 between the second gate and drain is CSN1. The stray capacitance 16 between the gate and the source of the compensation NchTr 13 is CSN2. The capacitance of the coupling capacitor 8 is Cc, and the parasitic capacitance 17 attached to it is Csub.
And In the following description, as in the case of FIG. 5, the input point 3 of the coupling capacitor 8 is called the first node, and the input end 4 of the inverter 9 is called the second node.

This chopper type comparator also operates under the control of the non-inverted and inverted clock signals .phi., .About..phi. Having the same timing as in FIG. 6, and has a "bias period" and a "comparison period". .

The analog input voltage is VIN and the reference voltage is Vre
Let f be the voltage change of the first node 3 at the time of transition from the “bias period” to the “comparison period” by ΔV 3 (= Vref −V
IN), the voltage change ΔV4a of the second node 4 at the time of the transition becomes ΔV4a = Cc · ΔV3 / (Cc + Csub) (6) as in the above-mentioned formula (1). .

Further, the PchTr 11 and the NchTr 12 constituting the first CMOS transmission gate 6
Considering the feed-through of the clock signal between the compensation NchTr13 and the compensation NchTr13, the voltage change of the non-inverted clock signal φ at the time of transition from the “bias period” to the “comparison period” is −ΔVφ.
If the voltage change of the inverted clock signal ~ φ is + ΔVφ (where ΔVφ> 0), the amount of charge ΔQφ3 injected into the first node 3 by the switching of these clock signals. Is given by ΔQφ3 = − (CSP1−CSN1−CSN2) · ΔVφ (7) Therefore, the voltage change ΔV4b of the second node 4 due to the injected charges is ΔV4b = ΔQφ3 / (Cc + Csub) = − (CSP1−CSN1−CSN2) · ΔVφ / (Cc + Csub) (8). Therefore, the total voltage change ΔV4 of the second node 4 when the feed-through of the clock signal is taken into consideration is
From the equations (6) and (8), ΔV4 = ΔV4a + ΔV4b = {Cc · ΔV3− (CSP1−CSN1−CSN2) · ΔVφ} / (Cc + Csub) (9)

Generally, the geometrical dimensions of each of the PchTr and NchTr constituting the CMOS transmission gate are such that the gate dimension ratio (W / L) _P of the PchTr is N.
It is determined to be larger than the gate dimension ratio (W / L) _{N of} chTr. Therefore, in the above example, PchTr1
1st gate-drain stray capacitance CSP1 is NchTr
Larger than the stray capacitance CSN1 between the gate and drain of 12 (C
SP1> CSN1) and both stray capacitances CSP1, CSN
There is an imbalance between 1. Therefore, the term of (CSP1-CSN1-CSN2) in equation (9) becomes 0,
That is, as described above, the compensation Nc having the gate-source stray capacitance CSN2 is set so that the value of the equation (7) becomes zero.
hTr13 is added to correct the above imbalance of stray capacitance.

That is, by adding the compensating NchTr 13 to the first CMOS transmission gate 6 so that C SP1 = C SN1 + C SN2, equation (9)
Becomes ΔV4 = CcΔV3 / (Cc + Csub) (10), and the influence of the feedthrough of the clock signal can be eliminated. Accordingly, when the voltage change ΔV3 of the first node 3 is positive, the voltage change ΔV4 of the second node 4 also becomes positive, and the voltage change ΔV of the first node 3 is
When 3 is negative, the voltage change of the second node 4 ΔV4
Also becomes negative, so that a correct comparison result is always output from the comparator output point 21.

For the second CMOS transmission gate 7 provided on the input side of the reference voltage Vref, it is general to use PchTr and NchTr having uniform gate-drain stray capacitances. Therefore, as described above, the gate-drain stray capacitance may normally be compensated only for the first CMOS transmission gate 6 on the input side of the analog voltage VIN. On the other hand, when the imbalance of the gate-drain stray capacitance in the second CMOS transmission gate 7 becomes a problem, the following embodiment is useful.

<Second Embodiment> FIG. 2 is a circuit diagram showing an embodiment of a chopper type comparator according to the present invention.
The chopper type comparator shown in the same figure has the first CMOS transmission gate 7 on the side of the second input terminal 2 as well.
The second compensation NchTr 24 is added in the same form as the CMOS transmission gate 6 of FIG.
That is, the second CMOS transmission gate 7
Is a Pch whose gate is supplied with the non-inverted clock signal φ.
A second compensating NchTr24, which is composed of a Tr22 and an NchTr23 whose gate receives an inverted clock signal ~ φ, whose sources and drains are commonly connected.
Is connected to the gate of the NchTr 23 of the second CMOS transmission gate 7. Also,
The source of the second compensation NchTr 24 is the second CM.
It is connected to the commonly connected drains of the PchTr 22 and the NchTr 23 of the OS transmission gate 7. However, the drain of the second compensation NchTr 24 is open without being connected to anything.

In this case, the stray capacitance 25 between the gate and drain of the PchTr 22 in the second CMOS transmission gate 7 is set to CSP2, and the NchTr23 is
When the stray capacitance 26 between the gate and drain of is the CSN3 and the stray capacitance 27 between the gate and the source of the second compensation NchTr24 is CSN4, the clock signal is switched from the "bias period" to the "comparison period". The amount of charge ΔQφ3 injected into the first node 3 is calculated by the above equation (7).
Instead of ΔQφ3 = {-(CSP1-CSN1-CSN2) + (CSP2-CSN3-CSN4)}. ΔVφ (11)

That is, not only the first compensation NchTr 13 is added to the first CMOS transmission gate 6 so that C SP1 = C SN1 + C SN2 holds, and C
Second CMOS so that SP2 = CSN3 + CSN4 holds
Second compensation NchTr for transmission gate 7
By adding 24, the value of Expression (11) can be set to 0, and the influence of the feedthrough of the clock signal can be surely eliminated.

<Third Embodiment> FIG. 3 is a circuit diagram showing an embodiment of a chopper type comparator according to the invention of claim 3, and FIG. 4 is a timing chart of its clock signal. The chopper type comparator shown in FIG. 3 has the same configuration as that shown in FIG.
r13 is removed, and the first CMOS transmission gate 6 is replaced with the fourth CMOS transmission gate 2
8 are additionally connected in parallel. That is, the first input terminal 1 to which the analog voltage VIN to be compared is applied is the second input terminal 2 to which the reference voltage Vref is applied via the first and fourth CMOS transmission gates 6 and 28. Both are connected to the input point 3 of the coupling capacitor 8 via the second CMOS transmission gate 7.

The first to third CMOS transmission gates 6, 7 and 10 are supplied with the first non-inverted and inverted clock signals φ, to φ similar to those in FIG. The CMOS transmission gate 28 is
The second inverted clock signal ~ φ2 is applied to the gate P
chTr29 and the second non-inverted clock signal φ at the gate
2 and the NchTr 30 to which 2 is applied, and their sources and drains are commonly connected. As shown in FIG. 4, the second non-inverted clock signal φ2 is a signal which rises at the same timing as the first non-inverted clock signal φ and falls later than the first non-inverted clock signal φ. Also, the second inverted clock signal ~ φ2 is
Is a signal obtained by inverting the non-inverted clock signal φ 2. That is, in the fourth CMOS transmission gate 28, the first and third CMOS transmission gates 6 and 10 are turned on at the same time, and the first and third CMOS transmission gates 6 and 10 are turned off. The second non-inverted and inverted clock signals .phi.2, .about..phi.2 are applied so that the second non-inverted and inverted clock signals are brought into the non-conductive state with a slight delay from the timing at which they are brought into the conductive state.

Next, the operation of the chopper type comparator described above will be described. However, in the fourth CMOS transmission gate 28, the floating capacitance 31 between the gate and drain of the PchTr 29 is set to CSP3, and the NchTr
The stray capacitance 32 between the gate and drain of 30 is CSN5.

As shown in FIG. 4, both the first and second non-inverted clock signals .phi. And .phi.2 have a logical value "H" (the first and second inverted clock signals .about..phi. And .phi.2 are logical values "." L ") is called the" bias period ",
Both the first and second non-inverted clock signals .phi. And .phi.2 are logical values "L" (first and second inverted clock signals .phi., .About.
φ2 is the "comparison period" when the logical value is "H")
Call. The period between these “bias period” and “comparison period” is called the “pre-sampling period”. In the "pre-sampling period", the first non-inverted clock signal φ has a logical value "L" (the first inverted clock signal ~ φ has a logical value "H").
However, the second non-inverted clock signal .phi.2 maintains the logical value "H" (the second inverted clock signal .about..phi.2 is the logical value "L") following the "bias period".

Considering the feedthrough of the clock signals of the first and fourth CMOS transmission gates 6 and 28, when the transition from the "bias period" to the "pre-sampling period" takes place, the logical value "H" changes to the logical value " The voltage change of the first non-inverted clock signal φ that switches to L ″ is −ΔVφ, and conversely, the voltage change of the first inverted clock signal to φ that switches from the logical value “L” to the logical value “H”. + ΔVφ In addition, the voltage change of the second non-inverted clock signal φ 2 which changes from the logical value “H” to the logical value “L” at the transition from the “pre-sampling period” to the “comparison period” is −ΔVφ 2
On the contrary, the voltage change of the second inverted clock signal ~ φ2 that switches from the logical value "L" to the logical value "H" is + ΔVφ2.
And However, ΔVφ> 0 and ΔVφ2> 0.

First non-inverted and inverted clock signals φ, ...
The amount of charge ΔQφ3 'injected into the first node 3 by the switching of φ is given by ΔQφ3' =-(CSP1-CSN1) ΔVφ (12). Therefore, the voltage change .DELTA.V4c of the second node 4 due to this injected charge is .DELTA.V4c = .DELTA.Q.phi.3 '/ (Cc + Csub) =-(CSP1-CSN1) .multidot..DELTA.V.phi ./ (Cc + Csub) (13).

Further, the charge amount ΔQφ3 ″ injected into the first node 3 by the switching of the second non-inverted and inverted clock signals φ2, ∼φ2 is ΔQφ3 ″ = as in the equation (12). -(CSP3-CSN5) .ΔVφ2 (14) Therefore, the voltage change ΔV4d of the second node 4 due to the injected charges is ΔV4d = ΔQφ3 ″ / (Cc + Csub) = − (CSP3−CSN5) · ΔVφ2 / (Cc + Csub) (15).

Therefore, in the case where the feedthroughs of the four clock signals φ, ˜φ, φ2, and ˜φ2 are taken into consideration in the transition from the “bias period” to the “comparison period” through the “presampling period”, Total voltage change of node 4 of 2 ΔV4
From equations (6), (13) and (15), instead of equation (9) above, ΔV4 = ΔV4a + ΔV4c + ΔV4d = {Cc · ΔV3− (CSP1−CSN1) · Δ Vφ- (CSP3-CSN5) .ΔVφ2} / (Cc + Csub) (16)

However, since the fourth CMOS transmission gate 28 maintains the conductive state even when the transition from the "bias period" to the "pre-sampling period" occurs,
Of the equation (12) injected into the first node 3 by switching between the non-inverted and inverted clock signals φ and
Qφ3 'flows out to the first input terminal 1 through the fourth CMOS transmission gate 28. For this reason,
P in the first CMOS transmission gate 6
chTr11 gate-drain stray capacitance CSP1 and N
Even if there is an imbalance with the gate-drain stray capacitance CSN1 of chTr12, the formula (1
The voltage change ΔV4c in 3) can be ignored. Also, CSP3 = C
If the PchTr 29 and the NchTr 30 of the fourth CMOS transmission gate 28 are designed so that SN5 holds, the second non-inverted and inverted clock signals φ2,
Expression (14) for the first node 3 by switching φ 2
The injected charge amount ΔQφ3 ″ can be set to 0, and the value of the voltage change ΔV4d in the equation (15) due to ΔQφ3 ″ can be set to 0. That is, the equation (16) becomes ΔV4 = ΔV4a = Cc · ΔV3 / (Cc + Csub) (17)

As described above, according to this embodiment, it is possible to eliminate the influence of clock signal feedthrough. As a result, when the voltage change ΔV3 of the first node 3 is positive, the voltage change ΔV4 of the second node 4 also becomes positive, and when the voltage change ΔV3 of the first node 3 is negative. Since the voltage change ΔV4 of the second node 4 becomes negative,
A correct comparison result is always output from the comparator output point 21.

When the imbalance of the stray capacitance in the second CMOS transmission gate 7 provided on the input side of the reference voltage Vref poses a problem, the second
The CMOS transmission gate 7 may be additionally connected in parallel with PchTr and NchTr having the same gate-drain stray capacitance and driven by the second non-inverted and inverted clock signals φ2, φ2.

[0052]

As described above, according to the first aspect of the invention, the CMOS is provided in the first switch means on the first input terminal side to which the analog voltage to be compared is applied.
Since a configuration is adopted in which a compensation NchTr having a gate-source stray capacitance CSN2 is added to the transmission gate, the Pc of the CMOS transmission gate is
The stray capacitance CSP1 between the gate and drain of hTr and the CM
Gate of NchTr of OS transmission gate
The imbalance between the drain and the stray capacitance CSN1 is corrected, and the charges injected into the coupling capacitor due to the switching of the voltage applied to the gates of the PchTr and NchTr can be canceled. You will always get the correct comparison result. Further, since the floating capacitance between the gate and the drain is compensated, the sizes of the PchTr and NchTr of the CMOS transmission gate to which the analog input voltage is applied can be freely selected and designed.

According to the second aspect of the invention, the gate-source stray capacitance CSN4 is also provided in another CMOS transmission gate constituting the second switch means on the side of the second input terminal to which the reference voltage is applied. Other compensation Nc to have
Since the configuration in which hTr is added is adopted, the other CMOS
The imbalance between the stray capacitance CSP2 between the gate and drain of the PchTr of the transmission gate and the stray capacitance CSN3 between the gate and drain of the NchTr of the other CMOS transmission gate is also corrected, and the Pch is corrected.
The charges injected into the coupling capacitor due to the switching of the voltage applied to the gates of Tr and NchTr can also be canceled, and a correct comparison result can always be obtained. Also, since the stray capacitance between the gate and drain is compensated, the CM to which the analog input voltage is applied
PchTr and Nch of OS transmission gate
Not only Tr but also PchTr and NchTr of the CMOS transmission gate to which the reference voltage is applied can be freely selected and designed in size.

According to the third aspect of the invention, PchTr and Nc having the same gate-drain stray capacitances CS3 and CSN5 are provided.
A CMOS transmission gate provided with hTr is additionally connected in parallel as a fourth switch means to a CMOS transmission gate as a first switch means to which an analog voltage to be compared is applied,
Since the fourth switch means is switched to the non-conducting state after the first switch means, the stray capacitance between the gate and drain of the PchTr and NchTr of the CMOS transmission gate as the first switch means is unbalanced. Even if it exists, the correct comparison result is always obtained. Also, the CM as the first switch means
PchTr and Nch of OS transmission gate
Since the Tr does not affect the comparison result even if there is an imbalance in the gate-drain stray capacitance, the size of Tr can be freely selected and designed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a chopper type comparator according to the invention of claim 1.

FIG. 2 is a circuit diagram showing an embodiment of a chopper type comparator according to the invention of claim 2;

FIG. 3 is a circuit diagram showing an embodiment of a chopper type comparator according to the invention of claim 3;

4 is a timing diagram of clock signals of the chopper type comparator of FIG.

FIG. 5 is a circuit diagram showing a configuration of a conventional chopper type comparator.

6 is a timing diagram of clock signals of the chopper type comparator of FIG.

[Explanation of symbols]

1 ... 1st input terminal 2 ... 2nd input terminal 3 ... Coupling capacitor input point (1st node) 4 ... Inverter input terminal (2nd node) 5 ... Inverter output terminal 6 ... (No. 1) CMOS transmission gate 7 ... Second CMOS transmission gate (other C
MOS transmission gate) 8 ... Coupling capacitor 9 ... Inverter 10 ... Third CMOS transmission gate (third)
Switch means of 11) P-type MOS transistor 12 ... N-type MOS transistor 13 ... (first) compensation N-type MOS transistor 14 ... Floating capacitance between gate and drain of P-type MOS transistor of first CMOS transmission gate (CSP1) 15 ... Floating capacitance between gate and drain of N-type MOS transistor of first CMOS transmission gate (CSN1) 16 ... Gate of first compensation N-type MOS transistor
Stray capacitance between sources (CSN2) 18 ... First switch means 19 ... Second switch means 20 ... Fourth switch means 21 ... Comparator output point 22 ... P-type MOS transistor 23 ... N-type MOS transistor 24 ... 2. Compensation N-type MOS transistor (other compensation N-type MOS transistor) 25 ... Stray capacitance (CSP2) between gate and drain of P-type MOS transistor of second CMOS transmission gate 26 ... Second CMOS transmission gate Stray capacitance (CSN3) between the gate and drain of the N-type MOS transistor of ...
Source-to-source stray capacitance (CSN4) 28 ... Fourth CMOS transmission gate 29 ... P-type MOS transistor 30 ... N-type MOS transistor 31 ... Fourth CMOS transmission gate P-type MOS transistor gate-drain stray capacitance ( CSP3) 32 ... Stray capacitance between gate and drain of N-type MOS transistor of fourth CMOS transmission gate (CSN5) φ ... (First) non-inverted clock signal to φ ... (First) inverted clock signal φ2 ... Second non-inverted clock signal ~ φ2 ... Second inverted clock signal

Claims (3)

(57) [Claims] 1. A first on / off control so that when one is in a conducting state, the other is in a non-conducting state.
And one end connected to the second switch means and a first input terminal to which an analog voltage to be compared is applied, via the first switch means,
A coupling capacitor having one end connected to a second input terminal to which a reference voltage is applied via the second switch means; and an inverter having an input end connected to the other end of the coupling capacitor, It is interposed between the output end of the inverter and the input end of the inverter, and when the first switch means is in the conductive state, it is also in the conductive state, and when the first switch means is in the non-conductive state, it is the same. A third switch means that is turned on / off so as to be in a non-conducting state, and the first switch means has a source and a drain that are commonly connected, and when one is in a conducting state, the other is also in a conducting state. State, and the voltage applied to each gate is controlled so that when one becomes non-conductive, the other becomes non-conductive. A CMOS transmission gate having an OS transistor, a gate connected to a gate of an N-type MOS transistor of the CMOS transmission gate, and a source of a common-connected drain of each of the P-type and N-type MOS transistors of the CMOS transmission gate And a compensation N-type MOS transistor connected to the CMOS transmission gate, wherein the P-type and N-type MOS transistors of the CMOS transmission gate and the compensation N-type MOS transistor are gates of the P-type MOS transistor of the CMOS transmission gate.・ Floating capacitance C between drains
SP1 and N-type M of the CMOS transmission gate
Floating capacitance CSN between gate and drain of OS transistor
1. A chopper-type comparator characterized in that each has a geometrical dimension such that the relationship between 1 and the stray capacitance CSN2 between the gate and source of the compensating N-type MOS transistor satisfies CSP1 = CSN1 + CSN2. 2. The chopper type comparator according to claim 1, wherein the source and drain of each of the second switch means are commonly connected, and when one of them is in a conductive state, the other is in a conductive state, and one of them is in a conductive state. Another CMOS transmission gate having P-type and N-type MOS transistors in which the voltage applied to each gate is controlled so that the other becomes non-conducting when it becomes non-conducting; Another N-type MOS transistor for compensation which is connected to the gate of the N-type MOS transistor of the gate and whose source is connected to the commonly connected drains of the P-type and N-type MOS transistors of the other CMOS transmission gate. And P-type and N-type of the other CMOS transmission gate Wherein the MOS transistors other compensating N-type MOS
The transistor is a floating capacitance CSP2 between the gate and drain of the P-type MOS transistor of the other CMOS transmission gate, a floating capacitance CSN3 between the gate and drain of the N-type MOS transistor of the other CMOS transmission gate, and the other. Chopper type comparators having geometrical dimensions such that the relationship between the gate-source stray capacitance CSN4 of the compensating N-type MOS transistor satisfies CSP2 = CSN3 + CSN4. 3. A first on / off control such that when one is in a conducting state, the other is in a non-conducting state.
ON / OFF so that when the first switch means and the second switch means are in the conductive state, they are also in the conductive state, and when the first switch means is in the non-conductive state, they are also in the non-conductive state. A third switch means to be controlled; and the first switch means connected in parallel to the first switch means.
A fourth switch means which is on / off controlled such that when the switch means of FIG. 1 is in a conductive state, it is also in a conductive state, and the first switch means is in a non-conductive state after being in a non-conductive state. One end is connected to the first input terminal to which a target analog voltage is applied via the first and fourth switch means, and the second switch is connected to a second input terminal to which a reference voltage is applied. A coupling capacitor whose one end is connected via means, and an inverter whose input end is connected to the other end of the coupling capacitor and whose output end is connected to the input end via the third switch means. And the source and drain of each of the first and fourth switch means are commonly connected, and when one of them is in a conductive state, the other is in a conductive state, and one of them is in a conductive state. CMOS transmission gates having P-type and N-type MOS transistors in which the voltages applied to the respective gates are controlled so that the other becomes non-conductive when brought into conduction, are respectively provided, and the CMOS of the fourth switch means is provided. The P-type and N-type MOS transistors in the transmission gate are
The floating capacitance CSP3 between the gate and drain of the N-type MOS transistor and the floating capacitance CSN5 between the gate and drain of the N-type MOS transistor have geometrical dimensions such that CSP3 = CSN5. A chopper type comparator.