JPS6386614A - Chopper type comparator - Google Patents

Abstract

PURPOSE:To eliminate malfunctions of a chopper type comparator cased by a clock feedthrough by prividing a clock feedthrough offset amplification stage between the input part switch circuit of said comparator and an input amplification stage. CONSTITUTION:In the stage preceeding the input part amplification stage 52 of a conventional chopper type comparator, the clock feedthrough offset amplification stage 51 is connected which is constituted of an inverse amplifier 40 whose amplification ratio is -1, a switch connected to a point between the I/O terminals of the amplfier 40, and a coupling capacitor. Accordingly, the two charge variations on the input terminal of the input part amplification stage 52 that leads to the inverse amplfier 40 i. e. a charge variation due to the clock feedthrough of the stage 52 and that caused by the clock feedthrough occurring in the clock feedthrough offset amplification stage 51, are offset with the charge variation induced through the coupling capacitor of the input part amplification stage 52. As a result, malfunctions due to clock feedthrough do not happen.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a chopper type comparator, and particularly relates to a chopper type comparator that controls malfunctions caused by feedthrough. .

[Prior Art] FIG. 2 is an example of a connection diagram showing the configuration of a conventional chopper comparator. First, the configuration of this conventional chopper comparator will be explained.

In the figure, the M quasi-voltage input terminal 1 is connected to the coupling capacitor 12 via the transmission gate 31, and similarly, the analog voltage input terminal 2 is connected to the coupling capacitor 1 via the transmission gate 32.
It is connected to one pole plate of 2. Clock signals φ and φ, which do not overlap with each other, are applied to the gate terminals of both transmission gates 31 and 32. Transmission gates 31 and 32 are controlled to be turned on or off by the output signals φ and φ, respectively, and transmission gates 31 and 32 are turned on and off in a complementary manner.

The other seed plate of the coupling capacitor 12 is connected to the input terminal of the CMO8 inverting amplifier 41, and the output terminal of the CMO8 inverting amplifier 41 is connected to the transmission gate 3, which is turned on and off at the same timing as the transmission gate 31.
4 to the input terminal 6.

The capacitors 17, 18 drawn in connection with the transmission gate 34 are the gate parasitic capacitances of the P-channel MO3 field-effect transistors of the transmission gate 34, and the capacitors 19.20 are the gate parasitic capacitances of the N-channel MO8W field-effect transistors of the transmission gate 34. This is gate parasitic capacitance. Further, the capacitor indicated by reference number 22 is all the capacitance parasitic to the node 6, and the gate parasitic δ! of the transmission gate 34! ! ! 1
7.

All paranormal capacities, including 18.19.20.

Next, the operation of this chopper comparator will be explained.

When the clock φ has the logical value "H", the transmission gate 31 and the transmission gate 34 are turned on. This period is called an "automatic compensation period". During this period, the input and output terminals of the inverting amplifier 41 are short-circuited, and nodes 6 and 7 are biased to the potential vb at which the inverting amplifier 41 has the highest sensitivity. On the other hand, through transmission gate 31 to node 3! ! A quasi-voltage V is applied. From the above, the clock φ is a logical value "I-1
”, the coupling capacitor 12 is (/V, -
The Ti charge is charged by the potential difference of Vb).

Next, a case where the lower clock signal has a logical value of "H" will be explained. In this case, the clock φ is the logical value “L”
”, transmission gates 31 and 3
4 is turned off and the transmission gate 32 is turned on. This period is called the "comparison period." By turning off transmission gate 34, the charge at node 6 is conserved. Further, an analog input voltage Vin is applied to the node 3 via the transmission gate 32.

Therefore, the voltage change at node 6 at this time ΔV・r
r is proportional to the voltage change ΔV at node 3 and is given by the following equation.

This voltage change ΔV S'' is amplified by the highly sensitive biased inverting amplifier 41, and if necessary, several stages of amplifier #JjA are connected and thereby amplified to the MOS level.In other words, the reference voltage ratio ■The magnitude relationship of analog input voltage v:n with respect to ref is a logical value “H” or L
” is output.

[Problems to be Solved by the Invention] The explanations so far have been made without taking into account the existence of clock feedthrough, but if this is taken into account, the following problems arise.

Here, clock feedthrough refers to the inflow and outflow of charges through the gate parasitic disturbance of the transmission gate due to changes in the clock signal.

Now, let's consider the case where you move from the automatic compensation period to the comparison period. If the voltage change of the clock φ at this time is ΔV cQk, the voltage change of the clock φ is -ΔV cQk.

Therefore, by switching the clock signal,
tJi flowing into node 6 through one gate parasitic capacitance fl17, ΔQc, = -CspΔcQk 0Csr+ΔV cut--(C
sp-Csn) ΔV cll! k (Δcl
lk>O)...(2) It is given by: Due to this, the voltage change at node 6 Δv,''
′ becomes . Therefore, the total voltage change ΔVG′ at node 6 when clock feedthrough is taken into account is Δv,
,'' and Δv6''.

That is, ΔV, l-ΔV, ″+ΔV, rn...<4) In the above formula (4), l Cc ΔV s l > i (C3D-C5
n) ΔV cuk l... (5) If this is the case, then there is no problem or Ij, but if this is not the case, the following problem arises.

<1) When Csp-C5n>O, [Δv, >0 and CCΔvs < (Cs++-C5n)ΔV elk
When J is established, ΔVG'<O.

(2) When Csp−C5n<O, “ΔV,<O
and CCΔV, > (Csp-Csn)ΔV cik
J When the force is established, ΔVs'>O.

In other words, the voltage change ΔV, rrJ at node 6 caused by the switching of the OFF signal is compared in absolute value with the voltage change ΔV,'' at node 6 caused by the voltage change Δ■, at node 3. If it is large,
Even though the voltage change Δ■ at node 3 is positive,
There are cases where the voltage change ΔVs' at node 6 becomes negative, or the voltage change Δ6' at node 6 becomes positive even though the voltage change ΔV at node 3 is negative. An incorrect logic value is output from the comparator.

This invention was made in order to solve the above-mentioned problems, and aims to provide a chopper type comparator that does not cause malfunctions due to overflow feedthrough. .

[Means for Solving the Problems] The chopper comparator according to the present invention has an amplification factor installed before the input amplification stage of the conventional chopper comparator in order to suppress malfunctions caused by clock feedthrough. A clock feedthrough canceling amplification stage is connected, which is composed of a -1x inverting amplifier, a switch connected between its input and output terminals, and a coupling capacitor.

[Function] The chopper type comparator in this invention has an input amplifier stage 5.
2 (see Figure 2), there are two charge changes at the input end of the inverting amplifier: a charge change due to the clock feed-through of the input amplifier stage, and a charge change due to the clock feed-through occurring in the clock feed-through canceling amplifier stage. However, the amount change induced through the input amplifier stage coupling capacitor is canceled out, and malfunctions due to clock feedthrough do not occur.

[Practice of invention I #1 example] Hereinafter, a practical example of this invention will be explained with reference to the drawings.

FIG. 1 is a V connection diagram showing the configuration of a chopper type comparator according to an embodiment of the present invention, in which an input section switch circuit 50
The clock feedthrough canceling amplifier stage 5] is connected between the input section amplifier stage 52 and the input section amplifier stage 52. NaJ
3. The other components of 81 are exactly the same as the configuration shown in FIG. 2, and their explanation will be omitted here.

One plate of the coupling capacitor 11 included in the clock feedthrough canceling amplifier 51 is connected to the output terminal of the input section switch circuit 50. The other plate of the coupling capacitor 11 is an inverted m
The input end of the width transducer 40 is connected. The output terminal of the inverting amplifier 40 is connected to the input terminal of the input section amplification stage 52, and is fed back to the input terminal of the inverting amplifier 40 via the transmission gate 33, which turns on and off at the same timing as the transmission gate h31.34. There is. The inverting amplifier 40 is a diode-connected P-channel MOSa.
It consists of an f field effect transistor 53 and an N channel MO8 field effect transistor 54. Inverting amplifier 4
The input terminal of 0 is the gate terminal of the N-channel MO8II field effect transistor 54, and the output terminal is the drain of both transistors 53 and 54. P channel M OS
'tJX The source of the stomach effect transistor 53 is a high voltage f
f1iVoo, and the source of the P-channel MOS@field effect transistor 54 is connected to the low voltage source vSS.

Capacitors 13, 14, 15, and 16 shown in connection with transmission gate 33 are gate parasitic capacitances of transmission gate 33, and capacitor 21 is a gate parasitic capacitance of transmission gate 33 that is parasitic to node 4. All paranormal capacities including jujube. Note that the two transistors of the transmission gate 33 and the two transistors of the transmission gate 34 have the same transistor size.

Next, the operation of one embodiment of the present invention will be explained.

do.

Since the transmission gate 33 is turned on and off at the same timing as the transmission gates 31 and 34, the input and output terminals of the 1-inverting amplifier 40 are short-circuited during the automatic zero compensation period, and the potentials of the input and output terminals are biased to the potential Va. Ru. During the comparison period, the voltage change ΔV at node 4
, is amplified 11 times by the inverting amplifier 40, so the voltage change ΔV at the node 5 becomes Δv,−Δv4 (6). The inversion amplification 340 with an amplification factor of −1 (8) can be realized as follows.

The transconductance of the P-channel MO3l field-effect transistor 53 is expressed as ')III), N-channel M○
When the transconductance of the S field effect transistor 54 is set to goin, the amplification factor A of the inverting amplifier 40 is given by the following equation.

A −−amn /(il+) −(7)
If the current flowing from the source to the drain of the C1 transistor 53 is 1p, and the current flowing from the drain to the source of the transistor 54 is in, then Ip-In (8) in a steady state. In other words, penetration 1! The flow flows. The reason for this is that during the self i #I zero 14 compensation period when the input and output terminals of the inverting amplifier 40 are short-circuited and during the comparison period when the input difference 1 voltage, that is, the voltage change ΔV at node 3 is extremely small, the transistor 53
．． 54 because they both operate in the saturation region. most,
Since clock feedthrough is not a problem when the input differential voltage ΔV is large, here, transistor 5
The explanation is limited to the case where a minute input difference voltage ΔV such that both 3.54 and 3.54 operate in the saturation region occurs at node 3.

When transistors 53 and 54 are both in the saturation region, (
lap, 1JIn are respectively up-r month l]1
...〈9)un -E■3n I n
- given by (10). Here βp,
βn is given by, respectively. In addition, here, μp
: mobility of holes, μn; mobility of electrons, COX: capacitance of oxide film per unit volume, Wp: gate width of P-channel MO3 field effect transistor 53, p: gate length of transistor 53, Wn: Gate width of N-channel MOS field effect transistor 54, Lo; same transistor 5
The gate length is 4.

Therefore, when equation (2) holds true, equation (7) determines the transistor size of transistors 53 and 54! 2
By doing so, βp-βn (13), an inverting amplifier with an amplification *-i times can be realized.

Using such an inverting amplifier with an amplification factor of -1, clock feedthrough is canceled out by the following chain theory.

In FIG. 1, the voltage change V at node 4 during the comparison period with respect to the automatic 7 compensation period is given by the following equation based on the same concept as equation (4).

At this time, the voltage change ΔVs at node 5 is expressed by formula (6). On the other hand,
Since the voltage change Δv5 at the node 6 is given by the same as equation (14), the following equation can be obtained by eliminating ΔV from equations (15) and (18).

From equation (17), the voltage change ΔV err at node 6 due to clock feedthrough is as follows. In a conventional chopper comparator, the voltage change ΔVerr at node 6 due to clock feedthrough
' is from Equation (4), and from Equations (18) and (19), and the voltage variation due to clock feedthrough can be almost ignored.

In the above embodiment, the inverting amplifier 40 is of a type in which a diode-connected P channel MO3 field effect transistor 53 is used as a load and an N channel MO3 field effect transistor 54 is used as a driver. Any type of inverting amplifier may be used as long as the amplification factor is 11 times.

[Effects of the Invention] As described above, according to the present invention, since the clock feedthrough canceling amplification stage is provided between the input switch circuit and the input amplification stage of the chopper type comparator, the clock This has the effect of suppressing malfunctions of the chopper comparator caused by feedthrough.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a chopper type comparator which is an embodiment of the present invention. FIG. 2 is a connection diagram showing an example of the configuration of a conventional chopper type comparator. In the figure, 1 is a reference voltage input terminal, 2 is an analog voltage input terminal, 7 is an output terminal of the input amplification stage, 11.15 and 12 are coupling capacitors, 13 to 20 are gate parasitic capacitances of the transmission gate, and 21 is a node 4
total parasitic capacitance, 22 is m parasitic capacitance of node 6, 31-3
4 is a 1-transmission gate, 40 is an inverting amplifier with an amplification factor of -1, 41 is a CMO3 inverting amplifier, 50 is an input switch circuit, 51 is an amplification stage for clock feedthrough cancellation, 52 is an input amplification stage, 53 is P channel MOS
'R field effect transistor, 54 is an N-channel O8 field effect transistor. Note that the same numbers in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 5 OS procedure amendment (voluntary)

Claims (1)

[Claims] A first switch means connected to an input terminal to which a compared analog voltage signal is applied and controlled by a clock signal; and a first switch means connected to an input terminal to which a reference voltage is applied and controlled by the clock signal. a second switch means to be controlled; a first capacitor having one plate connected to the output sides of the first and second switch means; and an input side connected to the other plate of the first capacitor. a first amplifier connected thereto; a third switch means connected in parallel to the first amplifier and controlled by the clock signal; and a connection between the output side of the first amplifier and the third switch means. a second capacitor whose one plate is commonly connected to the output side; a second amplifier whose input side is connected to the other plate of the second capacitor; and a second amplifier connected in parallel to the second amplifier. and a fourth switch means connected to the clock signal and controlled by the clock signal, wherein the first amplifier has an amplification factor of -1.