JP2671856B2 - Tunnel transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tunnel transistor and a method of manufacturing the same, and more particularly, to a transistor using a tunnel phenomenon that enables high integration, high speed operation and multi-function, and a method of manufacturing the same.

[0002]

2. Description of the Related Art The mainstream of transistors is a device such as a MOS field effect transistor (FET) using silicon (Si) at present, but it is more and more required to realize a higher integration and a higher speed integrated circuit. A Schottky junction type field effect transistor (MESFET: ME) having a structure in which a gate electrode is directly formed on a conductive layer on the surface of a semiconductor substrate by using a compound semiconductor such as GaAs which can operate at high speed.
Tal Semiconductor FETs) are also known.

However, although speeding up and higher integration of integrated circuits using these transistors have been promoted by miniaturization of element size from the past, miniaturization has a limit and wiring delay is caused. The influence cannot be ignored. Therefore, in order to solve these problems, it is necessary to reduce the number of transistors in the integrated circuit by further increasing the speed of the device itself and realizing the multifunction.

Therefore, it is possible to realize higher performance and more functions than ever before.
Various transistors have been proposed as possible
However, what is the above-mentioned MOS type FET and MESFET?
P on the surface of a semiconductor with different operating principles⁺-N⁺ At the junction
Introduces a tunnel transistor that utilizes the tunnel phenomenon of
Proposed by the authors (for example, Japanese Patent Laid-Open No. 58-9)
No. 6766: Title of invention “semiconductor device”
-41520 Publication: Title of Invention "Semiconductor Device", Japanese Patent Application
No. 6-20707: Title of invention "Tunnel Transis
And its manufacturing method "). The tunnel that makes this proposal
The transistor is a problem in the limit of miniaturization of MOS FET.
It is an active use of the tunnel effect
The use of negative resistance characteristics together with a structure suitable for miniaturization
Enable multi-functional operation and enable high-density integrated circuits
Trying to do it.

FIG. 3 is a schematic view of a layer structure of an example of the conventional tunnel transistor described above. In this tunnel transistor, a source layer 2, a low impurity concentration layer 3, a drain layer 4, a channel layer 5 and an insulating layer 6 are laminated on a substrate 1, and an ohmic junction is formed on each of the source layer 2 and the drain layer 4. In this structure, a source electrode 8 and a drain electrode 9 are formed, and a gate electrode 7 is formed on the insulating layer 6.

Here, the source layer 2 is made of a semiconductor having one conductivity type, and the drain layer 4 is made of a degenerate semiconductor having a conductivity type different from that of the source layer 2. The channel layer 5 is made of a semiconductor having the same conductivity type as the source layer 2. The insulating layer 6 is made of a material having a wide band gap.

How to manufacture this conventional tunnel transistor
The method and operation are as follows: i-GaAs (where i is an intrinsic
Or, it means a non-doped semiconductor that can be regarded as substantially authentic.
Abbreviation: same as below), n in source layer 2⁺-GaAs, low
I-GaAs for the impurity concentration layer 3 and p for the drain layer 4⁺−
GaAs, n in the channel layer 5⁺-For GaAs and insulating layer 6
i-Al _0.3Ga_0.7As, aluminum for the gate electrode 7
(Al), gold (A) for the source electrode 8 and the drain electrode 9
An example using u) will be described.

First, the molecular beam crystal growth method (MBE: Mol
n ⁺ by means of the Equal Beam Epitaxy)
The -GaAs source layer 2, the i-GaAs low impurity concentration layer 3, and the p ⁺ -GaAs drain layer 4 are continuously grown.
Next, mesa etching is performed so as to leave the drain region, and the n ⁺ -GaAs source layer 2 is exposed. afterwards,
The surface is cleaned in the MBE apparatus, and the n ⁺ -GaAs channel layer 5 and the i-Al _0.3 Ga _0.7 As insulating layer 6 are regrown. Finally, after etching the regrown layer using the Al gate electrode 7 as a mask, the source electrode 8 and the drain electrode 9 are formed to complete the device.

According to this conventional tunnel transistor, since the source layer 2 and the channel layer 5 have the same conductivity type, when the source electrode 8 is set to the ground potential and a positive voltage is applied to the drain electrode 9, the channel layer 5 is formed. By the n ⁺ -p ⁺ tunnel junction between the drain layer 4 and the drain layer 4, a tunnel current flows between the drain and the source due to the tunnel effect at the time of forward bias like the Esaki diode (tunnel diode), and the current-voltage characteristic has a negative resistance The characteristic appears. Since this negative resistance characteristic depends on the carrier concentration of the channel layer 5, it is controlled by modulating the carrier concentration of the channel by the gate voltage. As a result, transistor characteristics having negative resistance characteristics can be obtained.

[0010]

However, although the above-mentioned conventional tunnel transistor can be easily manufactured by applying the existing crystal growth technique, it has a vertical structure and is easy to integrate. It does not have a planar structure. Also, between the gate and drain, between the source and drain,
Since there is a large amount of overlap between the source and drain, there is a problem that the parasitic capacitance is large and high-speed operation is hindered.

The present invention has been made in view of the above points,
An object of the present invention is to provide a tunnel transistor having a planar structure and a small parasitic capacitance, and a manufacturing method for manufacturing the tunnel transistor.

[0012]

In order to achieve the above-mentioned object, a tunnel transistor of the present invention according to claims 1 and 2 has a first conductivity type channel layer provided on a substrate and a channel layer on the channel layer. An insulating layer provided on the insulating layer, a first conductive type gate layer formed on the insulating layer and having an impurity concentration lower than that of the channel layer, and a first conductive type gate layer formed on the insulating layer. A second region different from the first conductivity type formed on the substrate and in contact with each side surface of the channel layer, the insulating layer, and the gate layer of the first conductivity type source region;
Or a source region, a gate electrode and a drain electrode respectively connected to the channel layer, the gate layer and the drain region, or a source region similar to the drain region. The semiconductor layer is in contact with the other side surface of each of the channel layer, the insulating layer, and the gate layer, and is formed on the substrate by the degenerate semiconductor having the second conductivity type.

According to the method of manufacturing a tunnel transistor of the present invention as defined in claims 3 and 5, a channel layer is formed on the substrate,
A first step of sequentially laminating an insulating layer and a gate layer of the first conductivity type, and a portion which becomes a drain region or a portion which becomes a drain region and a source region of the laminated structure formed by the first step are formed. A second step of removing and exposing the substrate, and a third step of forming a drain region or a drain region and a source region by a degenerated semiconductor of the second conductivity type on the substrate exposed by the second step. And a fourth step of forming a source electrode, a gate electrode, and a drain electrode, respectively.

[0014]

In the tunnel transistor of the present invention as set forth in claim 1, since the drain region is formed in self-alignment with the side surfaces of the channel layer and the gate layer, the source electrode, the gate electrode and the drain electrode are substantially in the same plane. It may be a planar structure located within.

Further, in the tunnel transistor of the present invention as defined in claim 2, not only the drain region but also the source region is formed in self-alignment with the side surfaces of the channel layer and the gate layer. Instead, a planar structure can be obtained in which a negative resistance characteristic appears.

Further, in any of the tunnel transistors of the present invention described above, the gate layer is provided only on the channel layer and may not be present on the drain region.

According to the manufacturing method described in claims 3 and 5, the tunnel transistor of the present invention described in claims 1 and 2 can be manufactured.

[0018]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a schematic diagram of a layer structure of a first embodiment of a tunnel transistor according to the present invention. In the figure,
The same components as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 1, a channel layer 5 and an insulating layer 6 are sequentially laminated on a substrate 1. A gate layer 10 and a source region 11 are formed on the insulating layer 6. Further, the drain region 12 is formed on the substrate 1 by the channel layer 5 and the insulating layer 6.
And adjacent to the side surfaces of the gate layer 10, respectively. Further, a gate electrode 7, a source electrode 8 and a drain electrode 9 are formed on the gate layer 10, the source region 11 and the drain region 12.

The gate layer 10 has the same conductivity type as the channel layer 5, but the impurity concentration is set lower than that of the channel layer 5. The drain region 12 has a conductivity type opposite to that of the channel layer 5 and is made of a degenerated semiconductor.

Next, in the tunnel transistor of this embodiment,
For the operation, i-GaAs is applied to the substrate 1 and n is applied to the channel layer 5.⁺−
GaAs, n-Al in insulating layer 6_0.3Ga_0.7As, gate
N-GaAs, drain region in the layer 10 and the source region 11
P in area 12⁺ -GaAs, Au for gate electrode 7, source
For example, AuGe is used for the electrode 8 and AuZn is used for the drain electrode 9.
I will explain.

In this embodiment, the drain region 12 is a degenerate semiconductor in which a high concentration of holes is present, which is formed in a cell-aligned manner with respect to the gate layer 10, and is located between the edge of the channel layer 5 and the drain region 12. An n ⁺ -p ⁺ tunnel junction is formed in the. Further, as will be described later, the source electrode 8 is electrically connected to the channel layer 5 through at least the source region 11 and the insulating layer 6 by alloying. Therefore, the source electrode 8 and the channel layer 5 have the same potential.

Therefore, the source electrode 8 is set to the ground potential,
When a positive voltage is applied to the gate electrode 7, due to the n ⁺ -p ⁺ tunnel junction formed between the channel layer 5 and the drain region 12, a negative resistance characteristic appears at the time of forward bias like the Esaki diode. .

Although an np ⁺ junction is also formed between the gate layer 10 and the drain region 12, the gate layer 10
The impurity concentration of the channel layer 5 is set to be lower than that of the channel layer 5.
It is smaller than the current flowing between the drain regions 12 and can be almost ignored. Therefore, the carrier concentration of the channel layer 5 is modulated by the voltage of the gate layer 10 connected to the gate electrode 7, and a band-to-band tunnel current between the channel layer 5 and the drain region 12 is generated by the gate electrode 7 as in the conventional tunnel transistor. Can be controlled by the applied voltage.

The structure of this embodiment has a planar structure in which the source electrode 8, the gate electrode 7 and the drain electrode 9 are located in substantially the same plane as shown in FIG. -Easy to process and suitable for high integration. In addition, the gate layer 10
Is provided only on the channel layer 5 near the band-to-band tunnel junction and does not exist on the drain region 12, so that the gate capacitance can be significantly reduced as compared with the conventional tunnel transistor.

Next, the operation of the manufacturing method of this embodiment will be described.
The same material as that used in the description will be used for description. Ma
On the semi-insulating GaAs substrate 1 having a thickness of 500 nm.
GaAs, 20 nm thick n⁺-GaAs (Te = 2x
10¹⁹cm^-3 ) Channel layer 5, 30 nm thick n
-Al_0.3Ga_0.7Insulating layer 6 made of As, having a thickness of 80 nm
n-GaAs (Si = 5 × 10¹⁸cm^-3 ) By gate
The layers are grown by applying the MBE method to obtain their laminated structure
You.

Subsequently, the drain region in the laminated structure
To form a drain formation region on the substrate for forming 12
On the substrate after removing the laminated structure by etching
Carbon (C) -doped p⁺-GaAs (C = 2 × 10²⁰
cm^-3 ) Is buried by an organometallic MBE method.
Area 12 is formed. Further, the above-mentioned n-G having a thickness of 80 nm
A part of the aAs gate layer is removed by etching,
The source layer 10 and the source region 11 are formed.

Next, AuGe and AuZn are formed on the source region 11 and the p ⁺ -GaAs drain region 12 and alloyed at 410 ° C. to form the source electrode 8 and the drain electrode 9, respectively. As a result, the source electrode 8 penetrates at least the source region 11 and the insulating layer 6 and is connected to the channel layer 5. Finally, Au is formed as the gate electrode 7 on the gate layer 10 to complete the manufacture of the tunnel transistor.

According to the tunnel transistor of the present embodiment produced in this way, transistor characteristics having clear negative resistance characteristics similar to those of conventional tunnel transistors can be obtained, and the peak current density of the negative resistance characteristics can be obtained. A larger value of 10 ⁴ A / cm ² than that of the conventional structure was obtained. Further, the gate capacitance of this embodiment is 1/3 or less of that of the conventional structure.

Next, a second embodiment of the present invention will be described. FIG. 2 is a schematic view of the layer structure of the second embodiment of the tunnel transistor according to the present invention. In the figure, the same components as those in FIGS. 1 and 3 are designated by the same reference numerals. In FIG. 2, the source region 13 is a semiconductor region having the same conductivity type as the drain region 12. The present embodiment is characterized in that the drain region 12 and the source region 13 are formed symmetrically, so that it is easier to manufacture than the first embodiment.

The operation principle of the second embodiment is also similar to that of the first embodiment. For example, the source electrode 8 is set to the ground potential and a positive voltage is applied to the gate electrode 7, so that the channel layer 5 and the drain region 12 are formed. N ⁺ −p ⁺ formed between
Due to the tunnel junction, a negative resistance characteristic appears at the time of forward bias as in the Esaki diode.

In this embodiment, the negative resistance characteristic appears regardless of the drain bias direction. This is because n ⁺ −p ⁺ tunnel junctions are formed between the channel layer 5 and the source region 13 and between the channel layer 5 and the drain region 12, respectively, and one of these two tunnel junctions has a low resistance value in the reverse direction. This is because it becomes a bias, and the other becomes a forward bias exhibiting a negative resistance characteristic.

Next, the manufacturing method of this embodiment will be described.
You. In this embodiment, for example, the substrate 1 is made of i-GaAs,
N on the flannel layer 5⁺-GaAs, n-Al in insulating layer 6_0.3Ga
_0.7As, n-GaAs in the gate layer 10, drain region
12 and p in source region 13⁺ -GaAs, gate electrode
7 is Au, and source electrode 8 and drain electrode 9 are AuZn.
Shall be used.

First, a semi-insulating GaAs substrate 1 having a thickness of 5 is formed.
00 nm i-GaAs, 20 nm thick n⁺-GaA
s (Te = 2 × 10¹⁹cm^-3 ) By the channel layer 5, thickness
30 nm n-Al_0.3Ga_0.7Insulating layer 6 of As,
80 nm thick n-GaAs (Si = 5 × 10¹⁸c
m^-3 ), The gate layer 10 is grown by applying the MBE method.
Obtain their laminated structure.

Subsequently, the drain region in the laminated structure
On the substrate to form 12 and source region 13 respectively
Part of the laminated structure that will become the drain formation region and the source region of
Is removed by etching, and carbon (C) is left on the substrate after the removal.
Dope p⁺-GaAs (C = 2 × 10²⁰cm^-3 )
Embedded by the machine metal MBE method and the drain region 12 and
The source region 13 is formed as shown in FIG.

Next, AuZn is formed on the p ⁺ -GaAs drain region 12 and the p ⁺ -GaAs source region 13 and alloyed at 410 ° C. to form the drain electrode 9 and the source electrode 8, respectively. Finally, Au is formed as the gate electrode 7 on the gate layer 10 to complete the manufacture of the tunnel transistor of this embodiment.

According to the tunnel transistor of this embodiment produced in this way, transistor characteristics having clear negative resistance characteristics in both directions of the drain bias can be obtained, and the peak current density of the negative resistance characteristics can be obtained as the conventional structure. A larger value of 10 ⁴ A / cm ² was obtained. Further, the gate capacitance of this embodiment is 1/3 or less of that of the conventional structure as in the first embodiment.

The present invention is not limited to the above-described embodiments. For example, as the semiconductor material for the substrate, other than GaAs, Si, Ge, SiGe, InP, In may be used.
Other semiconductors such as GaAs and GaSb may be used.
The semiconductor of the substrate, the source region, and the low concentration layer may be not only a homojunction made of the same kind of semiconductor but also a heterojunction made of different kinds of semiconductors. Further, as the insulating layer 6, Al _0.3
In addition to Ga _0.7 As, GaAS, InAlAs, InP
Other semiconductors that exhibit insulating properties, such as SiO ₂ and Si ₃
It may be an insulator such as N ₄ or AlN.

Further, as the material of the gate electrode 7, Au is used.
Other than these, other metal materials that form an ohmic junction with the gate layer 10 or low-resistance semiconductor materials may be used. Also,
Although the conductivity type of the channel layer 5 is described as n-type in the above embodiments, it may be p-type (however, in this case, the other regions also need to have the conductivity type opposite to that of the embodiments). There is.)

[0039]

As described above, according to the tunnel transistor of the present invention as defined in claims 1 and 2, the source electrode, the gate electrode, and the drain electrode have a planar structure in which they are located in substantially the same plane. The pattern drawing and processing at the time of creation are easy, and therefore it is suitable for high integration.

Further, the tunnel transistor of the present invention is
Since the gate layer is provided only on the channel layer and not on the drain region, the gate capacitance can be significantly reduced as compared with the conventional tunnel transistor.

Further, according to the tunnel transistor of the present invention as defined in claim 2, it is possible to form a planar structure in which a negative resistance characteristic appears regardless of the bias direction of the drain, and the drain region and the source region are symmetrical. It is easy to manufacture due to its location.

Further, according to the manufacturing method of the present invention, it has the same clear negative resistance characteristic as that of the conventional tunnel transistor, the peak current density of the negative resistance characteristic is larger than that of the conventional one, and the gate capacitance is large. However, it is possible to manufacture a smaller tunnel transistor than the conventional one.

As described above, according to the present invention, it is easy to realize a fine structure and reduce the parasitic capacitance, and it is possible to realize an ultrahigh integration and ultrahigh speed functional circuit.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a layer structure of a first embodiment of the present invention.

FIG. 2 is a schematic view showing a layer structure of a second embodiment of the present invention.

FIG. 3 is a schematic view showing a layer structure of a conventional example.

[Explanation of symbols]

 1 substrate 5 channel layer 6 insulating layer 7 gate electrode 8 source electrode 9 drain electrode 10 gate layers 11 and 13 source region 12 drain region

Claims (6)

(57) [Claims] 1. A channel layer of a first conductivity type provided on a substrate, an insulating layer provided on the channel layer, and an impurity concentration set to be lower than that of the channel layer. A gate layer of the first conductivity type formed on the insulating layer, a source region of the first conductivity type formed on the insulating layer, and a channel layer, an insulating layer and a gate layer, respectively. A drain region made of a degenerate semiconductor having a second conductivity type different from the first conductivity type, the drain region being in contact with a side surface of the substrate, the channel layer, the gate layer, and the drain. A tunnel transistor having a source electrode, a gate electrode, and a drain electrode respectively connected to the regions. 2. A first conductivity type channel layer provided on a substrate, an insulating layer provided on the channel layer, and an impurity concentration set to have an impurity concentration lower than that of the channel layer. A gate layer of the first conductivity type formed on the insulating layer, and one side surface of each of the channel layer, the insulating layer and the gate layer, and formed on the substrate, A drain region made of a degenerated semiconductor having a second conductivity type different from the first conductivity type, and contacting the other side surface of each of the channel layer, the insulating layer, and the gate layer, and on the substrate. A source region formed of a degenerate semiconductor having the second conductivity type, and a source electrode, a gate electrode, and a drain electrode connected to the source region, the gate layer, and the drain region, respectively. When Tunnel transistor that. 3. A first layer in which the channel layer, the insulating layer, and the semiconductor layer of the first conductivity type are sequentially stacked on the substrate.
And a second step of exposing the substrate by removing a portion of the laminated structure formed in the first step, which will be a drain region, and a second step on the substrate exposed by the second step. A third step of forming the drain region of the second conductivity type degenerate semiconductor, and a fourth step of separating the first conductivity type semiconductor layer to form the gate layer and the source region, respectively. And a fifth step of forming the source electrode, the gate electrode, and the drain electrode, respectively, and manufacturing the tunnel transistor according to claim 1. 4. The third step is a step of burying the drain region of the degenerate semiconductor of the second conductivity type on the substrate by a molecular beam crystal growth method using an organic metal. The method of manufacturing a tunnel transistor according to claim 3. 5. A first layer in which the channel layer, the insulating layer, and the gate layer of the first conductivity type are sequentially stacked on the substrate.
And the second step of exposing the substrate by removing the drain region portion and the source region portion of the laminated structure formed by the first step, respectively, and the second step. And a third step of forming the drain region and the source region of the second conductive type degenerate semiconductor on each of the one side and the other side of the substrate, and forming the source electrode, the gate electrode, and the drain electrode, respectively. And a fourth step for manufacturing the tunnel transistor according to claim 2. 6. The third step is a step of simultaneously burying the drain region and the source region of the second conductive type degenerate semiconductor on the substrate by a molecular beam crystal growth method using an organic metal, respectively. 6. The method for manufacturing a tunnel transistor according to claim 5, wherein