JP2668881B2 - High-efficiency coding device for image signals - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-efficiency coding apparatus for image signals such as television signals, and more particularly to buffering processing using sub-sampling. [Summary of the Invention] According to the present invention, for a second pixel other than the first pixel regularly located among a plurality of pixels having a temporal or spatial arrangement, a plurality of pixels around each of the second pixels are arranged. Means for predicting the interpolation using the first or second pixel of the above, and detecting the prediction error between the obtained data and the original data of the second pixel by interpolation, and calculating the magnitude of the prediction error Means for generating a control code in response to the control code, and means for transmitting the data of the first pixel and transmitting / decimating the original data of the second pixel in accordance with the control code to form transmission data. A high-efficiency coding apparatus comprising: a means for forming a prediction error for all pixels of a processing unit in advance; a means for totalizing the absolute value of the formed prediction error for each processing unit; Using a summary table, the layout for which output data is required To be less than, means for determining a threshold value for generating a control code is provided. According to the present invention, the density of the sub-sampling is changed according to the characteristics of the fine portion of the image, the restored image quality can be improved, and a high compression ratio can be obtained. Also,
The present invention enables real-time processing and can process not only still images but also moving images. Furthermore, the variable-rate sub-sampling can convert the rate-varying output data to a constant rate below the required rate. [Prior Art] When a digital video signal is transmitted, as a method of compressing the amount of data to be transmitted in comparison with the original amount of data, a method of thinning out pixels by subsampling and lowering a sampling frequency is known. . As one of the sub-sampling, a method is proposed in which the image data is thinned by 1/2, and a sub-sampling point and a 2-bit flag indicating the position of the sub-sampling point used at the time of interpolation are transmitted. . If one pixel data of the digital video signal is 8 bits, adding 2 bits of the flag results in 5 bits per pixel and a compression ratio of (5/8). In the conventional sub-sampling, since the sub-sampling pattern is always the same, there is a problem that the restored image quality is noticeably deteriorated in a portion such as the contour of the object in the image. In particular, when the sub-sampling rate is higher than 1/2, there is a drawback that the image quality is significantly deteriorated. To solve the above-mentioned problem, the present applicant divides one image into a large number of two-dimensional blocks as described in Japanese Patent Application No. 61-11098, and An encoding method has been proposed in which a difference (dynamic range) between a maximum value and a minimum value of a plurality of pixel data is obtained, and a sub-sampling cycle is varied according to a dynamic range of a block. That is, a block having a small dynamic range is determined to be a flat image, and the sub-sampling period is lengthened, for example, to (1/8).
A block having a relatively large dynamic range is determined to be an image having a change, and the sub-sampling cycle is set to (1/2). A block having an extremely large dynamic range is determined to be an image having a drastic change. And no subsampling is performed. As described above, in the high-efficiency encoding device that selectively switches the sub-sampling period according to the dynamic range, the sub-sampling period is set in units of blocks, so that the quality of the restored image is good or bad in units of blocks. And the distortion of the block was conspicuous. In addition, the types that can be selected as the sub-sampling period are limited, and the adaptability to the image features is insufficient. As a solution to these problems, the applicant has
As shown in the specification of Japanese Patent Application No. 62-85210, a basic pixel located regularly is always transmitted, and interpolation prediction is performed for pixels surrounding the basic pixel by using surrounding pixels. , A high-efficiency coding apparatus that controls transmission / decimation according to the magnitude of the prediction error of interpolation is proposed. According to the high-efficiency coding apparatus, no deterioration occurs in units of blocks, and an arbitrary sub-sampling pattern adapted to the characteristics of the image can be formed, so that a good restored image can be obtained. [Problems to be Solved by the Invention] The high efficiency encoding device according to the above-mentioned applicant's proposal is
In order to perform variable-density subsampling, the output data rate varies according to the content of the image. Digital VTR
Then, it is necessary that the amount of data recorded in one track is constant for reasons such as ease of editing. A typical conventional buffering process is to provide a large-capacity buffer memory and obtain output data at a constant rate from this buffer memory. However, when the buffer memory is used, there is a problem that the scale of the hardware becomes large, and there is a problem that overflow or underflow occurs unless the memory capacity is increased. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a high-efficiency encoding apparatus for an image signal capable of obtaining output data at a constant rate without using a buffer memory in variable-density subsampling. [Means for Solving the Problem] In the present invention, the second pixel other than the first pixel regularly located in a plurality of pixels having a temporal or spatial arrangement is referred to as a second pixel. A circuit for performing prediction of interpolation using a plurality of first or second pixels around each of them, and detecting a prediction error between obtained data and original data of the second pixel by interpolation; A circuit for generating a control code according to the magnitude of the prediction error; transmitting data of the first pixel; and transmitting / decimating original data of the second pixel according to the control code to form transmission data In the high-efficiency encoding apparatus, a circuit that forms a prediction error for all pixels in a processing unit in advance, and a circuit that totals the frequency of the absolute value of the formed prediction error for each processing unit, The output data is requested using a table of frequencies. That rate to be less than, a circuit for determining a threshold value for generating a control code is provided. [Operation] As an example, the first pixel located every (4 × 4) pixel of the digital video signal is always transmitted without being thinned out. The second pixels other than the first pixel are thinned out by sub-sampling or transmitted as they are. This determination is made according to the magnitude of the predicted error when the pixels thinned out on the receiving side are interpolated by peripheral pixels. The prediction error is compared with a threshold, and its magnitude is determined. That is, when the prediction error is greater than the threshold,
When the original data is transmitted because the thinning cannot be performed, and when the prediction error is smaller than the threshold value, the original data is not transmitted because the thinning is possible. The data of the second pixel and the data of the first pixel whose transmission / thinning is thus controlled are transmitted. One-bit control data for controlling transmission / thinning is added to each sample of the data of the second pixel. On the receiving side, it is determined whether interpolation is necessary by looking at the control data. If the above threshold value is increased, the number of pixels to be thinned out increases, and the rate of output data decreases. On the other hand, if the threshold value is made smaller, the number of pixels thinned out becomes smaller, and the rate of output data increases. Therefore, buffering processing can be performed by controlling the magnitude of the threshold value. Specifically, in order to determine an appropriate threshold value, the amount of generated information is obtained in advance for a processing unit such as one field, one frame, or a plurality of frames. The generated information amount can be known from the frequency distribution table of the prediction error of the interpolation for each processing unit. By applying thresholds to the frequency distribution table in order from the position where the prediction error is 0, the number of pixels to be thinned out can be known. The required number of thinned pixels corresponding to the target transmission rate is set, and the value when the number of thinned pixels exceeds the required number of thinned pixels is set as the threshold value. The variable-density subsampling is encoded by the threshold. In the present invention, the transmission / thinning-out determination based on the prediction error is made using the original data as in the invention of the previous application, so that real-time processing is possible, and the present invention is applied to a moving image. The present invention is preferable, and since the present invention does not have a block structure, there is no problem that the quality of the restored image quality is conspicuous for each block, and the thinning is determined for each pixel. The adaptability to the features of the image can be made very good. In particular, according to the present invention, it is possible to suppress the rate of the high-efficiency coded output data to be equal to or less than a target value. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This description is made in the following order. a. Entire configuration of one embodiment b. Subsampling encoder c. Subsampling decoder d. Threshold value determination circuit e. Modification a. Entire configuration of one embodiment FIG. Shows the overall configuration of
For example, a digital video signal is supplied to an input terminal denoted by reference numeral 101. This digital video signal is, for example, 1
The sampling frequency is 3.5 [MHz] and the number of quantization bits per pixel is 8 bits. The input digital video signal is supplied to a sub-sampling encoder 102 and a field delay circuit 103. In this embodiment, the processing unit of buffering is one field. The sub-sampling encoder 102 generates a prediction error ε for interpolation, and the prediction error ε is supplied to a threshold value determination circuit 104. The threshold value determination circuit 104 generates a threshold value TH such that the number of pixels to be thinned out exceeds the required number of thinning pixels, and therefore the output data does not exceed the target rate. The digital video signal that has passed through the field delay circuit 103 is supplied to the sub-sampling encoder 105 and undergoes variable density sub-sampling processing. Output data is obtained at the output terminal 28 of the sub-sampling encoder 105, and control data is obtained at the output terminal 28. b. Sub-sampling encoder The sub-sampling encoder 105 will be described with reference to FIG. In FIG. 2, a digital video signal is supplied to an input terminal denoted by reference numeral 1 as a field delay circuit 10.
Supplied from 3. A cascade connection of line delay circuits 2, 3, 4, 5 indicated by LD is connected to the input terminal 1. Also, sample delay circuits 6 and 7 indicated by SD are connected in series to the input terminal 1, sample delay circuits 8 and 9 are connected in series to the output side of the line delay circuit 2, and the output of the line delay circuit 3 is output. Sample delay circuits 10, 11, 12 and
13 are connected in series, sample delay circuits 14 and 15 are connected in series to the output side of the line delay circuit 4, and sample delay circuits 16 and 17 are connected in series to the output side of the line delay circuit 5. These line delay circuits 2, 3, 4, 5
Each has a delay amount in the horizontal period, and the sample delay circuit 6,
, 17, and 17 each have a delay amount of one sampling period. The line delay circuits 2 to 5 and the sample delay circuits 6 to 17 simultaneously extract the data of a plurality of pixels included in a predetermined two-dimensional area of the television image. The sub-sampling according to this embodiment will be described with reference to FIG. FIG. 3 shows a partial region of one field of the input digital video signal. The horizontal pixel interval corresponds to the sampling period, and the vertical pixel interval corresponds to the line interval. Each of the symbols (Δ, ●, □, ×, ○) attached to each pixel in FIG. 3 represents a difference in interpolation processing. First, what is shown by ○ is 4
Represents basic pixels located every line and every four pixels. this
One out of every 16 pixels is always transmitted without being thinned out. Pixels other than the basic pixel are compared with the average value of the two pixels as described below, and are thinned out when the difference (prediction error) ε between the original pixel data and the average value is equal to or smaller than the threshold value TH. . Conversely, if the prediction error ε exceeds the threshold value TH, it is transmitted. Pixel represented by Δ: Compared with the average value of the pixel data located on the upper and lower lines, respectively. For example, the pixel a2 is compared with the average value [1/2 (a1 + a3)]. Pixels represented by ●: Compared with the average value of the pixels located two lines apart from each other by two lines. For example, the pixel a3 is compared with the average value [1/2 (a1 + a5)]. Pixel represented by □: Compared with the average value of pixels located two pixels apart on the left and right. For example, the pixel c3 is compared with the average value [1/2 (a3 + e3)]. Pixels represented by x: Compared with the average value of the adjacent pixels on the left and right. For example, the pixel b2 is compared with the average value [1/2 (a2 + c2)]. The output side of the sample delay circuit 11 in FIG. 2 is the target pixel, and the output data of the sample delay circuit 11 is supplied to the fifth input terminals of the selectors 18 and 19, the subtraction circuit 23, and the gate circuit 27. The selectors 18 and 19 have first to fifth five input terminals, and output input data respectively supplied to these five input terminals according to a selection signal from a terminal 20 synchronized with the sampling clock. Selectively output to the terminal. Output data of the sample delay circuit 7 is supplied to a first input terminal of the selector 18, and output data of the sample delay circuit 17 is supplied to a first input terminal of the selector 19. Therefore, when the target pixel is a pixel represented by △, the input data supplied to the first input terminals of the selectors 18 and 19 is selected. The output data of the sample delay circuits 9 and 15 are supplied to the second input terminals of the selectors 18 and 19, respectively. Therefore, when the target pixel is a pixel represented by ●, the input data supplied to the second input terminals of the selectors 18 and 19 is selected. Output data of the line delay circuit 3 and the sample delay circuit 13 are supplied to third input terminals of the selectors 18 and 19, respectively. Therefore, when the target pixel is a pixel represented by □, the input data supplied to the third input terminals of the selectors 18 and 19 is selected. Output data of the sample delay circuits 10 and 12 are supplied to fourth input terminals of the selectors 18 and 19, respectively. Therefore, when the pixel of interest is a pixel represented by x, the selector
Input data supplied to the fourth input terminals 18 and 19 are selected. Output data (pixel of interest) of the sample delay circuit 11 is supplied to the fifth input terminals of the selectors 18 and 19. Therefore, when the pixel of interest is a basic pixel represented by ○, both the selectors 18 and 19 Selects the basic pixel. The output data of the selectors 18 and 19 is supplied to the adder 21, and the output signal of the adder 21 is supplied to the 倍 multiplier 22. Therefore, the 1/2 circuit 21 generates the average value data of the two pixel data selected by the selectors 18 and 19, respectively. The average value data and the data of the pixel of interest from the sample delay circuit 11 are supplied to the subtraction circuit 23, and the difference data from the subtraction circuit 23 is converted into an absolute value in the absolute value conversion circuit 24. The output data of the absolute value conversion circuit 24 is supplied to a comparison circuit 25 and compared with a threshold value from a terminal 26. As described above, the output data of the absolute value conversion circuit 24 represents the prediction error ε generated when the interpolation is performed with the average value of the two pixels. When the prediction error ε is less than or equal to the threshold value TH, it means that the pixel may be thinned out, and therefore the control data (1 bit) from the comparison circuit 25 is set to “1”. On the other hand, when the prediction error ε exceeds the threshold value TH, it means that the reception side cannot perform good interpolation, and therefore the control data from the comparison circuit 25 is set to “0”. On / off of the gate circuit 27 is controlled by the control data. When the control data is "0", the gate circuit 27 is turned on and the original pixel data is taken out to the output terminal 28. When the control data is "1", the gate circuit 27 is turned off and the original pixel data is output to the output terminal 28. Not taken out. Further, the control data is taken out to the output terminal 29 and transmitted together with the sub-sampled video data. That is, a framing circuit (not shown) is connected to the output terminals 28 and 29 of the sub-sampling encoder, and in this framing circuit, pixel data and control data are synthesized and, in the case of transmitted pixel data, 9-bit data is transmitted per pixel, and in the case of pixel data to be decimated, only 1-bit control data is transmitted per pixel. As described above, subsampling is performed for each pixel depending on whether or not the prediction error ε is large. That is, transmission / thinning is adaptively controlled not for each block but for each pixel, which is the minimum unit. Further, when determining whether or not to perform the thinning-out by obtaining the prediction error ε, since the actual data is used without using the interpolation data, the repetition processing can be avoided and the real-time processing can be performed. The sub-sampling encoder 105 has the same configuration as the configuration shown in FIG. On the other hand, since the sub-sampling encoder 102 is provided to obtain the prediction error ε from the absolute value conversion circuit 24 in FIG. 2, the comparison circuit 25 and the gate circuit 27 are not necessary. c. Subsampling Decoder, FIG. 4 shows a subsampling decoder provided on the receiving side (reproducing side in the case of VTR or the like). In FIG. 4, the received digital video signal is supplied to an input terminal indicated by 31, and a sampling clock synchronized with the received data is supplied to an input terminal indicated by 32. Line delay circuits 33, 34, 35, 36 are connected in series to the input terminal 31. Input terminal 31 and line delay circuits 33-36
The serial-to-parallel conversion circuits 41, 42, 43,
44 and 45 are connected respectively. These series-to-parallel conversion circuits
41 to 45 sequentially receive the respective reception data of different lines by the sampling clock, and
By the output signal of 7, four pixel data are latched, and when the next pixel data is inputted, five pixel data are generated in parallel. Therefore, at a certain timing, the pixels shown in FIG. 3 are output from each of the serial-to-parallel conversion circuits 41 to 45. For example, four pixel data (a1, b1, c1, d1) from the line delay circuit 36 are latched by the serial → parallel conversion circuit 45, and five pixel data including the next pixel data e1 are simultaneously parallel → Parallel conversion circuit 45
Arising from Among the output signals of the serial-to-parallel conversion circuits 41 to 45, a5 to e5
And e1 to e4 are peripheral pixel data used for interpolation, and (4 × 4 = 16) pixels excluding these pixels are to be interpolated. 51, 52, 53 ... 68, 69
Indicate interpolation circuits and have the same configuration as each other. FIG. 5 specifically shows the configuration of the interpolation circuit 51. The interpolation circuit 51 has input terminals 91, 92 and 93 and an output terminal 94. Pixel data c5 (including 1-bit control data) to be interpolated is supplied to the input terminal 91, Terminals 92 and 93 have peripheral pixel data e5 necessary for interpolation.
And a5 are supplied. Pixel data from the input terminals 92 and 93 are supplied to the addition circuit 95, and the output signal of the addition circuit 95 is 1 /
It is supplied to the doubling circuit 96. The output signal of the halving circuit 96 is an interpolation value in the average value interpolation. The pixel data from the input terminal 91 and the output signal of the halving circuit 96 are supplied to the selector 97. The selector 97 is controlled by 1-bit control data included in the pixel data from the input terminal 92. When the control data is “1” (thinning-out), the selector 97 outputs the output of the half circuit 96. When the signal is selected and the control data is “0” (transmission), the selector 97 selects the pixel data from the input terminal 91. The output signal of the selector 97 is obtained at the output terminal 94. When the original pixel data is the thinned pixel, the interpolation values obtained from each of the interpolation circuits 51 to 69 are as follows. Interpolator 51: c5 → 1/2 (a5 + e5) Interpolator 52: e4 → 1/2 (e3 + e5) Interpolator 53: c4 → 1/2 (c3 + c5) Interpolator 54: a4 → 1/2 (a3 + a5) Interpolator 55: d4 → 1/2 (c4 + e4) Interpolator 56: b4 → 1/2 (a4 + c4) Interpolator 57: e3 → 1/2 (e1 + e5) Interpolator 58: a3 → 1/2 (a1 + a5) Interpolator 59: c3 → 1/2 (a3 + e3) Interpolator 60: d3 → 1/2 (c3 + e3) Interpolator 61: b3 → 1/2 (a3 + c3) Interpolator 62: e2 → 1/2 (e1 + e3) Interpolator 63: c2 → 1/2 (c1 + c3) Interpolator 64: a2 → 1/2 (a1 + a3) Interpolator 65: d2 → 1/2 (c2 + e2) Interpolator 66: b2 → 1/2 (a2 + c2) Interpolator 67: c1 → 1 / 2 (a1 + e1) Interpolator 68: d1 → 1/2 (c1 + e1) Interpolator 69: b1 → 1/2 (a1 + c1) Among the output signals from the above-described interpolators 51 to 69, (4 ×
The 16 pixel data included in the range 4) are supplied to the parallel-to-serial conversion circuits 71, 72, 73, 74 for every four pixels in the same line. In each of the parallel-to-serial conversion circuits 71 to 74, four pixel data after interpolation are latched by the output signal of the 1/4 frequency dividing circuit 37. The parallel-to-serial conversion circuits 71 to 74 output serial restored data in synchronization with the sampling clock from the terminal 32. The pixel data entered in FIG. 4 will of course be different at the time when the next clock from the 1/4 frequency divider circuit 37 is generated. That is, the pixel data a1, a2, a3, a4, and a5 of the serial-to-parallel conversion circuits 41 to 45 are pixel data e1, e2, and e5, respectively.
Replaced by 3, e4, e5. The restored data from the parallel-to-serial conversion circuit 71 is supplied to the line delay circuit 75, and the output data of the line delay circuit 75 and the restored data from the parallel-to-serial conversion circuit 72 are supplied to the selector 76. The output data of the selector 76 is a line delay circuit 77
The output data of the line delay circuit 77 and the restored data from the parallel-to-serial conversion circuit 73 are supplied to the selector 78. The output data of the selector 78 is supplied to the line delay circuit 79, and the output data of the line delay circuit 79 and the restored data from the parallel → serial conversion circuit 74 are supplied to the selector 80. These line delay circuits 75, 77, 79 and selectors 76, 78, 80
Is provided to convert the order of the restored data into the same order as that of the television scanning. The output terminal 81 of the selector 80 obtains the restored data in the order of the television scanning. d. Threshold value determination circuit FIG. 6 shows an example of the configuration of the threshold value determination circuit 104. In FIG. 6, the prediction error ε from the sub-sampling encoder 102 is supplied to the input terminal 110. The prediction error ε is (0 to 255) in the case of 8 bits.
Can take values up to. The prediction error ε is supplied to the frequency memory 112 via the selection circuit 111.
Is supplied as an address signal. Also, input terminal 113
The sampling clock from is supplied as a write / read (R / W) signal to the frequency memory 112 via the selection circuit 114. The frequency memory 112 performs a read modified write operation (an operation of performing a write operation immediately after a read operation with respect to the same address) based on the R / W signal. To the frequency memory 112, the data passed through the selection circuit 116 is input. The selection circuit 116 is supplied with the output signal of the addition circuit 117 and zero data. In addition circuit 117,
An output signal of the one generation circuit 118 and a read signal of the frequency memory 112 are supplied. The frequency memory 112 is in an initial state where the contents are all zero. When the prediction error ε is supplied as an address, the data at that address (in the initial state, zero) is read out, and The supplied output signal (+1) of the adder circuit 117 is written to the frequency memory 112. When the prediction error ε is supplied over the period of one field, data corresponding to the occurrence frequency of each value of the prediction error ε included in (0 to 255) is stored in each address of the frequency memory. It The threshold value TH is determined using the count table stored in the count memory 112. This threshold value determining operation is performed, for example, during a vertical blanking period. At the time of the threshold value determining operation, the counter 1
Nineteen output signals are selected. Counter 119 has input terminal 1
The clock signal from 15 generates an address that increments from 0 to 255. Further, the clock signal from the terminal 115 is selected by the selection circuit 114. Based on these addresses and clock signals, the frequency of each prediction error ε stored in the frequency memory 112 is read out, and this frequency is supplied to the integrating circuit 120. At the same time, the selection circuit 116 selects zero data, zero data is written to the frequency memory 112, and initialization for processing the next field is performed. The integrating circuit 120 integrates the frequencies from a prediction error ε of 0 toward 255. The output signal of this integrating circuit 120 is
The number of thinnings is shown. The output signal of the integrating circuit 120 is supplied to the comparing circuit 121. The required thinning-out number corresponding to the target rate is supplied to the comparison circuit 121, and the output signal of the integrating circuit 120 is compared with this required thinning-out number. When the output signal of the integrating circuit 120 becomes equal to or larger than the requested thinning-out number, the comparison circuit 121 causes a latch pulse. An output signal that increments from 0 to 255 of the counter 119 is supplied to the latch 122 and is latched by a latch pulse from the comparison circuit 121. The threshold value TH from the latch 122 is taken out to the output terminal 123. Since the frequency of the prediction error 0 includes the basic pixel, the value of the required decimation number is set in consideration of this sentence. e. Modifications The present invention can be applied to a case where the present invention is used in combination with another high efficiency code. The present applicant divides a screen into a number of blocks, obtains a dynamic range for each block, divides this dynamic range into a number of areas determined by a fixed or variable number of bits, and to which the pixel data after the minimum value removal belongs. A code (called ADRC) adapted to a dynamic range for transmitting a code signal corresponding to a region has been previously proposed. The ADRC may be combined with the present invention. Further, the control data in the present invention may be encoded by run-length encoding. [Effects of the Invention] According to the present invention, it is possible to make the amount of generated information constant in processing units, and it is effective to apply the present invention to, for example, a digital VTR. Further, according to the present invention, since a large-capacity buffer memory is not required, the circuit scale can be reduced. Further, the present invention has the following advantages of the variable density subsampling. The variable density sub-sampling can prevent conspicuous deterioration of restored pixels in block units, unlike a method in which sub-sampling patterns are switched in block units. In addition, sub-sampling having very good adaptability to image features is performed, and the restored image quality can be improved. Furthermore, it is possible to perform real-time processing, which is suitable for processing moving images. Furthermore, even if an error occurs, the error is less likely to propagate.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a sub-sampling encoder, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a block diagram of a sub-sampling decoder, FIG. 5 is a block diagram showing an example of a specific configuration of an interpolation circuit provided in the sub-sampling decoder, and FIG. It is a block diagram of an example of a threshold value determination circuit. Description of main symbols in the drawings 101: input terminal, 2 to 5: line delay circuit, 6 to 17: sample delay circuit, 18, 19: selector, 23: subtraction circuit, 25: comparison circuit, 27: gate circuit, 28 , 29: output terminal, 102, 105: subsampling encoder, 112: frequency memory.

Claims (1)

(57) [Claims] With respect to the second pixel other than the first pixel regularly located in the plurality of pixels having a temporal or spatial arrangement,
A plurality of the first or second pixels around each of the second pixels
Means for predicting the interpolation using the pixels of the above; detecting the prediction error between the obtained data and the original data of the second pixel by the interpolation, and according to the magnitude of the prediction error Means for generating a control code; and means for transmitting the data of the first pixel, and transmitting / decimating the original data of the second pixel in accordance with the control code to form transmission data. In the high-efficiency coding apparatus provided, a means for forming the prediction error for all the pixels in the processing unit in advance, and a means for counting the frequency of the absolute value of the prediction error formed for each processing unit Means for determining a threshold value for generating the control code so that the output data is equal to or less than a required rate by using the frequency total table. High efficiency encoder.