JP2888523B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus capable of high-efficiency encoding / decoding. [Prior Art] Conventionally, as this type of image information transmission method, for example, a high-efficiency encoding method of a television signal has been known.
In the television signal high-efficiency coding method, a so-called MIN-MAX method for reducing the average number of bits per pixel is employed because of the necessity of narrowing the transmission band. Hereafter, this MI
The N-MAX method will be described. Television signals have a strong spatiotemporal correlation.
When an image is divided into small blocks, each block often has only a small dynamic range due to local correlation. Therefore, very efficient compression can be performed by obtaining a dynamic range in each block and adaptively encoding. Therefore, this encoding will be specifically described with reference to the drawings. FIG. 3 is a diagram showing a schematic configuration of an image information transmission system as an example of the prior art. Reference numeral 101 in the figure denotes an input terminal, which samples a raster-scanned analog image signal such as a television signal at a predetermined frequency, and
Digital image data digitized into n bits of data per sample is input. The digital image data of ²ⁿ gradations is supplied to the pixel block dividing circuit 102. FIG. 4 is a diagram showing a state in which all pixel data for one screen is divided into pixel blocks. Pixel block division circuit 102
In FIG. 4, all the pixel data for one screen is temporarily stored in a memory or the like, and as shown in FIG. 4, 1 pixel in the horizontal direction (hereinafter, referred to as H direction) and 1 pixel in the vertical direction (hereinafter, referred to as V direction). )
The pixel data is read in units of a pixel block composed of (1 × m) pixels of m pixels. That is, the output is performed for each data of each pixel block. FIG. 5 shows the configuration of each pixel block. In the figure, D _1,1 ~
D _{m, l} indicates each pixel data. Image data output from the pixel block division circuit 102 is input to the maximum value detection unit 103, the minimum value detection unit 140, and the timing adjustment unit 105. As a result, all pixel data (D
_{1,1 to} D _m, ), those having the maximum value (D _max ) and those having the minimum value (D _min ) are detected by the detection units 103 and 104,
Is output. On the other hand, in the timing adjustment unit 105, the maximum value detection unit 1
03 and the minimum value detection unit 104 delays all the pixel data by the time required to detect D _max and D _min, and transmits the pixel data to the division value conversion unit 106 in a predetermined order for each pixel block. Send out. For example, D _1,1 , D
_2,1 , _D3,1 , ..., _{Dm, 1} , _D1,2 , ..., _{Dm, 2} , ...,
D1 _{, (l-1)} , ..., _{Dm, (l-1)} , D1 _{, l} , ..., _{Dm, l} . In this way, all pixel data (D
_{1,1 to} D _{m, l} ) and their maximum (D _max ) and minimum (D _max )
_min) is input to the divided value converting unit 106, for each pixel data, D _max and D 2 ^k divided division code of k bits is compared with quantization levels between _{min (Δ 1,1 ~Δ m, l} ) get Here, k is an integer smaller than n, and the state of quantization is shown in FIG. 6 (a). As shown in FIG. 6 (a), Δ _{i, j} is k-bit 2
Output as value sign. The k-bit division code Δi _{, j} and the n-bit D _max and D _min obtained in this manner are converted into parallel-serial (PS) converters 107, 107 ', 10 respectively.
7 ", the data is converted into serial data as shown in Fig. 7 in the data selector 108. Note that Fig. 7 shows transmission data for one pixel block. The stored data is stored in the first-in first-out memory (FIFO memory) 109
, A time axis processing is performed so that a constant data transmission rate is obtained, a synchronization signal is further added by a synchronization addition section 110, and a transmission path (for example, a magnetic recording and reproducing system such as a VTR) is output from an output terminal 111.
Sent to Here, the addition of the synchronization signal may be performed for each pixel block or for each of a plurality of pixel blocks.
Note that the operation timing of each of the above-described units is determined based on a timing signal output from the timing control unit 112. FIG. 8 is a block diagram showing a schematic configuration of a receiving side corresponding to the data transmitting side shown in FIG. In FIG. 8, reference numeral 121 denotes a terminal to which the above-described transmission data which has been encoded at high efficiency at the transmission side is input. The synchronization signal in the input transmission data is separated by the synchronization separation unit 122 and supplied to the timing control unit 123. The timing control unit determines the operation timing of each unit on the receiving side based on the synchronization signal. On the other hand, in the data selector 124, n-bit data D _max and D _{min in} the transmission data described above and each pixel data are
It is distributed to a code Δi _{, j} which is k-bit quantized between _max and D _min . These are serial-parallel (S-
P) The data is converted into parallel data by the converters 125 and 125 '. The maximum value data D _max and the minimum value data D _{min in} each pixel block converted into parallel data by the SP converter 125
Are latched by the latch circuits 126 and 127, respectively, and the latched maximum value data _Dmax and minimum value data _Dmin are output to the divided value inverse conversion unit 128, respectively. On the other hand, the division code Δi _{, j} relating to each pixel data in each pixel block is output by the SP converter 125 ′ in the above-described predetermined order, and is supplied to the division value inverse conversion unit 128. FIG. 6 (b) is a diagram showing how the representative value data D ′ _{i, j} relating to the original pixel data is decoded from the division codes Δ _{i, j} and D _max , D _min . For example, D _max , D _min
^Is set in the middle of each of the ^2k- divided quantization levels. The n-bit representative value data (D ′ _{1,1 to} D ′ _{m, l} ) obtained by the division value inverse conversion unit 128 in this manner is output for each pixel block in the order described above. The scan converter unit 129 converts the output data of the divided value inverse conversion unit 128 into an order corresponding to the raster scan, and outputs the converted data to the output terminal 130 as decoded image data. [Problems to be Solved by the Invention] However, in the above conventional example, the correlation only in the two-dimensional space of the image is used. Therefore, when transmitting a still image or an image with little motion, the transmission information has a redundancy in the time axis, and the same information is repeatedly transmitted, which has a disadvantage that the transmission efficiency is deteriorated. Accordingly, an object of the present invention is to provide an image processing apparatus capable of efficiently encoding a high-quality image signal in view of the above points. [Means for Solving the Problems] In order to achieve the above object, an image processing apparatus according to the present invention divides a plurality of sample values corresponding to an image signal for one screen into blocks by a predetermined number of sample values. Blocking means to
The block-processed image signal is subjected to encoding processing by the block unit using a difference signal obtained by subtracting a prediction value from the block-formed image signal, and an encoding code obtained in the block unit by the encoding process is obtained. A first encoding mode to be output, and perform an encoding process on the block-by-block image signal without using the difference signal, and obtain an encoded code obtained in the block unit by the encoding process. Encoding means having a second encoding mode to output, motion detecting means for detecting the motion of the blocked image signal based on the block unit of the encoding process, and the motion detecting means And selecting means for selecting the encoding mode in accordance with the output of. EXAMPLES Hereinafter, the present invention will be described using one example of the present invention. FIG. 1 and FIG. 2 are diagrams showing a schematic configuration of an image information transmission system as one embodiment of the present invention. Here, FIG. 1 shows a transmission system, and FIG. 2 shows a reception system. In addition,
1 and 2, the same components as those in FIGS. 3 and 8 are denoted by the same reference numerals, and detailed description is omitted. In the following description, only portions different from the conventional example will be described. In FIG. 1, 1 is a subtractor for subtracting the output of the frame memory 10 from the output of the pixel block dividing circuit 102, 2 is a maximum value detector for finding the maximum value of the output of the subtracter 1, and 3 is also for finding the minimum value. A minimum value detection unit, 4 is a timing adjustment unit that adjusts the transmission time from the maximum value detection unit 2 to the divided value conversion unit 5, and 6 is a motion that determines a motion from the outputs of the maximum value detection unit 2 and the minimum value detection unit 3. A detection unit 7, a switch for switching the output of each of the above units 2, 3, 5, 8 an adder for adding the output of the divided value inverse conversion unit 128 and the frame memory 10, 9 an addition as an input to the frame memory 10 A switching unit for switching the output of the pixel unit 8 / the output of the pixel block division circuit 102, 10 is the frame memory for storing the signal from the switching unit 9, 11 is a maximum value detection unit 103, a minimum value detection unit 104, and a division value conversion unit.
106 is a switch for switching each output, 12 is a PS converter 13
13 is a P / S converter for converting the signal from the switch 12 from parallel to serial and adding the output of the motion detection unit 6, and 14 is a timing control for controlling the timing of each circuit. Department. In FIG. 2, reference numeral 20 denotes an SP converter for serial-to-parallel conversion of a signal from the input unit 121, reference numeral 21 denotes an adder for adding the output of the division value inverse conversion unit 128 and the output of the frame memory 23, and reference numeral 22 denotes a scan. A switch for selecting the output of the split value inverse converter 128 or the adder 21 as an input to the converter 129, 23 is a frame memory for storing the signal from the switch 22, and 24 is a motion signal from the output of the SP converter 20. 25 is a timing control unit that controls the timing of each circuit from the output of the synchronization separation unit 122. Next, the operation of the transmission system shown in FIG. 1 will be described. The image digital data input from the input terminal 101 in FIG. 1 is rearranged in block units by a pixel block dividing circuit 102, and only a signal processing unit using the frame difference DPCM and the MIN-MAX method and the MIN-MAX method are used. And a signal processing unit that uses The signal processing unit has a frame memory 10, finds a difference value between the previous frame and the current frame by the subtractor 1, and calculates the obtained value as a maximum value detection unit 2, a minimum value detection unit 3,
Re-encoding is performed by a MIN-MAX method encoder including a timing adjustment unit 4, a division value conversion unit 5, and a switch 7. The re-encoded signal is decoded by the inverse split value converter 128 and added to the output of the frame memory 10 by the adder 8. Further, new pixel data is rewritten to the frame memory 10 via the switch 9. By this decoding / rewriting operation, the contents of the frame memory can be updated, and the contents can be matched with the contents of the receiving frame memory. Through these signal processes, the inter-frame difference DPCM and the MIN-MAX encoding are performed. Motion detection is obtained by calculating the difference between the maximum value detection unit 2 and the minimum value detection unit 3 by the motion detection unit 6 and comparing the obtained value with a threshold value. If this threshold value is increased, transmission efficiency is improved, but in a reproduced image, image quality deterioration of a moving image, jerkiness, and the like occur. Conversely, when the value is reduced, the image quality degradation and the like are improved, but the transmission efficiency is reduced. Therefore, it is necessary to set an appropriate value in consideration of both. Next, the signal processing only by the MIN-MAX method is performed by the MIN-MAX method encoder including the maximum value detection unit 103, the minimum value detection unit 104, the timing adjustment unit 105, the division value conversion unit 106, and the switch 11. Is done. These two signal processing outputs are switched on a block basis by the output of the motion detector 6. If the image is close to a still image, the switching unit 12 performs signal processing using the frame difference DPCM and the MIN-MAX method, and if the image is a moving image, performs signal processing using only the MIN-MAX method. At the same time as this switching, the switcher 9 switches the input to the frame memory 10 from the DPCM, MIN-MAX method decoded signal to the signal of the pixel block dividing circuit 102 at the time of moving image, so that the contents of the frame memory 10 (the error accumulation value by the DPCM) ) Can be refreshed to the correct value. The PS (parallel-serial) converter 13 converts the input parallel data into serial data, and further adds one bit of motion data for each block from the motion detector 6 and outputs it. Hereinafter, processing and output are performed in the same manner as in the conventional example. Next, the operation of the receiving system shown in FIG. 2 will be described. The above-described transmission data that has been highly efficient encoded on the transmission side is input to the input terminal 121 of FIG. The synchronization signal in the input data is separated by the synchronization separation 122 and supplied to the timing control unit 25. The timing control unit 25 determines the operation timing of each unit based on the synchronization signal. On the other hand, in the SP (serial-parallel) converter 20,
Converts the input serial data to parallel data. The motion information is separated by the motion signal separation unit 24.
Each pixel block data converted into parallel data is converted into a maximum value latch circuit 126, a minimum value latch circuit 127, and a divided value inverse conversion unit 12.
Decoded by 8. In the case of a moving image, the switch 22 outputs the decoded signal to the scan converter 129 according to the output of the motion signal separation unit 24.
Enter directly into. At the time of a still image, the image is added to the output of the frame memory 23 by the adder 21 and input. The same signal as that of the scan converter 129 is input to the frame memory 23. By the operation of the frame memory 23, the frame difference value transmitted at the time of the still image is decoded into the original pixel data. Hereinafter, processing is performed in the same manner as in the conventional example. Here, the fact that the number of transmission bits is reduced by using the inter-frame difference DPCM and the MIN-MAX method together will be described. If the inter-frame difference of the image data is calculated using the redundancy of the time axis of the image, the dynamic range of the obtained data decreases. The stronger the redundancy, that is, the more the still image, the stronger this tendency is. According to the motion detection unit of the present embodiment, the condition for determining a still image is the correlation of the time axis (the former).
And a two-dimensional space correlation (the latter).
That is, when the correlation of the time axis (the former) is very strong, the correlation of the two-dimensional space (the latter) may be moderate, and conversely, when the former is weak, the latter is very strong. It is understood that the number of effective bits under this condition may be a very small value. The required number of bits of the maximum value / minimum value is obtained based on the above conditions, and the required number of bits of the divided value conversion unit is obtained by the threshold value of the motion detection unit. As is clear from the above explanation, the difference between frames DPCM and
When the MIN-MAX method is used together, the data compression ratio is greatly improved. For example, original data n = 8, l = m in each pixel block
= 3 In the static mode, if n = 3 and k = 2, the original data in each pixel block is (8 × 3 × 3 =) 72 bits, and the transmission data is (3 × 2 + 2 × 3 × 3 =) 24 bits. , 1/3
Is obtained. In the image information transmission system described above, when the amount of information is small, such as when the image is a still image, the compression rate is increased,
For videos, by adapting to the normal compression ratio,
Transmission efficiency can be improved without transmitting excessive information. In the above-described embodiment, only the case where raster-scanned image data is transmitted has been described. However, when image information is transmitted, the present invention is applicable regardless of the signal form of the original signal. . In this case, it is only necessary to appropriately change the configurations of the pixel block dividing circuit 102, the scan converter 129, and the like. [Effects of the Invention] As described above, according to the present invention, an image signal of one screen is divided into a plurality of blocks, and block coding is performed using a difference signal in accordance with the motion of the block image signal. Since the coding mode and the coding mode for performing block coding without using the difference signal are selected and coding is performed, and the addition control of the prediction value is performed in accordance with the motion of the image signal, a high-quality image is obtained. Signals can be efficiently encoded. Further, in the present invention, since the motion of the image signal is performed with reference to the block which is a unit of the encoding process, the block dividing circuit can be shared between the motion detection process and the encoding process, and the circuit scale is reduced. can do. further,
Since the motion detection processing and the encoding mode selection processing are completely synchronized, encoding can be performed more efficiently.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of a transmitting side of an image information transmission system as one embodiment of the present invention, and FIG. 2 is a receiving side of the image information transmitting system as one embodiment of the present invention. FIG. 3 is a schematic configuration diagram of a transmitting side of an image information transmission system according to the prior art, FIG. 4 is a diagram showing how all image data is divided into pixel block groups, and FIG. FIG. 6 (a) shows the conversion characteristics of the divided value converter in FIG. 3, and FIG. 6 (b) shows the conversion characteristics of the divided value inverse converter in FIG. FIG. 7 is a diagram for explaining data to be transmitted, and FIG. 8 is a diagram showing a schematic configuration of a receiving side corresponding to a transmitting side of the image information transmission system shown in FIG. Reference Signs List 1 subtractor, 2,103 maximum value detection unit, 3,104 minimum value detection unit, 4,105 timing adjustment unit, 5,106 division value conversion unit
6: motion detector, 7, 9, 11, 12: switcher, 8: adder, 10: frame memory, 13: parallel-serial converter, 14: timing controller, 102: pixel block dividing circuit, 128 ... Divided value inverse transform unit.

Claims (1)

(57) [Claims] Blocking means for dividing a plurality of sample values corresponding to one screen of image signal into blocks for each predetermined number of sample values; and the block signal is divided by a difference signal obtained by subtracting a predicted value from the blocked image signal. A first encoding mode for performing an encoding process on the image signal obtained in the block unit and outputting an encoded code obtained in the block unit by the encoding process, and the block process is performed without using the difference signal. Encoding means for performing an encoding process on the obtained image signal in units of blocks, and a second encoding mode for outputting an encoded code obtained in units of blocks by the encoding process; and A motion detection unit that detects a motion of an image signal based on the block unit of the encoding process; and the encoding according to an output of the motion detection unit. The image processing apparatus characterized by having a selection means for selecting over de.