JP2658309B2 - Jet cooling semiconductor device - Google Patents
Jet cooling semiconductor deviceInfo
- Publication number
- JP2658309B2 JP2658309B2 JP63309136A JP30913688A JP2658309B2 JP 2658309 B2 JP2658309 B2 JP 2658309B2 JP 63309136 A JP63309136 A JP 63309136A JP 30913688 A JP30913688 A JP 30913688A JP 2658309 B2 JP2658309 B2 JP 2658309B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- cooling
- semiconductor device
- carrier
- base portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001816 cooling Methods 0.000 title claims description 23
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000007788 liquid Substances 0.000 claims description 19
- 239000002826 coolant Substances 0.000 claims description 11
- 238000007599 discharging Methods 0.000 claims description 3
- 238000007667 floating Methods 0.000 claims description 3
- 239000003507 refrigerant Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 239000000110 cooling liquid Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔概要〕 発熱量の大きい半導体チップを搭載した噴流冷却半導
体装置の構造に関し， チップ中央部と周辺部との熱伝達効率の差を低減し，
チップ内の温度むらの発生を抑制して冷却効率の向上を
目的とし， チップの搭載位置に冷媒液体の排出孔を有する基底部
及びチップ搭載側において該基底部の周囲に設けられた
壁を有するチップキャリアと，該チップキャリアに該基
底部より浮かして搭載されたチップと，該冷媒液体が該
チップに吹きつけられ，該壁により該チップの両面を通
過する流路を形成して該排出孔より排出される手段とを
有するように構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding the structure of a jet cooling semiconductor device on which a semiconductor chip having a large heat value is mounted, the difference in heat transfer efficiency between the central portion and the peripheral portion of the chip is reduced.
For the purpose of improving the cooling efficiency by suppressing the temperature unevenness in the chip, it has a base with a coolant liquid discharge hole at the chip mounting position and a wall provided around the base on the chip mounting side A chip carrier, a chip mounted on the chip carrier floating from the base portion, and a cooling liquid sprayed on the chip, the wall forming a flow path passing through both sides of the chip, and forming the discharge hole. And a means to be more discharged.
本発明は発熱量の大きい半導体チップを搭載した噴流
冷却半導体装置の構造に関する。The present invention relates to a structure of a jet cooling semiconductor device on which a semiconductor chip having a large calorific value is mounted.
この半導体装置は，冷媒液体の噴流により冷却される
VLSIチップを高密度に実装した回路基板に適用できる。This semiconductor device is cooled by the jet of the coolant liquid
It can be applied to circuit boards on which VLSI chips are mounted at high density.
大型汎用コンピュータやスーパーコンピュータに使用
される半導体素子は高速化に伴う消費電力の増大は著し
く，又，素子の高速性能を生かすための高密度実装によ
り，回路基板の発熱密度の上昇は止まるところを知らな
い。Semiconductor devices used in large general-purpose computers and supercomputers have a remarkable increase in power consumption due to higher speeds, and the rise in heat generation density of circuit boards has stopped due to high-density mounting to take advantage of the high-speed performance of the devices. Do not know.
このために，強制対流沸騰冷却の一種である噴流冷却
のような高効率の冷却方法を適用して，冷却能力の大幅
な増大を行う必要がある。For this reason, it is necessary to significantly increase the cooling capacity by applying a high-efficiency cooling method such as jet cooling, which is a kind of forced convection boiling cooling.
従来の噴流冷却を適用した半導体装置は，基板に高密
度に搭載したチップにノズルから冷媒液体を噴出して冷
却するものであるが，冷媒液体はチップ中央部に垂直に
当たって，撥ね返るような流れをとっていた。In conventional semiconductor devices to which jet cooling is applied, cooling liquid is ejected from a nozzle to a chip mounted on a substrate at high density to cool it. However, the cooling liquid flows perpendicularly to the center of the chip and rebounds. Was taking.
このため，チップ中央部では冷媒液体が強く当たって
熱交換効率が高いが，チップの周辺部では流れが停滞し
て熱交換効率が低く，チップ中央部と周辺部との熱伝達
効率の差からチップに温度むらが生ずる欠点があった。As a result, the heat exchange efficiency is high due to the strong contact of the coolant liquid at the center of the chip, but the flow is stagnant at the periphery of the chip and the heat exchange efficiency is low. There is a disadvantage that the chip has uneven temperature.
又，フリップチップ実装のように，チップを微細なは
んだバンブを介して，基板から浮かせて接合する場合に
は，回路基板に対してチップの裏面からしか熱交換でき
ないため冷却能力の点で不利であった。Also, when a chip is floated from a substrate via a fine solder bump as in flip-chip mounting, it is disadvantageous in terms of cooling capacity because heat can be exchanged only from the back surface of the chip with the circuit board. there were.
本発明は，従来の噴流冷却を適用した場合に生ずるチ
ップ中央部と周辺部との熱伝達効率の差を低減し，チッ
プ内の温度むらの発生を抑制して冷却効率の向上を目的
とする。An object of the present invention is to improve the cooling efficiency by reducing the difference in heat transfer efficiency between the central part and the peripheral part of the chip, which occurs when conventional jet cooling is applied, and suppressing the occurrence of temperature unevenness in the chip. .
更に，フリップチップ実装のように基板と隙間のある
接合を行ったチップについては，チップの両面からの冷
却を可能にして，冷却効率の向上をはかる。Further, for a chip that has been bonded to a substrate with a gap, such as flip-chip mounting, cooling from both sides of the chip is enabled to improve the cooling efficiency.
上記課題の解決は，チップの搭載位置に冷媒液体の排
出孔を有する基底部及びチップ搭載側において該基底部
の周囲に設けられた壁を有するチップキャリアと，該チ
ップキャリアに該基底部より浮かして搭載されたチップ
と，該冷媒液体が該チップに吹きつけられ，該壁により
該チップの両面を通過する流路を形成して該排出孔より
排出される手段とを有する噴流冷却半導体装置により達
成される。In order to solve the above-mentioned problems, a chip carrier having a base portion having a coolant liquid discharge hole at a chip mounting position and a wall provided around the base portion on the chip mounting side, and floating on the chip carrier from the base portion. A jet cooling semiconductor device having a chip mounted thereon, and means for spraying the coolant liquid onto the chip, forming a flow path passing through both surfaces of the chip by the wall, and discharging from the discharge hole. Achieved.
第１図は本発明の原理図で，チップをフリップチップ
接合により搭載したチップキャリアの断面図である。FIG. 1 is a principle view of the present invention, and is a sectional view of a chip carrier on which a chip is mounted by flip chip bonding.
本発明では，チップキャリア２は，表面にチップ１を
載せて接合する基底部21と，搭載したチップの周囲にチ
ップ面に対して略垂直な壁22とを有し，基底部21の裏面
にははんだバンプ６等と接続する接続ピン7Aが埋め込ま
れている。又，基底部21のチップ搭載位置の略中央には
冷媒液体の排出孔23が開けられている。In the present invention, the chip carrier 2 has a base portion 21 on which the chip 1 is mounted and bonded on the front surface, and a wall 22 substantially perpendicular to the chip surface around the mounted chip. Are embedded with connection pins 7A for connection to the solder bumps 6 and the like. At the substantially center of the chip mounting position of the base 21, a refrigerant liquid discharge hole 23 is formed.
チップキャリア２にはんだバンプ６を介してチップ１
を搭載して冷媒液体８を吹き付けると，冷媒液体の流れ
はまずチップに当たって直角に折れ曲がり，更にチップ
キャリアの周囲の壁に当たってチップと基板との間に回
り込む。冷媒液体がチップの両面を高速で対流すること
になるため，チップの中央部だけでなく，周辺部の熱交
換効率も向上し，チップ表面の熱交換が均一化する。Chip 1 on chip carrier 2 via solder bumps 6
Is mounted and the refrigerant liquid 8 is sprayed, the flow of the refrigerant liquid first hits the chip and bends at a right angle, and further hits the peripheral wall of the chip carrier and goes around between the chip and the substrate. Since the coolant liquid convects at high speed on both sides of the chip, the heat exchange efficiency is improved not only in the central part of the chip but also in the peripheral part, and the heat exchange on the chip surface is made uniform.
このように，フリップチップ実装の場合はチップと基
底部間に隙間があり，この隙間に面する発熱源であるチ
ップ表面に冷媒液体が循環するので冷却能力は向上す
る。As described above, in the case of flip-chip mounting, there is a gap between the chip and the base portion, and the cooling liquid is circulated on the chip surface which is a heat source facing the gap, so that the cooling capacity is improved.
第２図は本発明の実装の一実施例を説明する断面図で
ある。FIG. 2 is a sectional view for explaining one embodiment of the mounting of the present invention.
図において，中央に直径2mmφの孔を開けた13mm角，
高さ6mmのアルミナ製のチップキャリア２にLSIチップ１
をはんだバンプ６を介してフリップチップ接合して搭載
し,150mm角の回路基板３に10×10個搭載した。In the figure, a 13 mm square with a 2 mm diameter hole in the center,
LSI chip 1 on alumina chip carrier 2 of 6 mm height
Were mounted by flip-chip bonding via solder bumps 6, and 10 × 10 were mounted on a 150 mm square circuit board 3.
回路基板３の裏面には接続ピン7A等と接続するI/Oピ
ン７が埋め込まれている。I / O pins 7 connected to the connection pins 7A and the like are embedded on the back surface of the circuit board 3.
それぞれのチップ１に対応して冷媒液体を噴出させる
ためのノズル５を配置した冷却容器４にこの回路基板３
を封入して，それぞれのノズル５に熱交換器とポンプを
介して冷媒液体８を流速2m/sで強制循環した。The circuit board 3 is mounted on a cooling container 4 in which a nozzle 5 for ejecting a coolant liquid is arranged corresponding to each chip 1.
And the refrigerant liquid 8 was forcibly circulated through each nozzle 5 at a flow rate of 2 m / s via a heat exchanger and a pump.
ここで，冷媒液体は弗化炭素（C6F14等）を用いる。Here, the refrigerant liquid uses carbon fluoride (such as C 6 F 14 ).
チップ１に電力を印加すると冷媒液体８は沸騰を始
め，チップ１は気化熱を奪われて冷却される。冷媒液体
はチップに当たって流れの向きを直角に変えてチップと
平行になり，さらにチップキャリア２の壁22に当たって
チップと基板との間に回り込みチップの下側に開けられ
た排出孔23から基板３へ排出されチップキャリアの外側
を通って流路に戻る。When electric power is applied to the chip 1, the refrigerant liquid 8 starts to boil, and the chip 1 is deprived of heat of vaporization and cooled. The coolant liquid strikes the chip, changes the direction of flow to a right angle, becomes parallel to the chip, and further strikes the wall 22 of the chip carrier 2, wraps between the chip and the substrate, and is discharged from the discharge hole 23 formed below the chip to the substrate 3. It is discharged and returns to the flow path through the outside of the chip carrier.
従来例ではノズルから吹き付けた冷媒液体がチップ面
で撥ね返っていたため，チップの単位面積当たりの冷却
能力が60W/cm2であったものが，同一条件で実施例では
約２倍の110W/cm2に向上した。In the conventional example, the cooling liquid per unit area of the chip was 60 W / cm 2 because the coolant liquid sprayed from the nozzle was repelled on the chip surface. Improved to 2 .
実施例においてはチップと基板間に隙間のある実装例
としてフリップチップ実装について説明したが，上記隙
間のできるその他の実装の場合にも本発明は適用でき
る。In the embodiment, the flip-chip mounting has been described as an example of mounting with a gap between the chip and the substrate. However, the present invention can be applied to other mounting with the above-mentioned gap.
以上説明したように本発明によれば，従来の噴流冷却
を適用した場合に生ずるチップ中央部と周辺部間の温度
むらの発生を制御して冷却効率を向上することができ
る。As described above, according to the present invention, it is possible to improve the cooling efficiency by controlling the occurrence of temperature unevenness between the central portion and the peripheral portion of the chip, which occurs when the conventional jet cooling is applied.
即ち，フリップチップ実装のように基板と隙間のある
接合を行ったチップについては，チップの両面からの冷
却を可能にして，冷却効率の向上をはかれる。That is, for a chip that has been bonded to the substrate with a gap, such as flip-chip mounting, cooling can be performed from both sides of the chip, thereby improving the cooling efficiency.
第１図は本発明の原理図で，チップをフリップチップ接
合により搭載したチップキャリアの断面図， 第２図は本発明の実装の一実施例を説明する断面図であ
る。 図において， １はチップ， ２はチップキャリア， 21はチップキャリアの基底部， 22はチップキャリアの周囲に設けられた壁， 23は基底部に設けられた冷媒液体の排出孔， ３は回路基板， ４は冷却容器， ５はノズル， ６ははんだバンプ， ７はI/Oピン， ８は冷媒液体 である。FIG. 1 is a principle view of the present invention, and is a cross-sectional view of a chip carrier on which a chip is mounted by flip chip bonding, and FIG. 2 is a cross-sectional view for explaining an embodiment of the mounting of the present invention. In the drawing, 1 is a chip, 2 is a chip carrier, 21 is a base of the chip carrier, 22 is a wall provided around the chip carrier, 23 is a refrigerant liquid discharge hole provided on the base, and 3 is a circuit board. , 4 are cooling vessels, 5 is a nozzle, 6 is a solder bump, 7 is an I / O pin, and 8 is a refrigerant liquid.
Claims (1)
する基底部及びチップ搭載側において該基底部の周囲に
設けられた壁を有するチップキャリアと，該チップキャ
リアに該基底部より浮かして搭載されたチップと，該冷
媒液体が該チップに吹きつけられ，該壁により該チップ
の両面を通過する流路を形成して該排出孔より排出され
る手段とを有することを特徴する噴流冷却半導体装置。1. A chip carrier having a base portion having a coolant liquid discharge hole at a chip mounting position and a wall provided around the base portion on the chip mounting side, and a chip carrier floating above the chip carrier from the base portion. Jet cooling, comprising: a mounted chip; and means for discharging the coolant liquid to the chip, forming a flow path through both surfaces of the chip by the wall, and discharging from the discharge hole. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63309136A JP2658309B2 (en) | 1988-12-07 | 1988-12-07 | Jet cooling semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63309136A JP2658309B2 (en) | 1988-12-07 | 1988-12-07 | Jet cooling semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02155258A JPH02155258A (en) | 1990-06-14 |
| JP2658309B2 true JP2658309B2 (en) | 1997-09-30 |
Family
ID=17989333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63309136A Expired - Lifetime JP2658309B2 (en) | 1988-12-07 | 1988-12-07 | Jet cooling semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2658309B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2053055C (en) * | 1990-10-11 | 1997-02-25 | Tsukasa Mizuno | Liquid cooling system for lsi packages |
| CA2070062C (en) * | 1991-05-30 | 1997-01-07 | Hironobu Ikeda | Cooling structure for integrated circuits |
| JP2995590B2 (en) * | 1991-06-26 | 1999-12-27 | 株式会社日立製作所 | Semiconductor cooling device |
| JP2748732B2 (en) * | 1991-07-19 | 1998-05-13 | 日本電気株式会社 | Liquid refrigerant circulation system |
| WO2009009516A2 (en) * | 2007-07-12 | 2009-01-15 | Honeywell International Inc. | Nano shower for chip-scale cooling |
-
1988
- 1988-12-07 JP JP63309136A patent/JP2658309B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02155258A (en) | 1990-06-14 |
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