JP2634492B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents
Manufacturing method of nonvolatile semiconductor memory deviceInfo
- Publication number
- JP2634492B2 JP2634492B2 JP657291A JP657291A JP2634492B2 JP 2634492 B2 JP2634492 B2 JP 2634492B2 JP 657291 A JP657291 A JP 657291A JP 657291 A JP657291 A JP 657291A JP 2634492 B2 JP2634492 B2 JP 2634492B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate insulating
- forming
- window
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 104
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000003599 detergent Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、不揮発性半導体記憶装
置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device.
【0002】[0002]
【従来の技術】電気的書き込み消去が可能なEEPRO
Mの1つとしてフローティングゲート型の電界効果トラ
ンジスタを利用した不揮発性半導体記憶装置が知られて
いる。この不揮発性半導体記憶装置は、Si基板の表面
上に設けられたソース領域、ドレイン領域及び両領域に
挟まれたチャネル領域上に第1ゲート絶縁膜を形成し、
ドレイン領域上の第1ゲート絶縁膜をエッチングにより
一部除去してSi基板表面を一部露出させ、露出したS
i基板表面に薄い第2ゲート絶縁膜を形成し、第1及び
第2ゲート絶縁膜の上にフローティングゲート、絶縁膜
及びコントロールゲートを順次形成したものであって、
ドレイン領域上の薄い第2ゲート絶縁膜を介してフロー
ティングゲートに電荷のトンネリング注入を行なうこと
によって該フローティングゲートに電荷を蓄積させ、ト
ランジスタの閾値電圧を変化させて情報を記憶させるこ
とを原理としている(例えばGiora Yaron
et.al. ISSCC 82,P108参照)。2. Description of the Related Art Electrically erasable EEPRO
As one of the M, a nonvolatile semiconductor memory device using a floating gate type field effect transistor is known. In this nonvolatile semiconductor memory device, a first gate insulating film is formed on a source region, a drain region, and a channel region sandwiched between both regions provided on a surface of a Si substrate,
The first gate insulating film on the drain region is partially removed by etching to partially expose the surface of the Si substrate, and the exposed S
i to form a thin second gate insulating film on the substrate surface, a floating gate, it is one obtained by successively forming an insulating film and a control gate over the first and <br/> second gate insulating film,
The principle is that charges are accumulated in the floating gate by injecting charges into the floating gate through a thin second gate insulating film on the drain region, and the threshold voltage of the transistor is changed to store information. (Eg Giora Yaron
et. al. ISSCC 82, P108).
【0003】図12及び図13は、従来の不揮発性半導
体記憶装置の製造方法の工程の一部を説明する断面図で
ある。FIGS. 12 and 13 are cross-sectional views illustrating a part of steps of a method for manufacturing a conventional nonvolatile semiconductor memory device.
【0004】図12において、201はSi基板、20
2bは不純物拡散層であるドレイン領域、203は第1
ゲ−ト絶縁膜、206は第2ゲ−ト絶縁膜形成窓であ
る。同図に示すように第1ゲート絶縁膜203をドライ
エッチングして第2ゲート絶縁膜形成窓206を作成す
る際に、Si基板201の表面がオーバーエッチングさ
れて段差207ができる。仮にドライエッチングの代わ
りにウエットエッチングを適用したとしても、エッチン
グ後にNH4OH等のアンモニア系洗剤で洗浄を行なう
と、Si基板201が洗剤によりエッチングされて同様
の段差が形成される。しかも従来は、Si基板201の
段差底面及び段差側面の面方位がいずれも(100)で
あった。次に第2ゲート絶縁膜形成窓206を通してS
i基板201の表面を酸化すると、図13に示すように
ドレイン領域202b上に第2ゲート絶縁膜208が形
成される。ただし、前記のようにSi基板201の表面
において段差底面の面方位と段差側面の面方位とが同一
であったために、図示のように第2ゲート絶縁膜208
の段差底面部分の膜厚Aと段差側面部分の膜厚Bとの関
係がA≧Bとなっていた。段差側面部分の膜厚Bが小さ
くなるのは、絶縁膜の流動による薄膜化(thinni
ng)現象が生じるからである。In FIG. 12, reference numeral 201 denotes an Si substrate;
2b is a drain region which is an impurity diffusion layer, and 203 is a first region.
A gate insulating film 206 is a window for forming a second gate insulating film. As shown in the figure, when the first gate insulating film 203 is dry-etched to form the second gate insulating film forming window 206, the surface of the Si substrate 201 is over-etched to form a step 207. Even if wet etching is applied instead of dry etching, if cleaning is performed with an ammonia-based detergent such as NH 4 OH after the etching, the Si substrate 201 is etched by the detergent and similar steps are formed. In addition, conventionally, both the plane orientation of the step bottom surface and the step side surface of the Si substrate 201 are (100). Next, through the second gate insulating film forming window 206, S
When the surface of the i-substrate 201 is oxidized, a second gate insulating film 208 is formed on the drain region 202b as shown in FIG. However, since the plane orientation of the step bottom surface and the plane orientation of the step side surface are the same on the surface of the Si substrate 201 as described above, the second gate insulating film 208
The relationship between the film thickness A of the step bottom surface portion and the film thickness B of the step side surface portion was A ≧ B. The reason why the film thickness B on the side surface of the step is small is that the thickness of the insulating film is reduced by thinning (thinni).
ng) The phenomenon occurs.
【0005】[0005]
【発明が解決しようとする課題】従来は、前記のように
第1ゲート絶縁膜203のエッチングの際に形成される
Si基板201のオーバーエッチング段差207におい
て段差底面及び段差側面の面方位がともに(100)で
あり、第2ゲート絶縁膜208の段差底面部分の膜厚A
に対して段差側面部分の膜厚Bが小さくなっていたた
め、第2ゲート絶縁膜208のうち段差側面部分の絶縁
耐力が小さくなっていた。したがって、書き込み消去の
ために第2ゲート絶縁膜208に繰返し電界をかける
と、第2ゲート絶縁膜208の段差側面部分に早期に絶
縁破壊が生じる問題があった。Conventionally, as described above, in the over-etching step 207 of the Si substrate 201 formed when the first gate insulating film 203 is etched, both the plane orientation of the step bottom surface and the step side surface are ( 100), and the film thickness A at the step bottom surface portion of the second gate insulating film 208
On the other hand, the film thickness B of the step side portion was small, so that the dielectric strength of the step side portion of the second gate insulating film 208 was small. Therefore, when a repetitive electric field is applied to the second gate insulating film 208 for writing and erasing, there is a problem that a dielectric breakdown occurs early on the side surface of the step of the second gate insulating film 208.
【0006】本発明はかかる点に鑑みてなされたもので
あって、絶縁破壊しにくい第2ゲート絶縁膜を有する寿
命の長い不揮発性半導体記憶装置を製造する方法を提供
することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a long-life nonvolatile semiconductor memory device having a second gate insulating film which is not easily broken down.
【0007】[0007]
【課題を解決するための手段】本発明の不揮発性半導体
記憶装置の製造方法は上記課題を解決するため、第2ゲ
ート絶縁膜形成窓を作成する際に形成される半導体基板
表面の段差において段差底面に比べて段差側面の面方位
を酸化膜の成長速度の速い面方位とすることによって第
2ゲート絶縁膜の膜厚分布を改善する。具体的に、請求
項1の発明では、第1の面方位を有する半導体基板の表
面上に設けられたソース領域、ドレイン領域及び該両領
域に挟まれたチャネル領域上に第1ゲート絶縁膜を形成
する第1ゲート絶縁膜形成工程と、ドレイン領域上の第
1ゲート絶縁膜をエッチングにより一部除去して半導体
基板表面を一部露出させ、露出した半導体基板表面のオ
ーバーエッチングによって半導体基板表面に段差が形成
されるように第2ゲート絶縁膜形成窓を作成することに
よって第1の面方位と同一の面方位を有する段差底面と
該段差底面に比べて酸化膜の成長速度が速い第2の面方
位を有する段差側面とを露出させる第2ゲート絶縁膜形
成窓作成工程と、第2ゲート絶縁膜形成窓を通して段差
底面及び段差側面を酸化することにより第2ゲート絶縁
膜を形成する第2ゲート絶縁膜形成工程と、第1及び第
2ゲート絶縁膜の上にフローティングゲート、絶縁膜及
びコントロールゲートを順次形成する配線工程とを備え
たものとする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a method of manufacturing a nonvolatile semiconductor memory device according to the present invention has a step on a surface of a semiconductor substrate formed when a second gate insulating film forming window is formed. The thickness distribution of the second gate insulating film is improved by setting the plane direction of the step side surface to the plane direction in which the growth rate of the oxide film is higher than that of the bottom surface. More specifically, according to the first aspect of the present invention, the first gate insulating film is formed on the source region, the drain region provided on the surface of the semiconductor substrate having the first plane orientation, and the channel region sandwiched between the two regions. Forming a first gate insulating film, and partially removing the first gate insulating film on the drain region by etching to partially expose the semiconductor substrate surface; By forming the second gate insulating film forming window such that a step is formed, a step bottom having the same plane orientation as the first plane orientation and a second layer having a higher oxide film growth rate than the step bottom are formed. a second gate insulating film formed window creation step of exposing the step side having a plane orientation, the second gate insulating film by oxidizing the step bottom and step side through the second gate insulating film formed window A second gate insulating film forming step of forming the floating gate, and that a wiring sequentially forming an insulating film and a control gate over the first and second gate insulating film.
【0008】特に絶縁耐力の高い第2ゲート絶縁膜を形
成するために請求項2の発明では、第2ゲート絶縁膜形
成工程にRTP(Rapid Thermal Pro
cess)法を適用し、半導体基板表面を酸化して第2
ゲート絶縁膜を形成する。[0008] In order to form a second gate insulating film having a particularly high dielectric strength, in the invention of claim 2, RTP (Rapid Thermal Pro) is used in the second gate insulating film forming step.
ses) method to oxidize the surface of the semiconductor substrate and
A gate insulating film is formed.
【0009】[0009]
【作用】請求項1の発明によれば、第2ゲート絶縁膜形
成窓を作成する際に形成される半導体基板表面のオーバ
ーエッチング段差において、段差側面は段差底面に比べ
て面方位の違いにより酸化膜の成長速度が速くなってい
る。したがって、次工程で第2ゲート絶縁膜形成窓を通
して段差底面と段差側面とを同時に酸化すれば、第2ゲ
ート絶縁膜は段差側面部分が段差底面部分より厚く成長
する。これにより、第2ゲート絶縁膜のうち段差側面部
分の絶縁耐力が向上する。According to the first aspect of the present invention, in the over-etching step on the surface of the semiconductor substrate formed when the second gate insulating film forming window is formed, the side surface of the step is oxidized due to the difference in the plane orientation as compared with the bottom surface of the step. The film growth rate is faster
You. Therefore, in the next step, if the step bottom surface and the step side surface are simultaneously oxidized through the second gate insulating film forming window, the second gate insulating film grows thicker at the step side surface portion than at the step bottom portion portion. Thereby, the dielectric strength of the step side surface portion of the second gate insulating film is improved.
【0010】また、請求項2の発明によれば、第2ゲー
ト絶縁膜形成工程にRTP法を適用する場合、第2ゲー
ト絶縁膜が短時間のうちに成長するので、この絶縁膜の
流動による薄膜化現象が通常の電気炉の場合よりも小さ
くなる。したがって、絶縁破壊しにくい第2ゲート絶縁
膜が容易に得られる。According to the second aspect of the present invention, when the RTP method is applied to the step of forming the second gate insulating film, the second gate insulating film grows in a short time. The phenomenon of thinning is smaller than in a normal electric furnace. Therefore, a second gate insulating film that is not easily broken down can be easily obtained.
【0011】[0011]
【実施例】図1〜図11は、本発明の一実施例における
不揮発性半導体記憶装置の製造方法を説明する工程断面
図である。1 to 11 are process sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.
【0012】まず図1のように、半導体基板であるSi
基板101の表面上に設けられたソース領域102a、
ドレイン領域102b及び該両領域に挟まれたチャネル
領域102c上に酸化膜である第1ゲート絶縁膜103
を形成する。Si基板101としては、ソース領域10
2a、ドレイン領域102b及びチャネル領域102c
からなるトランジスタ素子を形成する面の面方位が(1
00)であり、オリエンテーション・フラット(オリフ
ラと略称する。)の面方位が(110)であるSiウェ
ーハを選択するのが好都合である。オリフラに対して平
行な直線とこれに垂直に交わる直線とを縦横の基準線と
してSi基板101上に多数のトランジスタ素子を形成
しておく。First, as shown in FIG. 1, a semiconductor substrate Si
A source region 102 a provided on the surface of the substrate 101,
A first gate insulating film 103 serving as an oxide film on the drain region 102b and the channel region 102c sandwiched between the two regions;
To form As the Si substrate 101, the source region 10
2a, drain region 102b and channel region 102c
The plane orientation of the surface forming the transistor element made of
It is convenient to select a Si wafer whose orientation flat (orientation flat) is (110). A large number of transistor elements are formed on the Si substrate 101 by using a straight line parallel to the orientation flat and a straight line perpendicular to the orientation flat as vertical and horizontal reference lines.
【0013】この第1ゲート絶縁膜形成工程に続いて、
図2〜図4の第2ゲート絶縁膜形成窓作成工程を実行す
る。まず図2のように第1ゲート絶縁膜103上にエッ
チング窓105を有するフォトレジスト104を形成す
る。エッチング窓105はドレイン領域102b上に位
置する矩形の窓である。次に、エッチング窓105内の
第1ゲート絶縁膜103をドライエッチングにより除去
する。このエッチングの結果を図3に示す。ドライエッ
チングによって第2ゲート絶縁膜形成窓106ができて
Si基板101の表面が一部露出するだけでなく、Si
基板101の表面がオーバーエッチングされて段差10
7が形成される。このようにして第2ゲート絶縁膜形成
窓106を作成した後にフォトレジスト104を除去し
た状態を図4に示す。なお、前記のように仮にドライエ
ッチングの代わりにウエットエッチングを適用したとし
ても、エッチング後にNH4OH等のアンモニア系洗剤
で洗浄を行なうと、Si基板101が洗剤によりエッチ
ングされてSi基板101に同様の段差107が形成さ
れる。Following the first gate insulating film forming step,
The step of forming the second gate insulating film forming window shown in FIGS. 2 to 4 is performed. First, a photoresist 104 having an etching window 105 is formed on the first gate insulating film 103 as shown in FIG. The etching window 105 is a rectangular window located on the drain region 102b. Next, the first gate insulating film 103 in the etching window 105 is removed by dry etching. FIG. 3 shows the result of this etching. The second gate insulating film forming window 106 is formed by the dry etching, so that not only the surface of the Si substrate 101 is partially exposed but also the Si
The surface of the substrate 101 is over-etched to
7 is formed. FIG. 4 shows a state in which the photoresist 104 has been removed after the second gate insulating film forming window 106 has been formed in this manner. Even if wet etching is applied instead of dry etching as described above, if cleaning is performed with an ammonia-based detergent such as NH 4 OH after the etching, the Si substrate 101 is etched by the detergent and becomes similar to the Si substrate 101. Is formed.
【0014】図5及び図6は、ぞれぞれ図4の第2ゲー
ト絶縁膜形成窓106の拡大断面図及び拡大斜視図であ
る。両図に示すように本実施例では、Si基板101の
オーバーエッチング段差107において段差底面の面方
位がトランジスタ素子形成面の面方位と同じ(100)
になり、段差側面の面方位がオリフラと同じ(110)
になる。FIGS. 5 and 6 are an enlarged sectional view and an enlarged perspective view of the second gate insulating film forming window 106 of FIG. 4, respectively. As shown in both figures, in the present embodiment, the plane orientation of the step bottom surface in the overetching step 107 of the Si substrate 101 is the same as the plane orientation of the transistor element formation surface (100).
And the plane direction of the step side is the same as the orientation flat (110)
become.
【0015】次に、第2ゲート絶縁膜形成窓106を通
してSi基板101の露出面を熱酸化する。この第2ゲ
ート絶縁膜形成工程の実行結果を図7に、その拡大図を
図8にそれぞれ示す。Siは面方位(100)に比べて
面方位(110)の方が酸化膜の成長速度が速いので、
形成された第2ゲート絶縁膜108は従来とは違って段
差底面部分の膜厚Aに比べて段差側面部分の膜厚Bの方
が大きくなる。Next, the exposed surface of the Si substrate 101 is thermally oxidized through the second gate insulating film forming window 106. FIG. 7 shows an execution result of the second gate insulating film forming step, and FIG. 8 is an enlarged view thereof. Si has a higher growth rate of the oxide film in the plane orientation (110) than in the plane orientation (100).
The thickness B of the formed second gate insulating film 108 on the side surface of the step is larger than the film thickness A on the bottom surface of the step, unlike the related art.
【0016】最後に図9〜図11に示すように、第1ゲ
ート絶縁膜103及び第2ゲート絶縁膜108の上にフ
ローティングゲート109、絶縁膜110及びコントロ
ールゲート111を順次形成する配線工程を実行して不
揮発性半導体記憶装置を完成させる。[0016] Finally, as shown in FIGS. 9 to 11, the first gate
Floating gate 109 on the over gate insulating film 103 and the second gate insulating film 108, by executing the wire sequentially forming an insulating film 110 and the control gate 111 to complete the non-volatile semiconductor memory device.
【0017】以上説明したように本実施例によれば、第
2ゲート絶縁膜108の段差側面部分の膜厚Bを底面部
分の膜厚Aに比べて大きくすることができるから、従来
は低かった段差側面部分の絶縁耐力が向上する。したが
って、書き込み消去のために第2ゲート絶縁膜208に
繰返し電界をかけても第2ゲート絶縁膜208に絶縁破
壊が生じにくくなり、不揮発性半導体記憶装置の寿命が
延びる。As described above, according to the present embodiment, the film thickness B on the side surface of the step of the second gate insulating film 108 can be made larger than the film thickness A on the bottom surface, so that it was conventionally low. The dielectric strength of the step side part is improved. Therefore, even if a repetitive electric field is applied to the second gate insulating film 208 for writing and erasing, dielectric breakdown does not easily occur in the second gate insulating film 208, and the life of the nonvolatile semiconductor memory device is extended.
【0018】なお、上記実施例ではSi基板101のト
ランジスタ素子形成面の面方位を(100)とし、Si
基板101のオーバーエッチング段差側面すなわち第2
ゲート絶縁膜形成窓106の側壁の面方位を(110)
としたが、素子形成面の面方位を(100)又は(11
0)とする場合には側壁の面方位を(111)としても
同様の効果が得られる。ただし、後者の場合は側壁が素
子形成面に対して垂直にならない。 In the above embodiment, the plane orientation of the transistor element forming surface of the Si substrate 101 is (100),
The side face of the over-etched step of the substrate 101, that is, the second
The plane orientation of the side wall of the gate insulating film formation window 106 is (110)
However, the plane orientation of the element formation surface was set to (100) or (11).
In the case of 0), the same effect can be obtained even when the plane orientation of the side wall is set to (111). However, in the latter case, the side wall is not perpendicular to the element formation surface .
【0019】また、半導体基板として、Si基板101
に代えてGaAs等の化合物半導体基板を用いても構わ
ない。 As a semiconductor substrate, an Si substrate 101 is used.
Alternatively, a compound semiconductor substrate such as GaAs may be used.
【0020】第2ゲート絶縁膜形成工程にRTP(Ra
pid Thermal Process)法を適用す
る場合には、第2ゲート絶縁膜108が短時間のうちに
成長するので、この絶縁膜108の流動による薄膜化現
象が通常の電気炉の場合よりも小さくなる。したがっ
て、第2ゲート絶縁膜108の段差側壁部分の絶縁耐力
が向上し、特に段差底面部分と段差側壁部分との間のコ
ーナー部における絶縁破壊を防ぐことができる。 In the second gate insulating film forming step, RTP (Ra
When the pid thermal process is applied, the second gate insulating film 108 grows in a short time, so that the phenomenon of thinning due to the flow of the insulating film 108 is smaller than in a normal electric furnace. Therefore, the dielectric strength of the step side wall portion of the second gate insulating film 108 is improved, and it is possible to prevent dielectric breakdown particularly at a corner portion between the step bottom portion and the step side wall portion .
【0021】[0021]
【発明の効果】以上説明してきたように請求項1の発明
によれば、第2ゲート絶縁膜形成窓を作成する際に形成
される半導体基板表面のオーバーエッチング段差におい
て面方位の違いにより段差側面が段差底面に比べて酸化
膜の成長速度が速くなっており、次工程で形成される第
2ゲート絶縁膜の段差側面部分が段差底面部分より厚く
なる。したがって、本発明の方法で製造される不揮発性
半導体記憶装置は、従来に比べて第2ゲート絶縁膜の絶
縁耐力が向上し、信頼性が大きく向上する。しかも、半
導体基板の面方位を考慮するだけでこの効果が得られ
る。As described above, according to the first aspect of the present invention, the side surface of the semiconductor substrate surface formed at the time of forming the second gate insulating film forming window is formed by the difference in plane orientation in the overetching step. Is oxidized compared to the bottom of the step
The growth rate of the film is increased, and the side surface of the step of the second gate insulating film formed in the next step is thicker than the bottom of the step. Therefore, in the nonvolatile semiconductor memory device manufactured by the method of the present invention, the dielectric strength of the second gate insulating film is improved and the reliability is greatly improved as compared with the related art. Moreover, this effect can be obtained only by considering the plane orientation of the semiconductor substrate.
【0022】特に、請求項2の発明では第2ゲート絶縁
膜形成工程にRTP法を適用し、半導体基板表面を酸化
して第2ゲート絶縁膜を形成することにより、第2ゲー
ト絶縁膜が短時間のうちに成長するので従来生じていた
薄膜化現象が小さくなり、第2ゲート絶縁膜の絶縁耐力
が大きく向上する。 In particular, in the second aspect of the present invention, the surface of the semiconductor substrate is oxidized by applying the RTP method to the second gate insulating film forming step.
By forming the second gate insulating film and a thin film phenomenon that occurs prior since grown out of the second gate insulating film short is reduced, the dielectric strength of the second gate insulating film is greatly improved .
【図1】 本発明の一実施例における不揮発性半導体記
憶装置の製造方法を説明する工程断面図であって、第1
ゲート絶縁膜形成工程が完了した状態を示す。FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.
This shows a state where the gate insulating film forming step has been completed.
【図2】 第2ゲート絶縁膜形成窓作成工程のうち図1
の工程に引き続いて第1ゲート絶縁膜上にエッチング窓
を有するフォトレジストを形成する工程が完了した状態
を示す断面図である。FIG. 2 is a view showing a step of forming a second gate insulating film forming window in FIG.
FIG. 13 is a cross-sectional view showing a state after the step of forming a photoresist having an etching window on the first gate insulating film after the step of FIG.
【図3】 第2ゲート絶縁膜形成窓作成工程のうち図2
の工程に引き続いて第2ゲート絶縁膜形成窓を作成する
工程が完了した状態を示す断面図である。FIG. 3 is a view showing a step of forming a second gate insulating film forming window in FIG.
FIG. 14 is a cross-sectional view showing a state where a step of forming a second gate insulating film formation window following the step of FIG.
【図4】 第2ゲート絶縁膜形成窓作成工程のうち図3
の工程に引き続いてフォトレジストを除去する工程が完
了した状態を示す断面図である。FIG. 4 is a diagram showing a step of forming a second gate insulating film forming window in FIG.
FIG. 13 is a cross-sectional view showing a state in which the step of removing the photoresist subsequent to the step of FIG.
【図5】 図4の第2ゲート絶縁膜形成窓の拡大図であ
る。FIG. 5 is an enlarged view of a second gate insulating film forming window of FIG. 4;
【図6】 図5の第2ゲート絶縁膜形成窓の斜視図であ
る。FIG. 6 is a perspective view of a second gate insulating film forming window of FIG. 5;
【図7】 図4の工程に引き続く第2ゲート絶縁膜形成
工程が完了した状態を示す断面図である。FIG. 7 is a cross-sectional view showing a state where a second gate insulating film forming step following the step of FIG. 4 is completed.
【図8】 図7の第2ゲート絶縁膜部分の拡大図であ
る。FIG. 8 is an enlarged view of a second gate insulating film part of FIG. 7;
【図9】 配線工程のうち図7の工程に引き続いて第1
及び第2ゲート絶縁膜の上にフローティングゲートを形
成する工程が完了した状態を示す断面図である。[9] The first Following out 7 step wiring process
And is a sectional view showing a state where the process has been completed for forming a floating gate on the second gate insulating film.
【図10】 配線工程のうち図9の工程に引き続いてフ
ローティングゲート上に絶縁膜を形成する工程が完了し
た状態を示す断面図である。FIG. 10 is a cross-sectional view showing a state in which a step of forming an insulating film on the floating gate has been completed following the step of FIG. 9 in the wiring step;
【図11】 配線工程のうち図10の工程に引き続いて
絶縁膜上にコントロールゲートを形成する工程が完了し
て不揮発性半導体記憶装置が完成した状態を示す断面図
である。FIG. 11 is a cross-sectional view showing a state in which a step of forming a control gate on an insulating film is completed following the step of FIG. 10 in the wiring step to complete a nonvolatile semiconductor memory device.
【図12】 従来の不揮発性半導体記憶装置の製造方法
を説明する工程断面図であって、第2ゲート絶縁膜形成
窓を作成する工程が完了した状態を示す。FIG. 12 is a process cross-sectional view illustrating a method for manufacturing a conventional nonvolatile semiconductor memory device, and shows a state where a process of forming a second gate insulating film formation window is completed.
【図13】 図12の工程に引き続いて第2ゲート絶縁
膜を形成する工程が完了した状態を示す断面図である。FIG. 13 is a cross-sectional view showing a state where a step of forming a second gate insulating film subsequent to the step of FIG. 12 is completed.
101,201…Si基板(半導体基板) 102a…ソース領域 102b,202b…ドレイン領域 102c…チャネル領域 103,203…第1ゲート絶縁膜 104…フォトレジスト 105…エッチング窓 106,206…第2ゲート絶縁膜形成窓 107,207…Si基板表面のオーバーエッチング段
差 108,208…第2ゲート絶縁膜 109…フローティングゲート 110…絶縁膜 111…コントロールゲート101, 201: Si substrate (semiconductor substrate) 102a: Source region 102b, 202b: Drain region 102c: Channel region 103, 203: First gate insulating film 104: Photoresist 105: Etching window 106, 206: Second gate insulating film Forming windows 107, 207: Over-etching steps on Si substrate surface 108, 208: Second gate insulating film 109: Floating gate 110: Insulating film 111: Control gate
Claims (2)
上に設けられたソース領域、ドレイン領域及び該両領域
に挟まれたチャネル領域上に第1ゲート絶縁膜を形成す
る第1ゲート絶縁膜形成工程と、 前記ドレイン領域上の前記第1ゲート絶縁膜をエッチン
グにより一部除去して前記半導体基板表面を一部露出さ
せ、かつ露出した前記半導体基板表面のオーバーエッチ
ングによって前記半導体基板表面に段差が形成されるよ
うに第2ゲート絶縁膜形成窓を作成することにより、前
記第1の面方位と同一の面方位を有する段差底面と該段
差底面に比べて酸化膜の成長速度が速い第2の面方位を
有する段差側面とを露出させる第2ゲート絶縁膜形成窓
作成工程と、 前記第2ゲート絶縁膜形成窓を通して前記段差底面及び
前記段差側面を酸化することにより第2ゲート絶縁膜を
形成する第2ゲート絶縁膜形成工程と、 前記第1及び第2ゲート絶縁膜の上にフローティングゲ
ート、絶縁膜及びコントロールゲートを順次形成する配
線工程とを備えたことを特徴とする不揮発性半導体記憶
装置の製造方法。A first gate insulating film formed on a source region and a drain region provided on a surface of a semiconductor substrate having a first plane orientation and a channel region interposed between the source region and the drain region; A film forming step, by partially removing the first gate insulating film on the drain region by etching to partially expose the semiconductor substrate surface, and by overetching the exposed semiconductor substrate surface, By forming the second gate insulating film forming window so that a step is formed, a step bottom having the same plane orientation as the first plane orientation and a growth rate of an oxide film which is faster than the step bottom are formed. this oxidizing the second gate insulating film formed window creation step of exposing the step side, the stepped bottom surface and the step side through the second gate insulating film formed window having a second surface orientation The second gate insulating film forming step of forming a second gate insulating film, the floating gate on the first and second gate insulating film, further comprising a wiring step of successively forming an insulating film and a control gate A method for manufacturing a nonvolatile semiconductor memory device, characterized by:
ゲート絶縁膜を形成することを特徴とする請求項1記載
の不揮発性半導体記憶装置の製造方法。2. The method according to claim 2, wherein the oxidation is performed based on an RTP method.
2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein a gate insulating film is formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP657291A JP2634492B2 (en) | 1991-01-23 | 1991-01-23 | Manufacturing method of nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP657291A JP2634492B2 (en) | 1991-01-23 | 1991-01-23 | Manufacturing method of nonvolatile semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04271177A JPH04271177A (en) | 1992-09-28 |
JP2634492B2 true JP2634492B2 (en) | 1997-07-23 |
Family
ID=11642052
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Application Number | Title | Priority Date | Filing Date |
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JP657291A Expired - Fee Related JP2634492B2 (en) | 1991-01-23 | 1991-01-23 | Manufacturing method of nonvolatile semiconductor memory device |
Country Status (1)
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JP (1) | JP2634492B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101900103B1 (en) * | 2010-12-29 | 2018-09-18 | 에이블릭 가부시키가이샤 | Semiconductor nonvolatile memory device |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100423576B1 (en) * | 1997-06-30 | 2004-10-02 | 주식회사 하이닉스반도체 | Fabricating method of flash memory device for reducing undercut and noise |
US7307309B2 (en) * | 2004-03-04 | 2007-12-11 | Texas Instruments Incorporated | EEPROM with etched tunneling window |
JP2010283110A (en) * | 2009-06-04 | 2010-12-16 | Rohm Co Ltd | Semiconductor device |
JP2011100876A (en) * | 2009-11-06 | 2011-05-19 | Asahi Kasei Electronics Co Ltd | P-channel nonvolatile memory and semiconductor device, and method of manufacturing p-channel nonvolatile memory |
JP5606235B2 (en) * | 2010-09-14 | 2014-10-15 | セイコーインスツル株式会社 | Semiconductor nonvolatile memory device |
JP2014143377A (en) * | 2013-01-25 | 2014-08-07 | Seiko Instruments Inc | Semiconductor nonvolatile memory |
-
1991
- 1991-01-23 JP JP657291A patent/JP2634492B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101900103B1 (en) * | 2010-12-29 | 2018-09-18 | 에이블릭 가부시키가이샤 | Semiconductor nonvolatile memory device |
Also Published As
Publication number | Publication date |
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JPH04271177A (en) | 1992-09-28 |
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