JP2589694B2 - Charge transfer device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a charge transfer device.

2. Description of the Related Art In recent years, most solid-state imaging devices have been replaced by image pickup tubes in consumer applications as image pickup devices such as video cameras.
Performance is being improved. Especially the signal to noise ratio (S / N
Ratio) is desired, but the amount of signal charge in one pixel tends to decrease due to the decrease in the light receiving area due to the increase in resolution. Therefore, noise reduction in signal detection, that is, S Increasing the / N ratio is an important issue.

Hereinafter, a conventional charge transfer device will be described with reference to the drawings.

FIG. 7 is a schematic view of a main part of a conventional charge transfer device. In FIG. 7, 1 is a transfer gate electrode, 2 is an output gate electrode, 5 is a reset gate electrode, 6 is a reset / drain electrode, 14 is a floating diffusion layer, and 15 is a floating diffusion layer.
An amplifier detects and outputs 14 potentials, and 16 is its output terminal.

The operation of the conventional charge transfer device configured as described above will be described. The signal charge is transferred to the floating diffusion layer 14 over the channel immediately below the transfer gate electrode 1 and the output gate electrode 2, where the floating charge is transferred. It is converted to a voltage, which causes a potential change in the layer 14. In general, the first drive transistor of the amplifier 15 that detects and outputs the potential of the floating diffusion layer 14 is formed of a surface-type MOS-FET.
It is strongly affected by the interface between the Si surface and the SiO ₂ film. For this reason,
The disadvantage was that there was much noise such as 1 / f noise. The potential of the floating diffusion layer 14 is set by the reset gate electrode 5 so that the potential immediately before charge transfer is always constant.
There was fluctuation, which had a major problem of becoming KTC noise (noise accompanying capacitance due to temperature fluctuation).

SUMMARY OF THE INVENTION In view of the above-mentioned disadvantages, the present invention eliminates noise caused by an output amplifier, eliminates fluctuations in potential after reset in a floating diffusion layer, and can realize a high S / N ratio. Is provided.

Means for Solving the Problems In order to solve the above problems, a charge transfer device according to the present invention includes a first impurity layer which is divided and juxtaposed to transfer a signal charge and is in contact with the first impurity layer. A second impurity layer having a conductivity type opposite to that of the first impurity layer, and utilizing a change in a depletion region of the second impurity layer depending on a signal charge transferred into the first impurity layer; Then, a signal is output from the second impurity layer.

Operation With this configuration, the potential of the floating diffusion layer made of the first impurity layer can be detected without using a surface-type MOSFET.
Furthermore, fluctuations in the potential of the floating diffusion layer after resetting can be prevented, so that noise can be significantly reduced.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic view of a main part of a charge transfer device according to an embodiment of the present invention. In FIG. 1, each reference numeral in the figure denotes 1 for a transfer gate electrode, 2 for an output gate electrode,
Reference numeral 3 denotes an n-type impurity diffusion layer which is divided into two and juxtaposed, 4 denotes a p-type impurity diffusion layer in contact with each layer of the n-type impurity diffusion layer 3, 5 denotes a reset gate electrode, 6 denotes a reset / drain electrode,
Reference numeral 7 denotes a p-type substrate, and 8 denotes an output terminal connected to the p-type impurity diffusion layer 4.

FIG. 2 is a cross-sectional view taken along the line AA 'of FIG. 1. In each of the reference numerals in the figure, 9 denotes a load resistor, and 10 denotes a drive transistor. FIG. 5 is a sectional view taken along the line BB 'in FIG.

The operation of the charge transfer device configured as described above will be described below.

The n-type impurity diffusion layer 3 is maintained at a reset potential by a voltage applied to the reset / drain electrode 6.

By the transfer gate electrode 1 and the output gate electrode 2, the signal charge that has passed over the channel immediately below is transferred to the n-type impurity diffusion layer 3.

First, the operation when a negative voltage to one end V _D1 of the load resistor 9 is applied. In this case, the drive transistor 10 formed by the n-type impurity diffusion layer 3, the p-type impurity diffusion layer 4, and the p-type substrate 7 is a junction field effect transistor (J-FE) having the n-type impurity diffusion layer 3 as a gate.
Work as T). By applying the negative voltage V _D1 , the potential relationship on the line CC ′ in FIG. 2 is as shown in FIG. 3B, and the potential relationship between the p-type substrate 7 and the p-type impurity diffusion layer 4 is changed. A channel (hole) for holes serving as carriers is formed in the direction. On the other hand, the n-type impurity diffusion layer 3 and p
A depletion layer region is formed around the PN junction formed with the p-type impurity diffusion layer 4 or the p-type substrate 7,
The potential relationship on the D 'line is as shown by the solid line in FIG. 4 (b). The channel is narrowed by the depletion layer, so that the drain current hardly flows. Next, when the signal charge is transferred to the n-type impurity diffusion layer 3 over the channel immediately below by the transfer gate electrode 1 and the output gate electrode 2, the n-type impurity diffusion layer 3 serving as a gate is transferred.
Since the reverse bias voltage between the P.sub.-type substrate 7 and the source of the J.FET becomes small, the depletion layer region becomes small as shown by the dotted line in FIG. 4 (b). That is, JFET
Since the channel is widened, the drain current flows easily. The drain current is controlled according to the amount of signal charge transferred in this manner, and detected from the output terminal 8.

Next, when a positive voltage is applied to one end _VD1 of the load resistor 9, the potential relationship on the line CC 'in FIG.
(A) As shown in the figure. By forming a depletion layer region around the PN junction formed by the n-type impurity diffusion layer 3 and the p-type impurity diffusion layer 4 or the p-type substrate 7,
(A) As shown in the figure, a potential barrier appears near point a.
The signal charge is transferred from the transfer gate electrode 1 to the n-type impurity diffusion layer 3 and the output gate electrode 2 through the channel immediately below (a), thereby causing the potential barrier as shown by the dotted line in FIG. Becomes shallower, and holes as carriers easily flow. As described above, the depth of the potential barrier mainly controls the flow rate of holes flowing from the source to the drain, and the potential barrier becomes shallower according to the amount of signal charges transferred to the n-type impurity diffusion layer 3. FIG. 4 (a) shows a potential relation diagram along the line DD 'in FIG. When the signal charge is transferred to the n-type impurity diffusion layer 3, the potential barrier becomes shallow as shown by the dotted line. Incidentally, as shown in FIG. 6, it is also possible to connect an impedance conversion circuit comprising drive transistors 11, 11 'and load transistors 12, 12' after the terminal 8. In particular, if one V _D1 of the load resistor 9 is negative voltage, the voltage at terminal 8 becomes negative, the drive transistor 11, 11 'embedded MOSFET or n
Since a −J · FET can be used, it is possible to further reduce noise.

Thus, even when a positive or negative voltage is applied to one end V _D1 of the load resistor 9, the Si—SiO ₂ interface is not used and the Si
Since the change in the internal depletion layer region is used, 1 / f noise due to the influence of the interface does not occur.

Further, the impurity surface density of the n-type impurity diffusion layer 3 is set to 3 × 10 ¹² cm.
^By setting it lower than ^-2, it is possible to prevent fluctuations in the potential of the n-type impurity diffusion layer 3 after resetting, eliminate reset noise, and realize a high S / N ratio. Further, by dividing and juxtaposing the n-type impurity diffusion layer 3 serving as a gate, a sufficient cross-sectional area of a channel region formed in the p-type substrate 7 can be ensured, thereby increasing the J · J of high transconductance (gm). An FET can be obtained, and a charge transfer device with high sensitivity characteristics can be realized.

Effect of the Invention As described above, the present invention provides the second diffusion layer of the opposite conductivity type in contact with the first impurity diffusion layer divided and juxtaposed, and utilizes the change of the depletion layer region around the junction by these diffusion layers. By realizing the output section with high sensitivity characteristics,
No effect of -SiO ₂ interface, thus 1 / f noise, etc. are not generated charge transfer device is obtained, further, the first impurity diffusion layer impurity surface density lower than 3 × 10 ¹² cm ^-2, the first By completely depleting the impurity diffusion layer, it is possible to prevent the occurrence of reset noise and to obtain a high S / N ratio. For this reason, the practical effect is large, such as the fact that the reset noise and 1 / f noise elimination effects are effective, so that a noise elimination circuit such as a commonly used correlated double sampling circuit is not required. is there.

[Brief description of the drawings]

FIG. 1 is a schematic view of a charge transfer device according to one embodiment of the present invention, FIGS. 2 and 5 are cross-sectional views of essential parts in one embodiment of the present invention, and FIGS. FIG. 6 is a diagram showing a connection example of an impedance conversion circuit in the embodiment, and FIG. 7 is a schematic diagram of a conventional charge transfer device. 1 ... transfer gate electrode, 2 ... output gate electrode, 3 ...
n-type impurity diffusion layer, 4... p-type impurity diffusion layer, 5... reset gate electrode, 6.
7 ... p-type substrate, 8 ... terminal, 9 ... load resistance, 10 ...
Driving transistor, 11, 11 ': Transistor for driving impedance conversion circuit, 12, 12': Same load (transistor, resistor, etc.), 14: floating diffusion layer, 15
...... Amplifier, 16 ... Output terminal.

Claims (1)

(57) [Claims] 1. A transfer portion for transferring signal charges is formed on a substrate of one conductivity type, and a first impurity layer of a conductivity type opposite to the substrate is divided and juxtaposed adjacent to an output end of the transfer portion, A second impurity layer of one conductivity type is in contact with the output end of the charge transfer section, and the second impurity layer is in contact with the substrate sandwiched between the divided and juxtaposed layers of the first impurity layer; First
And the second impurity layer are a charge transfer device in contact with a reset game electrode on the side opposite to the output end of the transfer unit, and the first impurity layer is a gate electrode of a junction field effect transistor. The second impurity layer is a drain electrode (or a source electrode) of the transistor; the substrate is a source electrode (or a drain electrode) of the transistor; Depending on the amount of change in the signal charge transferred to the layer,
A charge transfer device for detecting a signal output by changing a depletion layer region formed at a junction between the first impurity layer, the second impurity layer, and the substrate.