JPS59108343A - solid state imaging device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Conventionally, solid-state imaging devices that use a charge transfer device such as a COD, or a device that uses a MOS (MOS) transistor are widely used. However, these solid-state imaging devices have problems such as charge leakage during charge transfer, low light detection sensitivity, and difficulty in increasing the degree of integration. Static induction transistor (Static induction transistor)
The initials of Transistor l.

A new method using SIT (called SIT) has been newly proposed (for example, Japanese Patent Laid-Open No. 15229/1983).

FIG. 1A is a sectional view showing the structure of such an SIT, and FIG. 1B is a circuit diagram showing the overall structure of a solid-state imaging device using this SIT. .

be.

As shown in FIG. 1A, a low impurity concentration (1o18~
An n-silicon epitaxial layer 2 of 1014i/cm8) is grown, and an n+ drain region 8, a p+ signal storage gate region 4, and a p+ isolation gate region 5 are formed on the surface 1 of this epitaxial layer 2 by thermal diffusion or the like. .

Further, on the substrate], an electrode 6 is formed to the source 1, and in the regions 3, 4 and 5, a drain electrode 8 is formed through the nitrogen layer formed in the insulating layer 7, and a signal storage gate electrode 2 is formed as the electrode 6. and separate gate electrodes 10 are formed. The diffusion depth of the drain region 3 is made shallower than the diffusion depth of the gate region 4.5. Isolation gate region #5 surrounds the drain region 8 and signal product gate region 4 of each SIT, and is mainly used to isolate adjacent SITs from each other, providing a potential that also serves as a floating potential. You can leave it there. Also, n
-Epitaxial Ni2 constitutes a channel region, and in a steady soft region with no optical input, that is, even at gate potential Ov, the channel, ... channel region is already depleted, and the source-drain region is in the forward direction. Even when biased, no current flows between the source and drain.

When an optical input is applied in such a configuration, holes and lightning electrons are generated in the channel region or gate depletion floor, of which the electrons flow away to the grounded source, while the holes are used for signal accumulation. It is accumulated in the gate region 4 and is responsible for only the gate potential PΔVG. After that, when a gate read pulse φG is applied to the gate electrode 9, the gate potential becomes φG plus ΔVG, and the potential between the signal storage gate region 4 and the drain region 3 decreases and becomes depleted. The layer decreases, and a drain current corresponding to the optical input flows between the source and drain. The first class in this drain city is SI
Due to the amplification effect of T, ΔVG is multiplied by the degree of amplification and becomes large. Also, does the same behavior occur even if the source and drain of SIT are swapped? It is something to do.

FIG. 1B shows the circuit configuration of the solid-state imaging device arranged in a 5ITE matrix as described above.・FIG. 1C is a signal waveform diagram for explaining the operation. As described above, each of 5ITII-1, 11-2, and so on is a normally-off type n-channel SIT, and the output video signal corresponding to the optical input is read out using the FXY end addressing method. The sources of the SITs constituting each pixel are grounded and connected to the drains G of a group of SITs arranged in the X direction to the row lines 12-1, 12-2, respectively. Video line via hand-folding transistors 13-1, 13-2--1...
14 in common. Also, the gates of the SIT group in one row in the Y direction are connected to the column line 15-1.15-
Connected to 2-m-. The video line 14 passes through the load resistor 16 and receives direct current! , power source] 7, and the negative terminal of this power source is grounded.

Now, consider the case where the output of one SIT pixel is read out. For example, by row selection pulse φS1, gate read pulse φG1 is applied to column line 15-1 while transistor 18-1 connected to row line 2-1 is on.

5ITI 1-1 is selected, and this 5IT11
A source current of −1 flows through the video line 14 through the erosive resistance] 6, and an output voltage VOut is generated at the output terminal 18. This sauce city as mentioned above.

Since the current is a function of the gate voltage, and this gate voltage is a function of one light input, the increase from the output voltage in the dark is Δv.
out becomes a heavy pressure corresponding to the optical input. Moreover, this voltage value Δvout becomes a large value, which is ΔVG times the amplification factor, due to the amplification effect of the SIT.

However, in the conventional solid-state imaging device with the SIT structure described above, the isolation gate gA region 5 for separating adjacent SITs is generally formed by diffusion at the same time as the signal storage gate region 4, so that the diffusion depth is limited. becomes the same, causing signal charge leakage of the rk-connected SIT when reading signal charges, resulting in poor separation.

It has the disadvantage of causing a decrease in image clarity. That is, in the solid-state imaging device described above, the signal charge stored in the signal storage gate region 4 of each SIT is read out by applying a positive readout pulse to the gate region. Since the signal charge is simultaneously added to the signal storage gate region of the SIT 1..., the signal charge of the adjacent SIT leaks to the selected SIT and is read out, resulting in a disadvantage that the resolution is significantly reduced.

The purpose of the present invention is to prevent such signal 1/lightning between adjacent SITs,
For this purpose, the present invention comprises a semiconductor body having an epitaxial layer P on a semiconductor substrate, one main electrode on the substrate side and one main electrode on the epitaxial layer P. Electrostatic induction transistor (S
In a solid-state imaging device with an SIT structure, in which an array of IT (IT) is provided and a separation gate region is provided on the surface of an epitaxial layer between each electrostatic induction transistor, the separation gate region is deeper than the signal storage gate region. It is characterized by being formed so as to extend up to or near it.

The present invention will now be described in detail with reference to the drawings. FIG. 2 shows a first embodiment of the solid-state imaging device of the present invention, and elements corresponding to those in FIG. 1 are designated by the same reference numerals 1.・Indicated by number. In this example, the signal strength between SITs.

In order to ensure load separation, a p+ type buried layer 21 with a high impurity concentration is provided between the substrate 1 and the epitaxial layer 2.
A p+ isolation gate region 5 is formed to reach this p+ buried N21.

As described above, in this example, since the p+ isolation gate region 5 that takes in each SIT extends to the p buried layer, which is much deeper than the p signal accumulation region, the SITs are almost completely isolated from each other. The leakage of the signal charge of each SIT is almost completely eliminated, and the resolution is significantly improved.

A device of such construction is advantageously formed as follows.

First, a p+ buried region 2] is formed in an n+ silicon substrate 1, a first n-type epitaxial layer portion 2'P is grown thereon, and then a first p+ buried region 2' is formed on this epitaxial layer portion 2'.
The isolation gate region portion 5' is selectively diffused to reach the p+ buried layer. Next, place 5b on the first evitaginal layer portion 2'.
A 2n type epitaxial layer Jmγ is grown, and a p type layer is grown in this epitaxial layer portion 2'. A second p isolation gate region portion 5' is formed by selective diffusion to reach the lower first isolation gate region portion 5', a p+ signal storage gate region 4 is formed, and an n-type impurity is further formed. ? It is selectively diffused to form an n+ drain fn. After the oxide film 7 is formed on the epitaxial layer portion 2', it is connected to each region 3, 4, and 5 by photoetching.
After forming a window and completely depositing the aluminum layer, patterning is performed to form each electrode 6, 8, 9, 1 (1 and wiring).

In this way, if the epitaxial layer 2 is formed by epitaxial growth twice and the p+ isolation gate region 5 is formed by two times of diffusion, the diffusion depth of the isolation gate region formed in each step can be shallow. Since the increase in the width of the isolation gate region due to lateral diffusion can be reduced accordingly, the width of the resulting isolation gate region can be made smaller and the integration density can be increased.

FIG. 3 shows a second embodiment of the solid-state imaging device of the present invention, and elements corresponding to those in FIG. 2 are designated by the same symbols as in FIG. 2. In this example, a p-type substrate 1' is used, and this base 1.

An n+ buried region #22 with a high impurity concentration is formed on the plate as a buried source region, and then a first epitaxial layer portion 2'f- is grown in the same manner as in the embodiment shown in FIG. 2, and a first p+ isolated gate region is formed. portion 5'' is diffused to reach the p-type substrate 1', and a second epitaxial layer portion 2' is grown and extended on this first epitaxial layer portion l, to which a second isolation gate region portion 5', a signal storage portion is formed. The gate region 4 and drain region 8 are diffused, and electrodes 8, 9.In are formed in each region.

In this example, since the p+ isolation gate area 5 surrounding each SIT is extended to the p type group &1'', the leakage of the signal charge of each SIT is prevented by kneading, and the separation between the SITs is complete. In addition, in this example, since each SIT is provided with a buried drain region, signals can be read out even in the source region, which increases the degree of freedom in usage and allows the readout electrode to be When used as a source region, it becomes easier to wire the drain tail on one surface, and it also has the effect of increasing the degree of freedom in setting the bias.In addition, in this way, the wiring of the drain tail on one surface is increased. The isolation gate region 5 is connected to the substrate 1' from L...in addition to S.
It can also be used to reset IT.

The present invention is not limited to the embodiments described above, and various modifications are possible based on the technical idea of the present invention. For example, in Example G of FIG. 2, the impurity concentration in the p+ buried region of the nl type substrate 1 and the impurity concentration in the first n type epitaxial layer portion 2'? By appropriately selecting and first controlling the thickness of the bitaxial layer portion 2' and the heat treatment of the subsequent process, the first isolated gate region portion 5' formed in the first epitaxial layer portion 2'' may be omitted or formed. It is also possible to use a buried layer 1.In addition, in the embodiment shown in FIG.
The isolation gate region 5 is formed so as to be in contact with the
As shown in FIG. 4, it is possible to obtain the desired signal charge separation effect even if it is formed somewhat apart from the p-type substrate 1'' without contacting the p-type substrate 1''.However, the complete separation effect cannot be obtained. Of course, it is better to make contact as shown in FIG. 8 in order to obtain the desired results.Also, it goes without saying that each of the diffusion regions shown in FIG. 1 and FIG. 2 can be formed by ion implantation.

[Brief explanation of drawings]

1A, B, and C are a sectional view of a conventional solid-state imaging device with an SIT structure, its circuit configuration diagram, and a signal waveform diagram for explaining its operation; FIG. 2 is a diagram of a first embodiment of the solid-state imaging device of the present invention. 3 is a sectional view of a second embodiment of the solid-state imaging device of the present invention, and FIG. 4 is a sectional view of a modification of the embodiment shown in FIG.
11] Ru. 1.1'...Substrate 2 (2', 2'')...Epitaxial frame 3...Drain region 4...Signal storage gate region 5 (5
', 5')...Isolation gate region 6...Source electrode 7...Insulating layer 8...Drain electrode
9... Signal storage gate lightning, pole 10... Minute gate electrode 2]... Buried layer 22... Buried source region.

Claims (1)

[Claims] 1. A semiconductor body having an epitaxial layer on a semiconductor substrate, the semiconductor body having one main electrode on the substrate side,
An array of static induction transistors (SIT) having the other main electrode and a signal storage gate region is provided on the surface of the epitaxial layer, and a separation gate region is provided on the surface of the epitaxial layer between each static induction transistor. 1. A solid-state imaging device having an SIT structure, wherein the separation gate region is formed to extend deeper than the signal storage gate region to a semiconductor substrate or to a vicinity thereof.