JP2552009B2 - Semiconductor memory - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory represented by a dynamic memory or the like, which has a data transfer function between a memory cell and a data register.

[Conventional technology]

Conventionally, as shown in FIG. 2, a semiconductor memory of this type has a word line WL, a pair of bit lines BL and ▲ ▼,
Bit line B formed by transistor Q11 and capacitor C11
Memory cell connected to one of L, ▲ ▼ and word line WL
Memory cell part 1 including MC1 and transistors Q25 to Q2
This data register 2 includes a flip-flop type data register 2 _A formed by 8 and having two input / output terminals, and transistors Q31 and Q32 which are turned on / off by a control signal φ1.
_A data transfer unit 3 for transmitting data between the two input / output terminals of A and the bit line BL / ▲ ▼, and a sensor which is activated by an activation signal SA3 and amplifies a differential voltage between the bit lines BL / ▲ ▼. The configuration includes the amplifier 4.

Data transfer between the memory cell portion 1 and the data register 2 _A, the transistors Q31, Q32 is possible becomes conductive when the control signal φ1 becomes high level power supply potential. When the control signal φ1 becomes low level of the ground potential, the transistor
Q31 and Q32 become non-conductive, and data transfer becomes impossible.

When data is transferred from the memory cell section 1 to the data register 2 _A , the activation signal SA3 is set to the activation level in advance, the data in the memory cell section 1 is amplified by the sense amplifier 4, and transmitted to the bit line BL, ▲ ▼. deep.

Before starting data transfer, the bit line BL and the input / output terminal ▲ ▼ of the data register 2 _A are at high level, and the bit line ▲
▼ and the input / output terminal DO of the data register 2 _A is low level, when the control signal φ1 becomes high level, the sense amplifier 4 supplies the electric charge to the input / output terminal DO of the data register 2 _A. Data register 2 _A transistor Q25
Data is amplified and fed back by Q28, and the input / output terminal of the data register 2 _A is determined by the capacity ratio of the transistors forming the sense amplifier 4, the data transfer unit 3, and the data register 2 _A.
The potential of DO, ▲ ▼ is decided.

Therefore, in order to correctly transfer the data, the drive capability of the sense amplifier 4 and the data transfer unit 3 is set to the data register 2 _A.
Is set large enough to invert.

When the control signal φ1 goes low, output terminal DO of the data register 2 _A high-level, the input and output terminals ▲ ▼ the data holding operation in the low state is performed.

When data is transferred from the data register 2 _A to the memory cell unit 1, if the input / output terminal ▲ ▼ of the data register 2 _A is at high level and the input / output terminal DO is at low level, the control signal φ
When 1 goes high, the data register 2 _A input / output terminal DO
And bit line BL via transistor Q31, input / output terminal ▲
▼ and bit line ▲ ▼ are connected via a transistor Q32.

For V _CC / 2 precharge method, bit line BL, ▲ ▼
Is at the V _CC / 2 level immediately before this connection, and the control signal φ1 goes high, so that the input / output terminals DO, ▲ ▼ of the data register 2 _A are respectively connected to the bit lines BL, ▲ ▼. The potential fluctuates to a level determined by the capacitance division with. Normally, the input / output terminal DO of the data register 2 _A , ▲
Since the capacity of ▼ is smaller than the capacity of the bit line BL, ▲ ▼, the level of the input / output terminal DO, ▲ ▼ of the data register 2 _A fluctuates close to the V _CC / 2 level.

On the other hand, the bit line BL starts to change to the low level by the transistor Q27, and the bit line ▲ ▼ starts to change to the high level by the transistor 26.

Then, when the sense amplifier 4 is activated by the activation signal SA3 after a fixed delay time after the control signal φ1 becomes high level, the sense amplifier 4 supplies electric charge to bring the bit line ▲ ▼ to high level and the bit line BL to BL. To bring it to a low level.

[Problems to be Solved by the Invention]

The conventional semiconductor memory described above has a structure in which the input / output terminal DO, ▲ ▼ of the data register 2 _A receives bit line level interference when data is transferred from the data register 2 _A to the bit line BL, ▲ ▼. and for which, during the data transfer, there is a disadvantage that the through-current flows between the power supply and the ground via the transistors constituting the data register 2 _a, Further, the bit lines BL, ▲ ▼ data transfer to the data register 2 _a from When performing, input / output terminal DO of data register 2 _A , ▲
Since ▼ is connected to the input / output terminal of the sense amplifier 4, at the time of this data transfer, between the transistor forming the data register 2 _A and the power supply / ground via the transistor forming the sense amplifier 4. There is a drawback that a through current flows.

Furthermore, it is necessary to set the driving capability of the sense amplifier 4 and the transistor of the data transfer unit 3 to a value large enough to invert the state of the data register 2 _A.
And the transistor of the data transfer unit 3 and the data register 2 _A
The transistor has to be designed while maintaining the correlation of the driving ability, and the design is complicated.

An object of the present invention is to provide a semiconductor memory capable of preventing a through current of a data register and a sense amplifier and facilitating the design thereof.

[Means for solving the problem]

A semiconductor memory according to the present invention includes a first pair of word lines and a word line.
And a second bit line, a memory cell portion having a memory cell connected to one of the bit lines and the word line, and a first activation signal having first and second input / output terminals. A data register which is activated to sense and amplify the data supplied to the first and second input / output terminals including the data from the bit line; and the first and second input / output terminals of the data register. A data transfer unit including first and second transistors provided correspondingly to the first and second bit lines, respectively, for turning on / off according to a control signal to transfer data; And the first and second input / output terminals respectively connected to the first and second bit lines and activated by the second activation signal.
And a sense amplifier that amplifies and outputs the data supplied to the second input / output terminal, and when the data in the memory cell section is transferred to the data register, the control signal is set to an activation level. After that, immediately after setting the second activation signal to the activation level and setting the second activation signal to the activation level, the first activation signal is set to the activation level,
When the data of the data register is transferred to the memory cell section, the first activation signal is set to an activation level to bring the data register into a data holding state, and the control signal is set to an activation level, The second activation signal is set to the activation level.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, the word line WL is paired with the first and second pairs.
Bit line BL, ▲ ▼, transistor Q11 and capacitor
A memory cell portion 1 formed of C11 and one of the bit lines BL, ▲ ▼ and a memory cell MC1 connected to the word line WL; and a first and a second input / output terminal DO, ▲ ▼ 1
Bit line activated by activation signal SA1, ▲ ▼
The data register 2 for sense-amplifying and holding the data supplied to the first and second input / output terminals DO, ▲ ▼ including the data from BL, ▲ ▼, and the first and second data registers 2 of the data register 2. First and second transistors provided correspondingly between the input / output terminal DO, ▲ ▼ and the first and second bit lines BL, ▲ ▼ to turn on / off according to a control signal φ1 and transfer data. The data transfer unit 3 having Q31 and Q32 is connected to the first and second bit lines in correspondence with the first and second input / output terminals and activated by the second activation signal SA2. Sense amplifier 4 for amplifying and outputting the data supplied to the first and second input / output terminals
It is configured to have and.

The data register 2 is a P-type and N-type transistor Q2.
CMOS type inverter consisting of 1, Q23, P type and N type similarly
Formed by connecting the output terminal and the input terminal of a CMOS inverter composed of transistors Q22 and Q24 of the same type, and having a function as a sense amplifier in addition to a function as a data register.

When data is transferred from the memory cell section 1 to the data register 2, the control signal φ1 is set to high level and the transistors Q31 and Q32 are turned on as shown in FIG. 3 (a).

Then, the second activation signal SA2 is set to the activation level to operate the sense amplifier 4, and immediately after the operation of the sense amplifier 4 is started (almost at the same time), the first activation signal SA1 ,.
Is changed from the precharge level to the high level and the low level, respectively, to operate the data register 2 and amplify the data in the memory cell section 1.

Next, when the transistors Q31 and Q32 are turned off by setting the control signal φ1 to the low level, the input / output terminals DO, ▲ ▼ of the data register 2 and the bit lines BL, ▲ ▼ become non-conductive, and thereafter The data holding operation of the data register 2 is performed, and the data transfer from the memory cell section 1 to the data register 2 is performed.

When data is transferred from the data register 2 to the memory cell section 1, as shown in FIG. 3 (b), the first activation signals SA1 and SA1 are set to the activation level to bring the data register 2 into the data holding state, and control is performed. When the transistors Q31, Q32 are turned on by setting the signal φ1 to a high level, the input / output terminals DO, ▲ ▼ of the data register 2 and the bit lines BL, ▲ ▼
Therefore, the bit line BL, ▲ ▼ is supplied with electric charges by the data register 2, and the data transfer from the data register 2 to the memory cell section 1 is performed.

At this time, the second activation signal SA2 is set to the activation level after a certain time has elapsed since the transistors Q31 and Q32 are turned on,
The sense amplifier 4 is operated to assist the charge supply to the bit line BL.

In addition, the control signal φ1 is set to the low level and the transistor Q3
When 1, Q32 is turned off and the data register 2 holds the data, the data in the memory cell section 1 is transferred to the bit line BL,
When it is necessary to inform ▲ ▼, the data in the memory cell section 1 is amplified by the sense amplifier 4 and the bit line BL, ▲
Tell ▼.

In this way, the data register is made to have the function of the sense amplifier, and the on / off timing of the data transfer unit 3 is
By controlling the activation timing of the data register 2 and the sense amplifier 4, the through current of the data register 2 and the sense amplifier 4 can be prevented.

Further, it is not necessary to consider the correlation between the driving capabilities of the transistors forming the data register 2 and the sense amplifier 4, and the design becomes easy.

〔The invention's effect〕

As described above, according to the present invention, the data register has a function as a sense amplifier, and by controlling the on / off timing of the data transfer section and the activation timing of the data register and the sense amplifier, The through current of the resistor and the sense amplifier can be prevented, and the design of these can be facilitated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a conventional semiconductor memory, and FIG. 3 is a diagram for explaining the operation of the embodiment shown in FIG. It is a timing chart of each part signal. 1 ... Memory cell part, 2,2 _A ... Data register, 3 ...
Data transfer unit, 4 ... Sense amplifier, BL, ▲ ▼
Bit line, C11 ... Capacitance element, MC1 ... Memory cell, Q11,
Q21 to Q28, Q31, Q32 …… Transistor, WL …… Word line.

Claims (1)

(57) [Claims] 1. A memory cell portion comprising a word line, first and second bit lines forming a pair, and a memory cell connected to one of the bit lines and the word line, and first and second memory cell parts. A data register having two input / output terminals and sense-amplified and holding the data supplied to the first and second input / output terminals including the data from the bit line activated by the first activation signal; Correspondingly provided between the first and second input / output terminals of the data register and the first and second bit lines, the first and second bit lines are turned on / off according to a control signal to transfer data. A data transfer section having two transistors and first and second input / output terminals that are respectively connected to the first and second bit lines in correspondence with each other;
A sense amplifier for activating the data supplied to the first and second input / output terminals by amplifying the data supplied to the first and second input / output terminals and transferring the data in the memory cell section to the data register. Activates the first activation signal immediately after setting the second activation signal to the activation level after setting the control signal to the activation level and setting the second activation signal to the activation level. When the level of the data register is to be transferred to the memory cell portion, the first activation signal is set to the activation level, the data register is set to the data holding state, and the control signal is set to the activation level. After that, the semiconductor memory is characterized in that the second activation signal is set to an activation level.