JPS6142794A - Sense amplifier system of semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a sense amplifier system for a semiconductor memory device.

[Technical background of the invention]

@4 Figure shows part of a typical configuration example of a conventional dynamic RAM (random access memory). That is, 1 is an input address buffer into which the address signal is input;
2 is a refresh address generator that generates a refresh address signal, 3 is an address multiplexer, LR is a row decoder line, RDI I RDz r RDs
r RD4 ”・ is a row decoder, W L 1 *
W L z r W L 3 r W L 4... are word lines, MC1, MCz + MC3+ MC
4... is a memory cell, BL, BL is a pin F line, D
MC1+DMC, is a dummy memory cell, DWLI
, DWLz is a dummy word line, SA is a sense amplifier,
LSil: sense latch control signal line, SE is the sense signal, QBQB is the bit line selection transistor controlled by the column decoder (CD) output, DL, DL is the data line, 4 is the output circuit, CB is the capacitance of the bit line , CRd is the capacitance of the row decoder line.

Each of the memory cells MC1... is composed of one canon 4-shita C6 and one transfer dart Q,
Information 10#, '1'' is stored depending on whether or not charges are accumulated in the canister C8.However, the charges accumulated in the canister C8 decrease over time due to leakage, etc. Therefore, before the accumulated charge is completely lost, it is necessary to read it once and write it again, and then to accumulate the charge again.This operation is called refresh. In general, dynamic RAM does not require the above refresh operation, for example, 256-bit dynamic RAM
However, there is a constraint that all memory cells must be refreshed once every 4 ms.

FIG. 5 shows the operation sequence in a memory configured to perform the above-mentioned refresh periodically, and normal read/write operations cannot be performed during the refresh period. This is because, for example, when a certain memory cell MC, ft7 is in operation, it is not possible to read the data of other memory cells connected to the bit line BL and BLIC used for the operation of this MCI. It is. Therefore, in a computer system using RAM'i,
During the period when RAM is being refreshed,
Since the RAM cannot be used even when you want to access it, you have to wait for access to the RAM during the refresh period, which increases the time it takes to access the RAM, which is a problem because it interferes with speeding up the process. Here, the operation of the dynamic RAM will be briefly described with reference to the timing waveforms shown in FIG. Address signal input changes or tick enable signal (not shown)
When input, one cycle of memory operation begins. First of all,
The bit lines BL and BL are precharged, and then the word line WL, for example, is precharged by the address signal input.

When word line WLI and dummy word line DWL are selected, the word line WLI and dummy word line DWL are respectively set to high level, and the memory cell MC1° and dummy cell DM connected to them are
Each transfer r-to-Q of C1 opens, and the respective stored information appears on the bit lines BL and BL.
, BL occurs. Next, when the sense signal SE is activated, the sense amplifier SA operates to sense and amplify the potential difference between the bit lines BL' and BL. At this point, the memory cell MCI is connected to the word line WL
, so that after the sensing operation, the memory cell MC is selected by the potential of the bit line DI.
I's stored information is refreshed. At the same time, the information on the bit lines BL, BL is transferred to the bit line selection transistor QB,
It is transmitted to data lines DL and DL via QB. The information read onto the data lines DL and DL undergoes waveform shaping etc. in the output circuit 4, and is outputted as data D after a short delay from the sensing operation. ut will be obtained.

Dynamic RAM that involves a refresh operation as described above does not impose a burden on the user, who must always keep the refresh timing in mind when designing system products, and is difficult to use. There are drawbacks. On the other hand, dynamic RAM has the advantage that it is suitable for high density storage and can be realized at low cost, since the memory cell area of the dynamic RAM is usually only 1.4 mm compared to static RAM that does not involve refresh operations.

Therefore, in order to prevent the user from being aware of the refresh operation even though it is accompanied by a refresh operation, the normal operation and the refresh operation are changed at different times so that the user can use it as if it were a static RAM. A pseudo-static RAM built to perform partitioning has been proposed. An overview of the operation of this pseudo-static RAM will be explained with reference to FIG. This operation differs from the operation described above with reference to FIG. 6 in that (1) the selected word line (for example, W
LI) and predetermined dummy word lines (e.g. DWL,
) is driven in a ・9rus manner, (2) sense an f
sA is the bit line BL.

A sense signal SE is used to sense the potential difference generated between BL.
(3) The bit lines BL and BL are returned to their original state once within the period until the data sensed by the sense amplifier SA is completely output from the output circuit 4. The selected word line WLI is charged and then a word m (for example, WL3) other than the selected word line WLI is charged.
) and a predetermined word line (e.g. DwL*) are selected and driven in a irritating manner so that the word line W L s I
The data of the memory cell ML connected to C is read out,
The sense amplifier fsk is again driven in a h-pulse manner by the SE multiplied signal to sense the bit line potential difference, thereby rewriting (refreshing) the memory cell MC3. Note that since the data of the memory cell MC3 to be refreshed does not need to be output from the output circuit 4, this refresh operation is performed relatively quickly. That is, in the operation shown in FIG. 7, the refresh operation of another memory cell is completed temporally in parallel with the normal access operation. Note that in the above operation example, cell selection for refresh operation is performed υ later than cell selection for normal access operation, but conversely, even if it is performed earlier in time, there will be no extra shift in normal operation. No adverse effects will occur. In addition, in the above operation example, the K IJ refresh operation is completely completed before the read data from the normal access operation is output from the output circuit 4, but if the refresh operation takes some time, the normal access time If it is determined that the pseudo-static method, in which the user does not see (or does not need to worry about) the refresh operation, has a great advantage even if it worsens the refresh operation, this method can be adopted. Furthermore, the time it takes for the word line selected for the refresh operation to return to the unselected state is longer than the time it takes for the word line selected for the normal access operation to return to the unselected state. Good too.

Further, in the above operation example, word line selection is performed twice within one memory cycle to perform refresh, but refresh does not necessarily have to be performed in each cycle.

The reason for this is that the refresh only needs to be performed once for each memory cell within a short period of time.
, BI, all of which happen to be shared memory cells MCI are accessed, so word line selection is performed twice within a cycle. If this is not the case, that is, if the RAM is not being accessed when refreshing is attempted, it is sufficient to simply perform refreshing.

[Problems with background technology]

By the way, since there is a delay in the data lines DL and DL due to the large stray capacitance CD, it takes quite a long time to drive the data lines DL and DL. While driving DL, the sense amplifier sA performs the following work (flessy operation in the above example)
I can't move on.

If the operation of the sense amplifier SA is slow in this manner, the cycle time will be slow if two ports are to be operated during the sense amplifier 5Ail cycle as described above.

[Purpose of the invention]

This invention has been made in view of the circumstances mentioned in section 2 of the present invention, and it is possible to quickly speed up the sensing operation by the sense amplifier by about 100%, and even if the cycle time is short, the sense amplifier is fully driven at least twice during one cycle The object of the present invention is to provide a sense amplifier system for a semiconductor memory device that can perform the following functions.

[Summary of the invention]

That is, the sense amplifier system of the semiconductor memory device of the present invention is provided with a latch circuit that latches the output of the sense amplifier, and all of the plurality of latch circuits are connected to the data line via a switch circuit, so that the sense amplifier and This is characterized in that a switch circuit on the sense amplifier output side is provided between the latch circuit and the sense amplifier output side. Therefore, after all of the first information sensed by the sense amplifier is latched by the latch circuit, the switch circuit on the output side of the sense amplifier is turned off to allow the sense amplifier to sense the second information. Become.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 schematically shows a part of a semiconductor memory integrated circuit.
A21-SAzar... is a sense amplifier, and each fo4ded bit extends in the same direction.
1ine configuration first bit line pair (BL, BLtt
) ~ (BL12 + BLxz) # ... and (BL211 BLzx) ”'(B]44 +
BLz4) r..., and each of these bit lines has a bit line BL shown in FIG.

Similar to BL, a plurality of memory cells of a memory cell block and one dummy cell are connected.

LAI is a child circuit and the sense amplifier SA,
! .

SAI! A switch circuit 5111312 is provided between the latch input terminal and each output terminal of the sense antenna fS All + S A12. In the same manner as above, the latch circuit LA1. and the switch circuit S13 are
゜S14 is provided, sense amplifier 5A21 * 5A
A child circuit LA21 and a switch circuit S21*822 are provided corresponding to the sense amplifier 5A23r.
A latch circuit LA22 and a switch circuit Sxs*Sza are provided corresponding to SAxa.

On the other hand, 2 B Tr 1 #j BL 1 is connected to the bit lines (B Lll * n Ll 1 ) to (BL
A second bit line pair (a kind of data line pair) provided in parallel on both sides of 2BL
z, 2BLz are the pit lines (BLzx r BL
zt) to (BL24 r BL24)1... are the second bit line pairs provided in parallel on both sides. The connection between the bit line pair 2BL1.2BLI and the output terminal of each of the latch circuits L A41 * L Ax z + . Switch circuit 25 for control
ill 281g+...), the bit line pairs 2BL, 2BL.

and the latch circuit L A21 r located inside thereof.
A switch circuit 2 for controlling the connection between each latch output terminal of the ``A 22 r...'' by controlling the column decoder output and controlling the switch S' 2112 S22 +
...is provided.

2S A, is the second bit line pair 2B L, l,
A second sense amplifier is connected to 2BL1, and is connected to the data line pair DL, DL via a switch circuit 2S1f. Similarly 1. ? SA2 is the second bit line pair 2BL2 . 2BLs, and is connected to the data line pair DL, DL via the switch circuits 2S and 2BLs. 4 is the second sense amplifier connected to the data line pair D.
Output circuit connected to L, DL, CB + C2B +
CD is each wiring capacitance.

Next, an example of the operation of the above memory will be explained. During a normal read operation, for example, the bit line pair B L 1 r
When sensing all the information of 13 L1, the above information is first sensed and amplified by the sense amplifier SAl1. At this time, the sense amplifier SA1. The switch circuit Sll between the latch circuit LAII and the latch circuit LAII may be closed or open, but the other switch circuit S12+2811 connected to the latch circuit LA11 is open, and the sensing operation of the sense amplifier 5AII is completed at the latest. At this time, the switch circuit Sll is closed and all the data in the sense amplifier SAi is transferred to the child circuit LAII and latched.

After this, even if the switch circuit 5AII is opened, the latch circuit L
A1t is latching data. Then, the switch circuits 2SIlb and 2S1 are closed, and the second bit line pair 2BL1*2BLx and the data lines DL, DL are driven by the latch circuit LA port, and the bit lines 2BI,
, 2BL, information is the second sense Anne; y'2sAt
The sense is amplified by The output of this sense amplifier 2SAI is sent to a data line pair DL via a switch circuit 2Slk.

The signal is read out to the output circuit 4 via the DL.

In the above operation, in order for the latch circuit CAl1 to drive the second bit lines 2BL1, . . . YBLt, the large wiring capacitances CB and CD must be charged and discharged, which increases the required time. However, this latch circuit LA1
．． Even when driving the second bit line 2B Ll +2BLl and the data lines DL and DL, if the switch circuit Sll between the child circuit LAl and the sense amplifier SAl is opened in this way, the above Sense amplifier 5AII is connected to data line DL.

It can be operated freely without adversely affecting the DL. Therefore, if normal read data is first latched into the latch circuit cA11 by the sense amplifier fsA, .
The next refresh operation for the memory cells connected to L3s can be performed. That is, the latch circuit LAIl is a heavy load on the second bit line 2BLl.
, 2BLx and the data pulses DL, DT can fully incorporate the above refresh operation.

Note that in the above-described operation), the one-cycle intermittent sense amplifier 5AII can be used once for a normal read operation and the other time for a refresh operation. In this case, during the refresh operation, there is no need to read the data read into the sense amplifier 5AII to the output circuit 4, so the sense amplifier SA! .

There is no need to transfer all data to the latch circuit CAII.

Further, the output circuit 4 normally has a latch function and latches only the read data for the normal operation.

FIG. 2 shows a representative example of a part of the bit line group, sense 777 group, circuit group, and switch circuit group. Here, the sense amplifier 5AII has a pair of sense signals SE, and similarly to the drive transistor Kanakura MO8 type sense amplifier p1 controlled by the SE, the latch circuit LAII also has a pair of latch signals LE,
Drive transistor t controlled by L and E including tr
The 28th switch circuit is composed of a CMO8 type O8 circuit, and the switch circuit Sll is an N-channel transistor controlled by the switch signal φ1.
It consists of an N-channel transistor controlled by.

Although the above embodiment shows a memory with a folded hit 1ine type configuration, FIG. 3 shows a part of the case where the present invention is fully applied to a memory with an open bit 1ine type configuration. Here, the latch circuit LAII' has a latch input terminal connected to the output terminal of the sense amplifier 5AII via the switch circuit S, and a latch output terminal connected to the switch circuit "dlr".
2 S tl”e via one second bit line 2BL
Connected to 1. Similarly, latch circuit CA1. ' is connected to the sense amplifier 7'5AIZ via the switch circuit StX and to the second bit line 2BI, ] via the switch circuit 281z''e), and the other latch circuit L A2 (' .

LA2. '... also connects the switch circuit S2 between the corresponding sense amplifiers 5Azt, 5Azz+... in the same way as above.
1°S22. ... is connected, and the switch circuit 2S 2
1' 12S2j... through the second bit line, ? B
Connected to L2.

In the above memory, for example, sense antenna 7'5A1
After the 1st sense operation, 9ch circuit LA11 is applied to the sense data.
By latching to ' and opening the switch circuit Sll, the latch circuit CA,1' becomes the second bit l1lli12
BL! And the data line DL connected to this via the switch circuit 2Slf! While J1 is operating, the sense amplifier 7'5Axti"l can freely perform the next refresh operation. Note that the latch circuit CAI
Since the data latched by , ' is a signal of @1# or 0#, it is sufficient to use only one bit line and r-twilight line of the broom 2 as in the above example, instead of a pair of each.

Note that the present invention is not limited to a memory that performs a normal read operation and a refresh operation during one cycle as described above, but can also be applied to a general memory for the purpose of speeding up a sense amplifier. In this case, the first sense operation in one cycle is used to read data by accessing the first address, and after latching this first read data, it is output from the data line. While the signal is being transmitted to the circuit, it may be disconnected from the sense unff latch circuit and left free, and used for data reading by the next second address access. In this way, the sensing of the subsequent data is completed during the signal delay on the data line, so pipelined or parallel control is possible. On the other hand, it appears as if the sense time is zero. In other words, high-speed operation is possible when reading several consecutive pieces of data.

〔Effect of the invention〕

As described above, the sense amplifier system of the semiconductor memory device of the present invention includes a latch circuit between the sense amplifier and the data line, and determines the timing relationship between the connection between the latch circuit and the sense amplifier and the connection between the latch circuit and the data line. By appropriately setting the sense amplifier, the speed of the sense amplifier can be increased, and even if the cycle time is short, sensing operations can be performed two or more times in one cycle. Therefore, it is particularly suitable for a pseudo-static memory in which a normal operation and a refresh operation are performed in a time-division manner within one cycle.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a part of a semiconductor memory according to an embodiment of the present invention, and Fig. 2 shows a specific example of a part of the circuit shown in Fig. 1. 3 is a block diagram showing a part of a semiconductor memory according to another embodiment of the present invention, FIG. 4 is a block diagram showing a part of a conventional semiconductor memory, and FIG. 5 is a block diagram showing a part of a conventional semiconductor memory. A diagram showing the time relationship between normal operation and refresh operation in the memory, FIG. 6 is a diagram showing an example of the operation in the memory of FIG. 4, and FIG. FIG. 4 is a timing diagram showing an example of operation in a memory. B I11! -B L14 *B Lt
l-B L14 , , B Lzl ~B
L24 r B L21-B Lzi-bit line, 2B
L1+2B L I T 2 B L 2 e 2
BL Go...2nd bit line (7J-Yuu line), DL
, DL...data line, S All. S A 12 r S A 211 S A22-Sense amplifier, LA11 + LA 12 + LA 2!
+ LA 22・LA1t'+ LAtz'+L
A2i'+ L Azz'...Latch circuit, Sxt"
St4+S21~5241 25ill 2 St
zν 2Szlr2Szzr281, 2 S2.2
S11'+ 2812'+ 2 S2i'+ 28'z
Tomi'...Switch circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 4 Figure IS Figure 6 Out Figure 7 DWL2 @ 1゜16-〇, 29F1 Patent Office Commissioner Manabu Shiga 1. Indication of the case Japanese Patent Application No. 59-163508 2. Name of the invention Sense amplifier system for semiconductor storage device 3. Relationship with the Nagisa case to be amended Patent applicant (307) Toshiba Corporation 4, Agent. 7, nlr positive content +11 Akii] 1st page 12th line 20th to 1st of nlr
On page 3, page 1, ``column decoder output'' is corrected to ``row decoder output''. (2) In the 5th and 6th lines of page 13 of detailed layer 1'', the phrase ``column decoder output'' is corrected to ``wax yarn decoder output.''

Claims (3)

[Claims] (1) A sense amplifier that senses and amplifies information on the bit line of the memory cell array, a latch circuit that latches the output of this sense amplifier, and a column decoder output that is connected between the plurality of latch circuits and the data line. a switch circuit to be controlled; and a sense amplifier output side switch circuit connected between the sense amplifier and the latch circuit, the first switch circuit being controlled by the sense amplifier.
After the latch circuit latches the information, the switch circuit on the output side of the sense amplifier is controlled to be in an OFF state so that the sense amplifier can sense the second information. system. (2) The sense amplifier for a semiconductor memory device according to claim 1, wherein the first information is obtained by a normal read operation, and the second information is obtained by a refresh operation. system. (3) A sense amplifier system for a semiconductor memory device according to claim 1, wherein the bit line is divided into a large number of parts.