JP2544371B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2544371B2 JP2544371B2 JP62040287A JP4028787A JP2544371B2 JP 2544371 B2 JP2544371 B2 JP 2544371B2 JP 62040287 A JP62040287 A JP 62040287A JP 4028787 A JP4028787 A JP 4028787A JP 2544371 B2 JP2544371 B2 JP 2544371B2
- Authority
- JP
- Japan
- Prior art keywords
- tab
- resin
- semiconductor device
- island
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 239000011347 resin Substances 0.000 claims description 80
- 229920005989 resin Polymers 0.000 claims description 80
- 239000000853 adhesive Substances 0.000 claims description 24
- 230000001070 adhesive effect Effects 0.000 claims description 24
- 239000007767 bonding agent Substances 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000000725 suspension Substances 0.000 claims description 3
- 230000035882 stress Effects 0.000 description 27
- 229910000679 solder Inorganic materials 0.000 description 21
- 238000000034 method Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 238000012360 testing method Methods 0.000 description 9
- 238000005336 cracking Methods 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に係り、特に、ダイボンデング時
あるいは基板への面付実装時に受ける応力によるクラツ
ク等を防止するに好適な樹脂封止型の半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a resin-sealed type suitable for preventing cracks or the like due to stress received during die bonding or surface mounting on a substrate. The present invention relates to a semiconductor device.
樹脂封止型の半導体装置では従来のピン挿入タイプに
代わり、基板に直接リードを半田付けする面付実装タイ
プが主流になりつつある。このようなパケージでは、高
温高湿環境下で保存すると樹脂が水分を吸収し、半田付
加熱時(リフロー時)に水分がタブと樹脂部との界面で
蒸気になり、タブ下面コーナ部にクラツクが生じ易い。
このクラツクは半田リフロー時に発生する為、俗にリフ
ロークラツクと呼ばれる。In the resin-sealed semiconductor device, a surface mounting type in which leads are directly soldered to a substrate is becoming the mainstream instead of the conventional pin insertion type. In such a package, when stored in a high temperature and high humidity environment, the resin absorbs moisture, and when heat is applied to the solder (during reflow), moisture becomes vapor at the interface between the tab and the resin portion, and cracks occur at the corners on the lower surface of the tab. Is likely to occur.
This crack is commonly called a reflow crack because it occurs during solder reflow.
このようなリフロークラツクを防止する従来技術とし
ては特開昭60−208847号公報に記載のようにパッケージ
の裏面に穴をあけ、発生する蒸気を逃がす方法がある。As a conventional technique for preventing such a reflow crack, there is a method of making a hole in the back surface of the package and letting the generated vapor escape, as described in JP-A-60-208847.
また樹脂部とタブの界面の接着強さを向上させ、すき
まを防止する技術として、タブの反素子搭載面に凹凸を
設ける方法として、特開昭58−199548号公報、同60−18
6044号公報に示される技術、更にタブに穴を形成したも
のとして同59−16357号公報に記載の技術がある。Further, as a technique for improving the adhesive strength at the interface between the resin portion and the tab and preventing the clearance, as a method of providing unevenness on the anti-element mounting surface of the tab, there is disclosed in JP-A-58-199548 and 60-18.
There is a technique disclosed in JP-A-6044 and a technique described in JP-A-59-16357 in which holes are formed in tabs.
上記従来技術のうち、パツケージ下面に穴をあける方
法は、リフロークラツクは防げるもののパツケージ外部
と内部に水分の通路を作ることになり、チツプ電極の腐
食が生じる可能性がある。Among the above-mentioned conventional techniques, the method of forming a hole in the lower surface of the package can prevent the reflow crack, but creates a moisture passage inside and outside the package, which may lead to corrosion of the chip electrode.
また、タブの反素子搭載面に単純な凹凸を設ける方法
はタブと樹脂との接着面内の変位を拘束する効果はある
ものの、両者を引き離す方向の変位については、凹部に
入り込んだ樹脂部が簡単に抜けるために効果が期待でき
ない。Further, although the method of providing a simple unevenness on the anti-element mounting surface of the tab has the effect of restraining the displacement within the bonding surface between the tab and the resin, the displacement in the direction separating the two causes the resin portion that has entered the concave portion to The effect cannot be expected because it is easily removed.
特開昭59−16357号公報ではタブの一部を抜き去り、
この部分に樹脂を充填することにより熱応力による剥離
を防ぐことともに等価的に樹脂部の厚さが増大すること
によつて耐湿性の向上がある程度は図れる。しかし、リ
フロー半田付け時の蒸気圧により、樹脂部がタブから剥
離した場合に生ずる変形によつて最大応力発生箇所の応
力はタブの一部が抜き去られない場合と大差なく、この
構造ではリフロー半田付けの際の樹脂部割れに対する効
果は望めない。In JP-A-59-16357, a part of the tab is removed,
By filling this portion with resin, peeling due to thermal stress is prevented, and the thickness of the resin portion is equivalently increased, so that the moisture resistance can be improved to some extent. However, due to the vapor pressure generated during reflow soldering, the stress at the point where maximum stress occurs due to the deformation that occurs when the resin part separates from the tab is not much different from the case where part of the tab cannot be removed. The effect of cracking the resin part during soldering cannot be expected.
ダンボンデング時或はその後の温度履歴による素子破
壊を防止するため、低膨張係数のリードフレーム材を用
いるとか、低弾性係数のダイボンデング剤を用いるとか
の従来技術による方法は材料の選択範囲を限定させ、原
価高を招き、しかも半田リフロークラツクに対してはほ
とんど効果が期待できない。In order to prevent element destruction due to temperature history during or after damboning, conventional methods such as using a lead frame material with a low expansion coefficient or using a die bonding agent with a low elasticity coefficient limit the selection range of materials, It causes high cost, and almost no effect can be expected for solder reflow crack.
温度サイクル試験によるタブ下端部の樹脂部のクラツ
ク発生を防止するためのデインプル加工処理は効果があ
る場合も多いが、リードフレーム材と樹脂材の線膨張係
数差が大きい場合には、デンプル加工穴に充填された樹
脂凸部の突起付根部で樹脂クラツクを生じ易い難点があ
る。The dimple processing to prevent cracking of the resin at the bottom edge of the tab due to the temperature cycle test is often effective, but if there is a large difference in the linear expansion coefficient between the lead frame material and the resin material, the dimple processing hole is used. There is a problem in that resin cracks are likely to occur at the roots of the protrusions of the resin protrusions filled in.
半田リフロークラツクに対する防止策として、パッケ
ージ表面から、タブの反素子側に達する小穴を明ける方
法は、小孔を通じて水分が容易にタブ/樹脂部の接着界
面、更には素子表面まで達するため、長期間使用してい
るとアルミ(Al)配線腐食などの故障を生ずる恐れが出
てくるなど耐湿性を低下させる難点がある。温度サイク
ルによるタブ下端部樹脂クラツクに対しては何の効果も
期待できない。As a measure to prevent solder reflow cracks, the method of opening a small hole from the package surface to the side opposite to the element of the tab is because the moisture easily reaches the adhesive interface between the tab / resin part and the element surface through the small hole. If it is used for a certain period of time, there is a problem that the moisture resistance is lowered, such as the risk of aluminum (Al) wiring corrosion and other failures. No effect can be expected on the resin crack at the lower end of the tab due to the temperature cycle.
本発明の目的は、ダンボンデング時、或いはその後の
温度履歴による半導体素子の破壊を生じにくく、温度サ
イクル試験によるタブ下端部樹脂クラツクに対しても強
く、しかも高い耐半田リフロークラツク性を有する半導
体装置を提供することにある。It is an object of the present invention to prevent a semiconductor element from being damaged by a temperature history during or after dampening, to be resistant to a resin crack at a lower end of a tab by a temperature cycle test, and to have a high solder reflow crack resistance. To provide.
上記目的はタブが接着剤搭載部、素子支持部及び両者
を結ぶリードより構成されているリードフレームを用
い、接着剤搭載部においてのみタブと半導体素子を接着
させることにより達成される。The above object is achieved by using a lead frame in which the tab is composed of an adhesive mounting portion, an element supporting portion and leads connecting the both, and adhering the tab and the semiconductor element only in the adhesive mounting portion.
本願第1番目の発明は、半導体素子とこの半導体素子
を搭載するタブと、このタブに連なるタブ吊リードを含
むリード群とを具備し、これらを樹脂で封止すると共
に、樹脂部から露出したリードの先端を曲げた面付実装
タイプのものにおいて、タブを周辺の環状部と中央のア
イランド部とに分割し、アイランド部を環状部にて支障
すべく環状部の一部にて一体に接続し、半導体素子はア
イランド部上に接着剤を介して間接に搭載せしめる一方
環状部の素子搭載面上には直接若しくは間隙部(空間
部)を介して搭載せしめるようにしたことを特徴とす
る。A first invention of the present application includes a semiconductor element, a tab on which the semiconductor element is mounted, and a lead group including a tab suspension lead connected to the tab, which are sealed with resin and exposed from a resin portion. In the surface mounting type with the tip of the lead bent, the tab is divided into a peripheral annular part and a central island part, and the island part is integrally connected at a part of the annular part to prevent it from interfering. The semiconductor element is indirectly mounted on the island portion via an adhesive, while the semiconductor element is directly mounted on the element mounting surface of the annular portion or via a gap portion (space portion).
また本願第2番目の発明は、第1番目と同様の前提に
おいて、タブを半導体素子接着用接着剤塗布部(要する
にアイランド部)とそれ以外の部分(環状部、リード群
等)とに分割することを特徴とする。Further, in the second invention of the present application, on the same premise as in the first invention, the tab is divided into a semiconductor element bonding adhesive application portion (in short, an island portion) and other portions (annular portion, lead group, etc.). It is characterized by
更に本願第3番目の発明は、第1番目と同様の前提に
おいて、前記タブの接着剤塗布領域を半導体底面よりも
小さくしたことを特徴とする。Furthermore, the third invention of the present application is characterized in that, on the same premise as in the first invention, the adhesive application region of the tab is made smaller than the semiconductor bottom face.
いずれにせよ本発明においてはタブの素子側表面積が
反素子側表面積よりも小さくなるようにタブの板厚方向
にテーパを形成することが好ましい。またアイランド部
の周辺にはボンデイング剤流出防止用の溝を形成するこ
とが好ましい。In any case, in the present invention, it is preferable to form the taper in the plate thickness direction of the tab so that the surface area of the tab on the element side is smaller than the surface area on the non-element side. Further, it is preferable to form a groove for preventing the outflow of the bonding agent around the island portion.
更にタブの素子搭載面側についてアイランド部は環状
部よりも凹んでいることが好ましい態様である。換言す
れば、接着剤搭載部表面を素子支持部表面に対してくぼ
ませて、段差を形成することが望ましい。Further, it is a preferable aspect that the island portion is recessed more than the annular portion on the element mounting surface side of the tab. In other words, it is desirable that the surface of the adhesive mounting portion is recessed with respect to the surface of the element supporting portion to form a step.
環状部の内素子搭載部分の素子側表面を他の環状部素
子側表面よりも凹ませることも望ましい。換言すればタ
ブの素子支持部において、素子を支持する部分にくぼみ
を形成する態様が好ましい。It is also desirable to make the element-side surface of the inner element mounting portion of the annular portion recessed from the other annular-element-side surface. In other words, it is preferable that the element support portion of the tab has a recess formed in a portion that supports the element.
アイランド部は1つに限らず複数に分割しても良い。
更にアイランド部の厚みは他のリード部分よりも薄くす
ることが好ましい。The island portion is not limited to one, and may be divided into a plurality.
Furthermore, it is preferable that the thickness of the island portion is thinner than that of the other lead portions.
また上記の各態様を適宜組み合わせることも一向に差
し支えない。It is also possible to combine the above-mentioned aspects appropriately.
本発明によれば、素子とタブの接着は素子中央の一部
分のみであるため、素子に発生する応力は接着部分の長
さに相当する素子の全面接着時において発生する値に概
略等しい。このため、大寸法の素子に対しても素子割れ
を起こすことがない。According to the present invention, since the element and the tab are adhered only to a part of the center of the element, the stress generated in the element is substantially equal to the value corresponding to the length of the adhered portion, which is generated when the element is entirely adhered. For this reason, element cracking does not occur even for large-sized elements.
温度サイクル試験によるタブ下端部の樹脂クラツクに
対してはタブの環状部とアイランド部との間が開いてお
りこの部分に充填される樹脂によつてタブ反素子面と樹
脂との相対すべりが阻止される。そこでタブ下端部の発
生応力は低く抑えられるから樹脂クラツクは防止でき
る。With respect to the resin crack at the lower end of the tab by the temperature cycle test, there is an opening between the annular part of the tab and the island part, and the resin filled in this part prevents relative slip between the tab anti-element surface and the resin. To be done. Therefore, the stress generated at the lower end of the tab can be suppressed to a low level, so that resin cracking can be prevented.
樹脂の線膨張係数はタブのそれよりも大きいので半田
リフロー時の高温下では穴明き部分の樹脂はタブ側面に
押しつけられることとなる。しかもタブ側面には形成時
に生じる凹凸の為に、たとえ樹脂と素子の接着力が不十
分で蒸気圧が加わる場合であつてもタブ側面がタブ下側
樹脂の膨れ出しを阻止することになる。ここでアイラン
ド部側面は固定支点として作用する。それ故従来のタブ
に比べて発生抑力は一層低減され、耐リフロークラツク
性が向上する。Since the linear expansion coefficient of the resin is larger than that of the tab, the resin in the holed portion is pressed against the side surface of the tab under high temperature during solder reflow. Moreover, due to the unevenness formed on the side surface of the tab, the side surface of the tab prevents the resin under the tab from bulging even if the adhesive force between the resin and the element is insufficient and vapor pressure is applied. Here, the side surface of the island portion acts as a fixed fulcrum. Therefore, compared with the conventional tab, the generation suppressing force is further reduced, and the reflow crack resistance is improved.
面付実装タイプではリフロークラツクの対策が特に重
要である。そこでタブと素子との接着面積が小さくなれ
ば、蒸気圧がかかっても面積に応じて発生応力が小さく
なる。よって樹脂との剥離や樹脂の割れを防止可能とな
る。Countermeasures against reflow cracks are especially important for surface mount type. Therefore, if the adhesion area between the tab and the element is reduced, the generated stress is reduced according to the area even if vapor pressure is applied. Therefore, peeling from the resin and cracking of the resin can be prevented.
以上述べたように、本発明によれば、ダイボンデング
時及びその後の温度履歴による素子破壊、温度サイクル
試験によるタブ下端部樹脂クラツクに強く、しかも、耐
リフロー性に優れた半導体装置を提供することができ
る。As described above, according to the present invention, it is possible to provide a semiconductor device that is resistant to element breakdown due to temperature history during and after die bonding, and is resistant to resin crack at the lower end of the tab due to a temperature cycle test, and has excellent reflow resistance. it can.
以下、本発明の実施例を図面に従つて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
尚以下に述べる。 It will be described below.
実施例の効果の算定にあたつては、従来技術として、
256KDRAMパッケージを仮想し、素子寸法4.0mm×9.0mm、
タブ寸法4.2mm×9.3mm,銅(Cu)合金製リードフレー
ム、半田によるダイボンデングを仮定する。In calculating the effect of the embodiment, as a conventional technique,
Hypothetical 256KDRAM package, element size 4.0mm × 9.0mm,
It is assumed that the tab size is 4.2 mm × 9.3 mm, the lead frame made of copper (Cu) alloy, and die bonding by soldering.
半導体素子1はタブ2の上に接着剤などを用いて固定
され、半導体素子1上の端子はタブ2の周囲に配設され
た複数のリード3と金属細線によつて電気的に接続され
ている。リードフレームタブ吊りリードを含むリード3
とタブ2から形成されており、樹脂部5によつて封止を
行つた後に、連結されていた外枠から切り離される。The semiconductor element 1 is fixed onto the tab 2 with an adhesive or the like, and the terminals on the semiconductor element 1 are electrically connected to the leads 3 arranged around the tab 2 by metal wires. There is. Lead frame tabs Leads including suspension leads 3
And the tab 2, and after being sealed by the resin portion 5, it is separated from the connected outer frame.
半導体素子1にはシリコン(Si)が用いられており、
その線膨張係数αは約3×10-6/℃である。リードフレ
ームの材料としては、通常42アロイ(α=5×10-6/
℃)あるいは銅合金(α=17×10-6/℃)などが使用さ
れ、また樹脂部5のαは20〜30×10-6/℃となつてい
る。本実施例においてはタブ2は更に中央のアイランド
部2aと、周辺部の環状部2bとに分割されている。尚符号
2cはアイランド部2aと環状部2bとを結ぶリードである。
更に第2図から明らかなように接着剤6はアイランド部
2a上にのみ適用されている。Silicon (Si) is used for the semiconductor element 1,
Its linear expansion coefficient α is about 3 × 10 -6 / ° C. The lead frame material is usually 42 alloy (α = 5 × 10 -6 /
C.) or a copper alloy (.alpha. = 17.times.10.sup.-6 / .degree. C.) is used, and .alpha. Of the resin portion 5 is 20 to 30.times.10.sup.- 6 / .degree. In this embodiment, the tab 2 is further divided into a central island portion 2a and a peripheral annular portion 2b. The code
Reference numeral 2c is a lead connecting the island portion 2a and the annular portion 2b.
Further, as is clear from FIG. 2, the adhesive 6 is the island portion.
Only applied on 2a.
従来の半導体装置においては上記のように構成する材
料の線膨張係数αが異なつているため、素子の寸法が大
型化してくると素子とタブを接合するダイボンデング時
あるいはダイボンデング後の温度履歴により、生ずる素
子割れ、半導体装置樹脂封止後の冷却や温度サイクル試
験時に生ずるタブ下端部レジンクラツクが問題となつ
た。また、長期間空中に放置した半導体装置を基板に面
付実装すると、樹脂クラツク(半田リフロー時樹脂クラ
ークと呼ぶ)が生じることがある。以下に、それぞれの
故障モードの内容について説明する。In the conventional semiconductor device, since the linear expansion coefficient α of the material configured as described above is different, it occurs due to the temperature history during die bonding or after die bonding for joining the element and the tab as the size of the element increases. Problems such as element cracks and resin cracks at the lower end of the tab that occur during cooling after the resin sealing of the semiconductor device and in the temperature cycle test have become problems. Further, when a semiconductor device left in the air for a long period of time is surface-mounted on a substrate, a resin crack (called a resin clerk during solder reflow) may occur. The contents of each failure mode will be described below.
ダイボンデング時には、半導体素子の線膨張係数とタ
ブ材の線膨張係数が異るため、熱応力が発生し、接着剤
が降伏すると、ダイボンデング後の温度履歴により、素
子表面に引張応力が発生する。At the time of die bonding, since the linear expansion coefficient of the semiconductor element and the linear expansion coefficient of the tab material are different, thermal stress is generated, and when the adhesive yields, tensile stress is generated on the element surface due to the temperature history after die bonding.
〔文献I志田、坂本、保川、超LSIパッケージ設計用ソ
フトウエア、電子材料1982年別冊、29〕この引張応力は
銅(Cu)リードフレーム、95Pn−5Sn半田材の場合、第1
5図に示すようになる。素子寸法が大きくなるにつれて
引張応力は増大し、素子の破壊強度を越えるケースが出
てくる。このため、低膨張係数のFe−Ni系リードフレー
ム材を用いるとか、超低弾性のダイボンデング剤を用い
て素子に発生する応力を低減させるなどの方策がとられ
る。[Reference I Shida, Sakamoto, Yasukawa, VLSI package design software, electronic materials 1982 supplement, 29] This tensile stress is the first in the case of a copper (Cu) lead frame and 95Pn-5Sn solder material.
It becomes as shown in Fig. 5. The tensile stress increases as the element size increases, and in some cases, the fracture strength of the element is exceeded. For this reason, measures such as using a Fe-Ni lead frame material having a low expansion coefficient and reducing stress generated in the element by using an ultra-low elasticity die bonding agent are taken.
温度サイクル試験によるタブ下端部樹脂クラツクはリ
ードフレーム材とレジン材の線膨張係数の差異により、
タブ下端部に応力が集中するため発生するとくに、タブ
の反素子側と樹脂側にはく離が生ずると、第16図に一例
を示すように、タブ下端部の応力がステツプ状に増加
し、それらはタブサイズ(チツプサイズ)が大きくなる
につれて急増し、樹脂クラツクを発生させる。タブ下端
部樹脂クラツクを防止する方法としては前記の如く例え
ば、タブの反素子側に穴を設け(デンプル加工と呼ぶ)
樹脂をその穴に充填させてタブと樹脂部のはく離による
相対すべりを阻止する方策がとられている。Due to the difference in the linear expansion coefficient between the lead frame material and the resin material,
The stress is concentrated on the lower end of the tab. Especially, when the anti-element side and the resin side of the tab are separated from each other, the stress at the lower end of the tab increases stepwise as shown in an example in FIG. Rapidly increases as the tab size (chip size) increases, causing resin cracks. As a method for preventing the resin crack at the lower end of the tab, as described above, for example, a hole is provided on the side opposite to the element of the tab (referred to as dimple processing).
A measure is taken to prevent the relative slip due to the peeling between the tab and the resin portion by filling the hole with resin.
半導体装置を、実際の基板に実装する際にはリードの
半田接続部と基板の接続部を半田ペースト等で仮付け
し、基板全体を赤外線リフロー炉あるいはベーパリフロ
ー炉中において、例えば200〜250℃で数十秒〜数分加熱
することにより、半田接合させ、基板への実装を完了さ
せる。これを半田リフロー工程と呼んでいる。When mounting the semiconductor device on the actual board, the solder connection part of the lead and the connection part of the board are temporarily attached with solder paste, etc., and the entire board is heated in an infrared reflow furnace or vapor reflow furnace, for example, 200 to 250 ° C. By heating for several tens of seconds to several minutes, solder joining is performed and mounting on the board is completed. This is called a solder reflow process.
ところが、半導体装置製造後、長期間、大気環境中に
放置したものや、短期間であつても、比較的湿度の高い
環境中に保管しておいた半導体装置を用いて上記リフロ
ーを行うと、半田リフロー工程中に樹脂クラツクが発生
することがある。However, after the semiconductor device is manufactured, if the reflow is performed using a semiconductor device that has been left in an atmospheric environment for a long period of time, or even for a short period of time, the semiconductor device stored in an environment of relatively high humidity, Resin cracks may occur during the solder reflow process.
これは、次の理由による。即ち半導体装置保管中に樹
脂が空気中の水分を吸収し、樹脂中或いは樹脂部とタブ
接着界面のわずかのすき間に水分がたまる。吸湿した半
導体装置を半田リフロー工程に入れると、急加熱によつ
て樹脂/タブ界面の水分が蒸気となつて膨張し、その蒸
気圧によつて大きな樹脂応力が発生する。接着界面に水
分がなくとも、樹脂中の水分が拡散して接着界面に濃縮
される為、同様の樹脂応力が生ずる。This is for the following reason. That is, the resin absorbs moisture in the air during storage of the semiconductor device, and moisture accumulates in the resin or in a slight gap between the resin portion and the tab bonding interface. When a semiconductor device that has absorbed moisture is put into a solder reflow process, the water on the resin / tab interface expands into steam due to rapid heating, and a large resin stress is generated due to the steam pressure. Even if there is no water at the adhesive interface, the water in the resin diffuses and is concentrated at the adhesive interface, so that similar resin stress occurs.
第13図は、一般的なリードフレームを使用した樹脂封
止型半導体装置の断面図である。第13図において、タブ
2の反素子搭載面の樹脂接着界面15に蒸気圧が作用して
いる場合に発生する応力は文献II〔南部、石黒、耐熱性
薄膜プラスチツクパツケージの開発、沖電気研究開発、
第128号、VOL,52,No.4,P75〕に記載があるように、第14
図に示す4辺が固定されている長方形板の等分布荷重で
モデル化することによつて求めることができる。その際
の最大応力σmaxは長辺の両端部中央に発生し、その値
は次式で与えられる。FIG. 13 is a sectional view of a resin-sealed semiconductor device using a general lead frame. In Fig. 13, the stress generated when the vapor pressure is acting on the resin bonding interface 15 on the anti-element mounting surface of the tab 2 is shown in Reference II [Southern, Ishiguro, Development of heat-resistant thin film plastic package, Oki Electric R & D ,
No. 128, VOL, 52, No. 4, P75],
It can be obtained by modeling with a uniformly distributed load of a rectangular plate whose four sides are fixed as shown in the figure. The maximum stress σ max at that time occurs at the center of both ends of the long side, and its value is given by the following equation.
ここで、Pは等分布荷重、aはタブ短辺の長さ、hは
樹脂の厚さ、βは長辺と短辺との長さの比で与えられる
係数を表わす。(1)式から明らかなように、タブサイ
ズaの2乗で発生応力は増加する。従つて、素子寸法が
大きくなると、半田リフロークラツク第13図16が生じ易
くなる。 Here, P is a uniformly distributed load, a is the length of the short side of the tab, h is the thickness of the resin, and β is a coefficient given by the ratio of the length of the long side to the short side. As is clear from the equation (1), the generated stress increases with the square of the tab size a. Therefore, as the element size increases, the solder reflow cracks shown in FIG. 13 are likely to occur.
しかるに本発明の実施例においては第1図及び第2図
に示す通りアイランド部2aと環状部2bとにタブ2が分か
れている。それ故、ダイボンデング時には、アイランド
部2aにのみ接着剤をぬり、環状部2bには素子をタブ2上
に安定して設置できるための安定板の役割を与える。ま
ず、素子割れに対する改善効果を検討する。素子割れは
チツプの長辺中央部で生じることが多いので、素子寸法
の代表値として長辺の寸法をとつて9mm□を仮定し、こ
れを中央部の2mm□のみで接着するとすれば、従来の全
面接着型のものに比し、素子に発生する応力を第15図よ
り60%にすることができる。However, in the embodiment of the present invention, as shown in FIGS. 1 and 2, the tab 2 is divided into the island portion 2a and the annular portion 2b. Therefore, at the time of die bonding, the adhesive is applied only to the island portion 2a, and the annular portion 2b serves as a stabilizer for stably mounting the element on the tab 2. First, the improvement effect on element cracking will be examined. Element breakage often occurs at the center of the long side of the chip, so assuming the dimension of the long side to be 9 mm □ as a typical value of the element size, and assuming that only 2 mm □ at the center is used for bonding, The stress generated in the element can be reduced to 60% as shown in FIG.
ダイボンデング後、モールド工程を経て、パツケージ
が製造れるが、次に温度サイクル試験によるタブ下端部
樹脂クラツクにつき検討する。タブ下端部の樹脂クラツ
クはタブ短辺の中央部で生じることが多いので、タブ幅
4.2mmを用いる。第16図において、タブ幅4.2mmのものを
考え、従来技術としてタブの反素子側と樹脂との相対す
べり有りか、本実施例により相対すべり無しになつたと
すると、タブ下端部樹脂応力を38%にすることができ
る。After die bonding, a package is manufactured through a molding process. Next, a resin crack at the lower end of the tab by a temperature cycle test will be examined. Since the resin crack at the bottom of the tab often occurs at the center of the short side of the tab, the tab width
Use 4.2 mm. In FIG. 16, considering a tab width of 4.2 mm, if there is relative slip between the element opposite the side of the tab and the resin as in the prior art, or if there is no relative slip according to this embodiment, the resin stress at the lower end of the tab is 38 Can be%.
最後に、半田リフローに対する効果を試算してみる。
従来技術のタブ寸法4.3mm×9.3mmに対し、本実施例にお
いて、素子裏面と樹脂界面が剥離したと仮定し、剥離部
の短辺長さを2.4mm、長辺長さを2.6mmとすると、(1)
式の値は 従来のタブにおいて β=0.5 α=4.2mm 本実施例のタブでは β=0.33 α=2.4mm となり、本実施例による半導体装置の最大応力σmaxの
値は従来装置の約22%に低下する。樹脂の破壊強度が変
わらないとすれば、耐圧は4.6倍増加する。Finally, we will try to calculate the effect on solder reflow.
In contrast to the tab size of 4.3 mm x 9.3 mm of the conventional technology, in this example, assuming that the back surface of the element and the resin interface are peeled off, and the short side length of the peeled portion is 2.4 mm and the long side length is 2.6 mm. , (1)
The value of the formula is β = 0.5 α = 4.2 mm in the conventional tab and β = 0.33 α = 2.4 mm in the tab of the present embodiment, and the maximum stress σ max of the semiconductor device according to the present embodiment is about 22% that of the conventional device. Fall to. If the breaking strength of the resin does not change, the breakdown voltage will increase by 4.6 times.
以上述べたように、本実施例によれば、素子割れ、温
度サイクル試験によるタブ下端部樹脂クラツク、半田リ
フロークラツクに対し、大幅な強度向上を達成すること
ができる。As described above, according to the present embodiment, it is possible to significantly improve the strength against cracking of the element, resin crack at the lower end of the tab by the temperature cycle test, and solder reflow crack.
このように温度サイクル試験によるタブ下端部樹脂ク
ラツクに対しては、第2図7のタブを抜いた部分に充填
されている樹脂によつてタブの反素子側と樹脂の相対す
べりが阻止されるため、タブ下端部の発生応力を低く抑
えることができ、樹脂クラツクを防止できる。As described above, with respect to the resin crack at the lower end portion of the tab by the temperature cycle test, the resin filled in the portion where the tab is removed in FIG. 2 prevents relative slip between the anti-element side of the tab and the resin. Therefore, the stress generated at the lower end of the tab can be suppressed to a low level, and resin cracking can be prevented.
樹脂の線膨張係数はタブのそれよりも大きい為、半田
リフロー時の高温になると、第2図7に示す穴明き部分
に充填された樹脂はタブ側面8に押しつけられる。しか
も、タブ側面には、形成時に生じる凹凸のため、たと
え、第2図9の樹脂と素子の接着力が不十分で蒸気圧が
加わる場合においても第2図8のタブ側面がタブ下側樹
脂の膨れ出しを阻止する。第2図8は固定支点として作
用する。従つて、従来のタブに対して(1)式のaは十
分小さくなつて発生応力は一層低減され、耐リフローク
ラツク性が向上するのである。Since the linear expansion coefficient of the resin is larger than that of the tab, the resin filled in the perforated portion shown in FIG. 2 is pressed against the tab side surface 8 when the temperature becomes high during solder reflow. In addition, since the tab side surface is uneven during the formation, even if the adhesive force between the resin and the element of FIG. 2 is insufficient and vapor pressure is applied, the tab side surface of FIG. Prevent the bulge of. 2 FIG. 8 acts as a fixed fulcrum. Therefore, a in the formula (1) is sufficiently smaller than that of the conventional tab, so that the generated stress is further reduced and the reflow crack resistance is improved.
第3図〜第12図に別の実施例を示す。第3図はタブの
板厚方向のテーパ10を設け、樹脂のタブから膨れ出しを
より強固に阻止したものである。第4図は接着剤搭載部
の外周に溝を設け、接着剤の流出を防止した構造であ
る。溝の寸法としては、例えば、幅0.2mm,深さ0.2mm程
度にすればよい。Another embodiment is shown in FIGS. In FIG. 3, a taper 10 in the plate thickness direction of the tab is provided to more firmly prevent the resin tab from bulging. FIG. 4 shows a structure in which a groove is provided on the outer periphery of the adhesive mounting portion to prevent the adhesive from flowing out. The groove may have a width of 0.2 mm and a depth of 0.2 mm, for example.
第5図,第6図は素子支持部表面と接着剤搭載部表面
に段差12、δを設けたものである。素子と素子支持部の
すき間を最小に抑えると同時に、接着剤の厚みを制御す
ることができる。δとしては10μm〜50μm程度がよ
い。5 and 6 show steps 12 and δ provided on the surface of the element supporting portion and the surface of the adhesive mounting portion. The thickness of the adhesive can be controlled while minimizing the gap between the element and the element supporting portion. δ is preferably about 10 μm to 50 μm.
第7図,第8図は素子支持部において、素子を支持す
る部分にくぼみ13を設け、素子の位置決めを容易にした
ものである。FIG. 7 and FIG. 8 show an element supporting portion provided with a recess 13 in a portion for supporting the element to facilitate positioning of the element.
第9図は接着剤搭載部のリードの厚み14を支持部の厚
みよりも薄くしたものである。これにより、素子に発生
する応力をさらに低く抑えることができる。In FIG. 9, the lead thickness 14 of the adhesive mounting portion is made thinner than that of the supporting portion. As a result, the stress generated in the element can be further suppressed.
第11図,第12図は素子搭載部を2個設けたものであ
る。このように、必要に応じ素子搭載部を複数個設けて
もよい。11 and 12 show two element mounting portions provided. As described above, a plurality of element mounting portions may be provided if necessary.
これらの実施例は、それぞれ単独で実施してもよい
し、いくつかを組合せて実施してもよい。These examples may be carried out individually or in combination.
以上の各実施例によれば、素子とタブを接合するダイ
ボンデングにおいて、素子中央部の一部分のみを接合す
るため、ダイボンデング或いはその後に発生する温度履
歴による素子発生応力が小さくでき素子の破壊が防止で
きる。According to each of the above embodiments, in die bonding for joining the element and the tab, only a part of the element central portion is joined, so that the element generated stress due to the die bonding or the temperature history generated thereafter can be reduced and the element can be prevented from being broken. .
タブに形成された穴に樹脂が充填されて凸部が形成さ
れるため、タブの反素子側と樹脂との接着部の相対すべ
りが生じない。それ故タブ下端部樹脂応力が低減でき、
温度サイクル寿命を大幅に向上できる。Since the hole formed in the tab is filled with the resin to form the convex portion, relative slippage of the adhesive portion between the resin on the opposite side of the tab and the resin does not occur. Therefore, the resin stress at the bottom of the tab can be reduced,
The temperature cycle life can be greatly improved.
更に、タブに形成された穴の側面が半田リフロー時の
蒸気圧による樹脂の膨れ出しを阻止するため、耐リフロ
ークラツク性を大幅に向上できる。Further, the side surface of the hole formed in the tab prevents the resin from bulging due to vapor pressure during solder reflow, so that the reflow crack resistance can be greatly improved.
以上説明した如く、本発明によればダイボンデイング
時或いはその後の温度履歴による半導体素子の破壊を生
じにくく、温度サイクル試験によるタブ下端部樹脂クラ
ツクに対しても強く、しかも高い耐半田リフロークラツ
ク性を有する半導体装置が得られるという効果がある。As described above, according to the present invention, the semiconductor element is less likely to be damaged by the temperature history during or after die bonding, is resistant to the resin crack at the lower end of the tab by the temperature cycle test, and has high solder reflow crack resistance. There is an effect that a semiconductor device having is obtained.
第1図,第4図,第6図,第8図,第10図,第12図は夫
々本発明の実施例に係る半導体装置タブの平面図、第2
図は第1図の断面図、第5図は第6図の断面図、第7図
は第8図の断面図、第9図は第10図の断面図、第11図は
第12図の断面図、第3図は本発明の実施例に係る半導体
装置タブの断面図、第13図は従来の樹脂封止半導体装置
の断面図、第14図は内圧を受ける半導体パツケージのモ
デル図、第15図は素子応力を示す図、第16図はタブ下レ
ジン応力を示す説明図である。 1……半導体素子、2……タブ、2a……アイランド部、
2b……環状部、2c……アイランド部〜環状部接合リー
ド、3……リード、4……金属細線、5……樹脂部、6
……接着剤、7……樹脂充填部、8……タブ側面、9…
…素子/樹脂界面、10……テーパ部、11……溝、12……
段差δ、13……くぼみ、14……アイランド板厚、15……
タブ/樹脂界面、16……半田リフロークラツク、17……
タブ下樹脂の厚さ。1, 4, 6, 8, 10 and 12 are plan views of a semiconductor device tab according to an embodiment of the present invention and FIG.
1 is a sectional view of FIG. 1, FIG. 5 is a sectional view of FIG. 6, FIG. 7 is a sectional view of FIG. 8, FIG. 9 is a sectional view of FIG. 10, and FIG. 11 is a sectional view of FIG. Sectional view, FIG. 3 is a sectional view of a semiconductor device tab according to an embodiment of the present invention, FIG. 13 is a sectional view of a conventional resin-encapsulated semiconductor device, FIG. 14 is a model diagram of a semiconductor package which receives internal pressure, FIG. 15 is a diagram showing element stress, and FIG. 16 is an explanatory diagram showing under-tab resin stress. 1 ... semiconductor element, 2 ... tab, 2a ... island part,
2b ... annular part, 2c ... island part-annular part joining lead, 3 ... lead, 4 ... metal thin wire, 5 ... resin part, 6
…… Adhesive, 7 …… Resin-filled part, 8 …… Tab side, 9…
… Element / resin interface, 10 …… tapered part, 11 …… groove, 12 ……
Step δ, 13 …… Dimple, 14 …… Island thickness, 15 ……
Tab / resin interface, 16 …… Solder reflow crack, 17 ……
Thickness of resin under the tab.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 立道 昭弘 土浦市神立町502番地 株式会社日立製 作所機械研究所内 (72)発明者 三浦 英生 土浦市神立町502番地 株式会社日立製 作所機械研究所内 (56)参考文献 特開 昭59−16357(JP,A) 実開 昭57−4226(JP,U) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiro Tachimichi 502 Jinritsucho, Tsuchiura-shi, Hitachi Ltd. Machinery Research Laboratory (72) Inventor Hideo Miura 502 Jinchocho, Tsuchiura-shi Hitachi, Ltd. Machinery Research In-house (56) Reference JP-A-59-16357 (JP, A) Actually developed S57-4226 (JP, U)
Claims (7)
ブと、該タブに連なるタブ吊リードを含むリード群とを
具備し、これらを樹脂で封止すると共に、樹脂部から露
出したリードの先端を曲げた面付実装タイプの半導体装
置において、前記タブを周辺の環状部と中央のアイラン
ド部とに分割し、該アイランド部を前記環状部にて支持
すべく該環状部の一部にて一体に接続し、前記半導体素
子は前記アイランド部上に接着剤を介して間接に搭載せ
しめる一方前記環状部の素子搭載面上には直接若しくは
間隙部を介して搭載せしめることを特徴とする半導体装
置。1. A semiconductor element, a tab on which the semiconductor element is mounted, and a lead group including a tab suspension lead connected to the tab, the lead group being sealed with a resin, and the lead exposed from the resin portion. In a surface-mounting type semiconductor device with a bent tip, the tab is divided into a peripheral annular portion and a central island portion, and a part of the annular portion is supported by the annular portion to support the island portion. A semiconductor device, which is integrally connected, wherein the semiconductor element is indirectly mounted on the island portion via an adhesive while the semiconductor element is mounted directly on the element mounting surface of the annular portion or via a gap. .
よりも小さくなるようにタブの板厚方向にテーパを形成
することを特徴とする特許請求の範囲第1項記載の半導
体装置。2. The semiconductor device according to claim 1, wherein a taper is formed in the plate thickness direction of the tab so that the element-side surface area of the tab is smaller than the anti-element-side surface area.
流上防止用の溝を形成することを特徴とする特許請求の
範囲第1項記載の半導体装置。3. The semiconductor device according to claim 1, wherein a groove for preventing the flow of the bonding agent is formed around the island portion.
ランド部は前記環状部よりも凹んでいることを特徴とす
る特許請求の範囲第1項記載の半導体装置。4. The semiconductor device according to claim 1, wherein the island portion is recessed from the annular portion on the element mounting surface side of the tab.
を他の環状部素子側表面よりも凹ませることを特徴とす
る特許請求の範囲第1項記載の半導体装置。5. The semiconductor device according to claim 1, wherein the element-side surface of the inner element mounting portion of the annular portion is recessed more than the other element-side surface of the annular portion.
特徴とする特許請求の範囲第1項記載の半導体装置。6. The semiconductor device according to claim 1, wherein the island portion is divided into a plurality of parts.
よりも薄くすることを特徴とする特許請求の範囲第1項
記載の半導体装置。7. The semiconductor device according to claim 1, wherein the island portion is thinner than the other lead portions.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62040287A JP2544371B2 (en) | 1987-02-25 | 1987-02-25 | Semiconductor device |
US07/158,673 US4942452A (en) | 1987-02-25 | 1988-02-22 | Lead frame and semiconductor device |
US08/448,881 USRE37690E1 (en) | 1987-02-25 | 1995-05-24 | Lead frame and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62040287A JP2544371B2 (en) | 1987-02-25 | 1987-02-25 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63208261A JPS63208261A (en) | 1988-08-29 |
JP2544371B2 true JP2544371B2 (en) | 1996-10-16 |
Family
ID=12576391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62040287A Expired - Lifetime JP2544371B2 (en) | 1987-02-25 | 1987-02-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2544371B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3610787B2 (en) * | 1998-03-24 | 2005-01-19 | セイコーエプソン株式会社 | Semiconductor chip mounting structure, liquid crystal device and electronic apparatus |
JP2007194379A (en) * | 2006-01-19 | 2007-08-02 | Matsushita Electric Ind Co Ltd | Lead frame, semiconductor device, and method of manufacturing same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS574226U (en) * | 1980-06-09 | 1982-01-09 | ||
JPS5916357A (en) * | 1982-07-19 | 1984-01-27 | Nec Corp | Semiconductor device |
-
1987
- 1987-02-25 JP JP62040287A patent/JP2544371B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63208261A (en) | 1988-08-29 |
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