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JP2541391Y2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2541391Y2
JP2541391Y2 JP1990407101U JP40710190U JP2541391Y2 JP 2541391 Y2 JP2541391 Y2 JP 2541391Y2 JP 1990407101 U JP1990407101 U JP 1990407101U JP 40710190 U JP40710190 U JP 40710190U JP 2541391 Y2 JP2541391 Y2 JP 2541391Y2
Authority
JP
Japan
Prior art keywords
metal layer
opening
insulating film
aluminum
main component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1990407101U
Other languages
Japanese (ja)
Other versions
JPH0494752U (en
Inventor
博美 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP1990407101U priority Critical patent/JP2541391Y2/en
Publication of JPH0494752U publication Critical patent/JPH0494752U/ja
Application granted granted Critical
Publication of JP2541391Y2 publication Critical patent/JP2541391Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05073Single internal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【考案の詳細な説明】[Detailed description of the invention]

【0001】[0001]

【産業上の利用分野】本考案は銅系のリード細線を接続
するために好適な電極を備えた半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with electrodes suitable for connecting copper-based lead wires.

【0002】[0002]

【従来の技術及び考案が解決しようとする課題】図2に
示す従来の半導体装置は半導体基体1の表面上にシリコ
ン酸化膜等から成る絶縁膜2を有する。この絶縁膜2の
開口3を通して半導体基体1にAl(アルミニウム)か
ら成る電極4がコンタクトしている。
2. Description of the Related Art The conventional semiconductor device shown in FIG. 2 has an insulating film 2 made of a silicon oxide film or the like on the surface of a semiconductor substrate 1. An electrode 4 made of Al (aluminum) is in contact with the semiconductor substrate 1 through the opening 3 of the insulating film 2.

【0003】ところで、近年、Cu(銅)から成るリー
ド細線の実用化が進んでいる。Cuリード細線は、Au
(金)リード細線と同様にワイヤボンディングの方向性
に制約を受けないボールボンディング(ネイルヘッドボ
ンディング)が可能である上、Auに比較して安価であ
る利点がある。ところが、Cuリード細線は周知のとお
りAuリード細線に比べてボール部分が硬く形成される
ためこれを上記のAl電極4にボールボンディングする
と、Al電極4は押し潰されて肉薄化され易い。図2に
はCuリード細線5をボンディングすることによって点
線の位置にあったAl電極4が実線の位置まで薄くなっ
た状態が示されている。このため、Cuリード細線5の
Cu成分が肉薄化したAl電極4を介して半導体領域1
に拡散し、Al電極4の半導体領域1に対するオーミッ
クコンタクト(低抵抗性接触)が悪くなる。これを解決
する手段としてAl電極4を肉厚に形成することが考え
られるが、Al電極4を厚くするとエッチングの精度が
低下するので、Cuの拡散を防止することができるほど
Al電極4を厚くすることは困難である。
In recent years, practical use of lead wires made of Cu (copper) has been advanced. Cu lead wire is Au
(Gold) Ball bonding (nail head bonding) can be performed without being restricted by the directionality of wire bonding as in the case of fine lead wires, and there is an advantage that it is less expensive than Au. However, as is well known, the ball portion of the Cu lead thin wire is formed to be harder than the Au lead thin wire, so that when this is ball-bonded to the Al electrode 4, the Al electrode 4 is easily crushed and thinned. FIG. 2 shows a state in which the Al electrode 4 at the position indicated by the dotted line is thinned to the position indicated by the solid line by bonding the Cu lead fine wire 5. Therefore, the semiconductor region 1 is connected via the Al electrode 4 in which the Cu component of the Cu lead thin wire 5 is thinned.
And the ohmic contact (low-resistance contact) of the Al electrode 4 to the semiconductor region 1 becomes worse. As a means for solving this problem, it is conceivable to form the Al electrode 4 to have a large thickness. However, if the Al electrode 4 is made thicker, the accuracy of etching is reduced. Therefore, the Al electrode 4 is so thick that diffusion of Cu can be prevented. It is difficult to do.

【0004】そこで、本考案の目的はCu等の拡散を防
ぐことができる電極構造を有する半導体装置を提供する
ことにある。
Accordingly, an object of the present invention is to provide a semiconductor device having an electrode structure capable of preventing diffusion of Cu or the like.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
の本考案は、半導体基体と、前記半導体基体上に形成さ
れ且つ開口を有している絶縁膜と、前記半導体基体の前
記開口によって露出された表面上に形成され且つ前記絶
縁膜の上には延在しないように形成されたアルミニウム
(Al)又はアルミニウム(Al)を主成分とする物質
から成る第1の金属層と、前記第1の金属層の上に形成
され且つ前記開口との間に間隙が生じるように前記開口
よりも小さく形成されたチタン(Ti)又はチタン(T
i)を主成分とする物質又はモリブデン(Mo)又はモ
リブデン(Mo)を主成分とする物質から成る第2の金
属層と、前記第2の金属層の上及び側面を覆うように
形成され且つ前記絶縁膜の上に延在するように形成され
アルミニウム(Al)又はアルミニウム(Al)を主
成分とする物質から成る第3の金属層と、ボールボンデ
ィング部を有し、このボールボンディング部が前記絶縁
膜の上には延在しないように前記第1、第2及び第3の
金属層積層領域上に接続されているリード線とを備え
た半導体装置に係わるものである。なお、請求項2に示
すように請求項1における第2の金属層と第3の金属層
との間に更にアルミニウム(Al)又はこれを主成分と
する金属層を配設することができる。 請求項1及び2の
考案と実施例との対応は次の通りである。請求項1の第
1、第2及び第3の金属層は図3の第1第2及び第3の
金属層14a、14b、14cであり、請求項2の第
1、第2、第3及び第4の金属層は 図1の第、第2、第
3及び第4の金属層6a、6b、6c、6dである。
In order to achieve the above object, the present invention provides a semiconductor substrate and a semiconductor substrate formed on the semiconductor substrate.
An insulating film having an opening and an opening in front of the semiconductor substrate .
Formed on the surface exposed by the opening and
A first metal layer made of a material mainly composed of aluminum is formed so as not to extend (Al) or aluminum (Al) is formed on the Enmaku, and formed on said first metal layer The opening so that a gap is formed between the opening and the opening.
Titanium, which is smaller than (Ti) or titanium (T
a second metal layer made materials or molybdenum (Mo) or molybdenum (Mo) of a material whose main component is the i) as a main component, is formed to cover the surface and a side surface of the second metal layer And formed so as to extend on the insulating film.
A third metal layer made of aluminum (Al) or a material containing aluminum (Al) as a main component ;
A ball bonding part, and the ball bonding part
The present invention relates to a semiconductor device including a lead wire connected to a stacked region of the first, second, and third metal layers so as not to extend over the film . In addition, as shown in claim 2,
As described above, aluminum (Al) or a metal layer containing aluminum (Al) as a main component can be further provided between the second metal layer and the third metal layer in the first aspect . Claims 1 and 2
The correspondence between the device and the embodiment is as follows. Claim 1
The first, second and third metal layers correspond to the first, second and third metal layers of FIG.
3. The metal layers 14a, 14b, 14c,
The first, second, third and fourth metal layers correspond to the first, second,
Third and fourth metal layers 6a, 6b, 6c, 6d.

【0006】[0006]

【考案の作用及び効果】本願の請求項1の考案は次の作[Operation and effect of the invention] The invention of claim 1 of the present application is as follows.
用及び効果を有する。Use and effect. (イ) チタン又はモリブデンから成る第2の金属層(B) Second metal layer made of titanium or molybdenum
は、リード線の構成物質が第1の金属層及び半導体基体Means that the constituent materials of the lead wire are the first metal layer and the semiconductor substrate
に拡散することを阻止する拡散阻止層としての機能を有Function as a diffusion blocking layer to prevent diffusion into
する。従って、リード線の構成物質の第1の金属層及びI do. Therefore, the first metal layer of the constituent material of the lead wire and
半導体基体への拡散によるオーミックコンタクトの悪化Deterioration of ohmic contact due to diffusion into semiconductor substrate
を防ぐことができる。Can be prevented. (ロ) 第1及び第2の金属層は絶縁膜の開口の中に配(B) The first and second metal layers are arranged in the opening of the insulating film.
置され、第3の金属層は絶縁膜の上に延在するように形And a third metal layer is formed to extend over the insulating film.
成され、チタン又はモリブデンから成る第2の金属層はAnd a second metal layer of titanium or molybdenum
上面のみならず側面も第3の金属層によって覆われていNot only the top surface but also the side surfaces are covered with the third metal layer
る。従って、第2の金属層の酸化又はエッチング液によYou. Therefore, the oxidation of the second metal layer or the etching solution
る侵蝕を良好に防ぐことができる。Erosion can be satisfactorily prevented. (ハ) 第1及び第2の金属層は絶縁膜の開口の中に配(C) disposing the first and second metal layers in the opening of the insulating film;
置されているので、絶縁膜の開口の縁における第3の金The third metal at the edge of the opening of the insulating film.
属層の段差が小さくなり、第3の金属層の段切れが発生The step of the metal layer becomes small, and the step of the third metal layer occurs.
し難い。Difficult to do. (ニ) リード線のボールボンディング部は絶縁膜の上(D) The ball bonding part of the lead wire is on the insulating film
に延在しないように第1及び第2の金属層が積層されてThe first and second metal layers are laminated so as not to extend
いる領域の上に設けられるので、リード線のボンディンOn the lead wire
グによる絶縁膜の破壊が生じない。The breakdown of the insulating film due to the bug does not occur. また、請求項2の考Further, according to claim 2
案は、請求項1と同一の作用効果を有する他に、次の作The plan has the same functions and effects as those of claim 1, and
用効果を有する。It has an effect. (ホ) 請求項2における第3の金属層は、第2の金属(E) The third metal layer according to claim 2 is a second metal layer.
層に連続した蒸着により形成し、同時に所定形状にエッThe layers are formed by continuous evaporation and
チングすることによって得ることが可能になる。従っIt can be obtained by ching. Follow
て、酸化しやすい第2の金属層を第3の金属層で直ちにAnd immediately oxidizes the second metal layer which is easily oxidized by the third metal layer.
覆うことにより第2の金属層の酸化を良好に防ぐことがBy covering, the oxidation of the second metal layer can be prevented well.
できる。it can. (ヘ) ボールボンディング部の下が第1、第2、第3(F) The first, second and third parts are below the ball bonding part.
及び第4の金属層の積層領域となり、この領域の厚さをAnd a fourth metal layer stacking region, and the thickness of this region is
請求項1の考案のこれに対応する領域の厚さよりも厚くThicker than the corresponding region of the invention of claim 1
することができ、ボールボンディングによる第1及び第The first and the second by ball bonding
2の金属層及び半導体基体の破壊または劣化をより確実More reliable destruction or deterioration of metal layer 2 and semiconductor substrate
に防ぐことができる。Can be prevented.

【0007】[0007]

【第1の実施例】次に、図1を参照して本考案の第1の
実施例に係わる半導体装置を説明する。本実施例の半導
体装置は、シリコン半導体基体1と、この上面に形成さ
れた絶縁膜2と、絶縁膜2の開口3を通じて半導体基体
1にコンタクトする多層構造の電極6を具備する。電極
6は、半導体基体1側から順番にAl(アルミニウム)
から成る厚さ約1.0μmの第1の金属層6aと、Ti
(チタン)から成る厚さ約5000オングストロームの
第2の金属層6bと、Alから成る厚さ約1.0μmの
第3の金属層6cと、Alから成る厚さ約3.0μmの
第4の金属層6dを有する。第1の金属層6aと第2の
金属層6bと第3の金属層6cは低圧雰囲気を維持した
中で蒸着物質をAl、Ti、Alに順次切換える方法、
いわゆる連続蒸着方法で半導体基体1の上面全体に形成
した後に、その外周側をエッチング除去して形成する。
第1の金属層6aと第2の金属層6bと第3の金属層6
cは平面的に見て開口3の内側に形成する。第4の金属
層6dは第3の金属層6cの上面、第1、第2及び第3
の金属層6a、6b、6cの側面、開口3から露出して
いる半導体基体1の表面、及び絶縁膜2の上面を覆うよ
うにAl膜を真空蒸着で形成してからその外周側をエッ
チングで除去して得る。第4の金属層6dは、開口3の
外側の絶縁層2の上面まで延在している。
First Embodiment Next, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. The semiconductor device of this embodiment includes a silicon semiconductor substrate 1, an insulating film 2 formed on the upper surface thereof, and a multi-layered electrode 6 that contacts the semiconductor substrate 1 through an opening 3 of the insulating film 2. The electrodes 6 are made of Al (aluminum) in order from the semiconductor substrate 1 side.
A first metal layer 6a of about 1.0 μm
A second metal layer 6b of about 5000 angstroms of (titanium), a third metal layer 6c of about 1.0 μm of Al, and a fourth metal layer of about 3.0 μm of Al It has a metal layer 6d. A method in which the first metal layer 6a, the second metal layer 6b, and the third metal layer 6c are sequentially switched to Al, Ti, and Al while maintaining a low-pressure atmosphere;
After being formed on the entire upper surface of the semiconductor substrate 1 by a so-called continuous vapor deposition method, the outer peripheral side thereof is removed by etching.
First metal layer 6a, second metal layer 6b, and third metal layer 6
c is formed inside the opening 3 when viewed in plan. The fourth metal layer 6d is formed on the upper surface of the third metal layer 6c, the first, second and third metal layers.
An Al film is formed by vacuum deposition so as to cover the side surfaces of the metal layers 6a, 6b, and 6c, the surface of the semiconductor substrate 1 exposed from the opening 3, and the upper surface of the insulating film 2, and the outer peripheral side is etched. Remove and get. The fourth metal layer 6 d extends to the upper surface of the insulating layer 2 outside the opening 3.

【0008】Cuから成るリード細線5は、ボンディン
グパッド部分即ち平面的に見て開口3の内側で第1の金
属層6aと第2の金属層6bと第3の金属層6cが形成
された部分の上方に位置するように第4の金属層6dに
ボールボンディングされている。リード細線5はその先
端部を加熱して球状とし、これを電極6に押し潰して接
続するので、リード細線5の接続によって電極6の内の
Alから成る第1、第3及び第4の金属層6a、6c、
6dは押し潰されて薄くなる。しかし、Alに比べて硬
いTiから成る第2の金属層6bは第1、第3及び第4
の金属層6a、6c、6dに比べて潰れ難い。
The fine lead wire 5 made of Cu is a bonding pad portion, that is, a portion where the first metal layer 6a, the second metal layer 6b, and the third metal layer 6c are formed inside the opening 3 in plan view. Is ball-bonded to the fourth metal layer 6d so as to be located above. The lead wire 5 is heated at its tip to form a sphere, which is crushed and connected to the electrode 6, so that the connection of the lead wire 5 allows the first, third, and fourth metals made of Al in the electrode 6 to be connected. Layers 6a, 6c,
6d is crushed and thinned. However, the second metal layer 6b made of Ti, which is harder than Al, has the first, third, and fourth metal layers.
Hardly crushed as compared with the metal layers 6a, 6c and 6d.

【0009】本実施例は次の効果を有する。 (1) ボンディングパッド部分にTiから成る第2の
金属層6bが介在し、これがリード細線5のCu成分の
拡散を抑制するバリアとして機能するから、電極6と半
導体基体1とのオーミックコンタクトが良好にとれる。
特に、高温環境下で使用した場合、従来ではオーミック
性が低下し易かったが、本実施例ではこれが改善され
る。 (2) Tiから成る第2の金属層6bは酸化され易い
が、本実施例では第1、第2及び第3の金属層6a、6
b、6cが連続して真空蒸着されるので、この問題が解
消されている。 (3) 第1、第2及び第3の金属層6a、6b、6c
が開口3の内側に形成されるので、ステップカバレッジ
が悪いTiから成る第2の金属層6bの段切れが生じな
い。即ち、第1、第2及び第3の金属層6a、6b、6
cを開口3の外側の絶縁膜3の上面まで延在させても上
記(1)の効果は得られるが、このように形成すると第
2の金属層6bが絶縁膜2の開口3側をはい上る部分に
段切れが生じ易い。第2の金属層6bに段切れが生じる
と、この部分で第1の金属層6aと第3の金属層6cと
の間に空間が形成され易い。この空間にエッチング液が
浸入すると、第1、第2及び第3の金属層6a、6b、
6cが所望しない状態にエッチングされることがある。
本実施例では、このようなことを防ぐことができる。(4) Cuの拡散阻止機能を有する第2の金属層6b
の上面は第3の金属層6cで被覆され、側面が第4の金
属層6dで被覆されているので、第2の金属層6bの上
面のみならず側面も酸化又はエッチング液等から保護す
ることができる。 (5) 第3の金属層6cによって第4の金属層6dの
補強効果を得ることができ、リード線5のボールボンデ
ィング部による第1及び第2の金属層6a、6b及び半
導体基体1に対するストレスを軽減することができる。 (6) リード線5のボールボンディング部は絶縁膜2
の上に延在していないので、絶縁膜2を破壊しない。
This embodiment has the following effects. (1) Since the second metal layer 6b made of Ti is interposed in the bonding pad portion and functions as a barrier for suppressing the diffusion of the Cu component of the fine lead wire 5, the ohmic contact between the electrode 6 and the semiconductor substrate 1 is good. Can be taken.
In particular, when used in a high-temperature environment, the ohmic property has conventionally tended to decrease, but in the present embodiment, this is improved. (2) Although the second metal layer 6b made of Ti is easily oxidized, the first, second and third metal layers 6a and 6
This problem is solved because b and 6c are continuously vacuum-deposited. (3) First, second and third metal layers 6a, 6b, 6c
Is formed inside the opening 3, so that the step of the second metal layer 6b made of Ti having poor step coverage does not occur. That is, the first, second, and third metal layers 6a, 6b, 6
Although the effect (1) described above can be obtained even if c is extended to the upper surface of the insulating film 3 outside the opening 3, the second metal layer 6b is formed on the opening 3 side of the insulating film 2 when formed in this manner. Step breakage is likely to occur in the ascending part. When the second metal layer 6b is disconnected, a space is easily formed between the first metal layer 6a and the third metal layer 6c at this portion. When the etchant enters this space, the first, second and third metal layers 6a, 6b,
6c may be etched in an undesired state.
In the present embodiment, such a situation can be prevented. (4) Second metal layer 6b having Cu diffusion blocking function
Is covered with a third metal layer 6c, and the side surface is made of a fourth metal layer.
Since the second metal layer 6b is covered with the metal layer 6d,
Protect not only the surface but also the side surface from oxidation or etchant etc.
Can be (5) The fourth metal layer 6d is formed by the third metal layer 6c.
The reinforcing effect can be obtained and the ball bond of the lead wire 5 can be obtained.
The first and second metal layers 6a, 6b and half
Stress on the conductor base 1 can be reduced. (6) The ball bonding portion of the lead wire 5 is the insulating film 2
Does not extend over the insulating film 2, so that the insulating film 2 is not broken.

【0010】[0010]

【第2の実施例】次に、図3を参照して第2の実施例に
係わる半導体装置を説明する。図3の半導体装置は、シ
リコン半導体基体11と、この上面に形成された絶縁膜
12と、絶縁膜12の開口13を通じて半導体基体11
に接触する3層構造の電極14と、電極14に接続され
たリード細線15を具備する。電極14は半導体基体1
1側から順番にAlから成る厚さ約1.0μmの第1の
金属層14aと、Mo(モリブデン)から成る厚さ約
0.3μmの第2の金属層14bと、Alから成る厚さ
約3μmの第3の金属層14cから成る。第1の金属層
14aと第2の金属層14bは低圧雰囲気を維持した中
で蒸発物質を順次AlとMoに切換える方法、いわゆる
連続蒸着法で半導体基体11の上面全体にAl層とMo
層を重ねて形成してから、この金属層の外周側をエッチ
ング除去して得る。第1の金属層14aと第2の金属層
14bは平面的に見て開口13の内側に配設されてい
る。第3の金属層14cは第1及び第2の金属層14
a、14bを形成した後、第2の金属層14aの上面、
第1及び第2の金属層14a、14bの側面、開口13
に露出する半導体基体11の表面及び絶縁膜12の上面
を覆うようにAl層を真空蒸着してから、このAl層の
外周側をエッチング除去して得る。第3の金属層14c
は平面的に見て開口13の外側まで延在して、第1及び
第2の金属層14a、14bを被覆している。
Second Embodiment Next, a semiconductor device according to a second embodiment will be described with reference to FIG. The semiconductor device shown in FIG. 3 includes a silicon semiconductor substrate 11, an insulating film 12 formed on an upper surface thereof, and an opening 13 in the insulating film 12.
And a thin lead wire 15 connected to the electrode 14. The electrode 14 is the semiconductor substrate 1
A first metal layer 14a made of Al and having a thickness of about 1.0 μm, a second metal layer 14b made of Mo (molybdenum) having a thickness of about 0.3 μm, and a thickness of Al The third metal layer 14c has a thickness of 3 μm. The first metal layer 14a and the second metal layer 14b are formed on the entire upper surface of the semiconductor substrate 11 by a method of sequentially switching the evaporation material to Al and Mo while maintaining a low-pressure atmosphere, that is, a continuous evaporation method.
After the layers are formed in layers, the outer peripheral side of the metal layer is removed by etching. The first metal layer 14a and the second metal layer 14b are provided inside the opening 13 in plan view. The third metal layer 14c includes the first and second metal layers 14c.
a, 14b, after forming the upper surface of the second metal layer 14a,
Side surfaces of first and second metal layers 14a and 14b, opening 13
An Al layer is vacuum-deposited so as to cover the surface of the semiconductor substrate 11 and the upper surface of the insulating film 12, which are exposed to the outside, and then the outer peripheral side of the Al layer is removed by etching. Third metal layer 14c
Extends to the outside of the opening 13 in plan view, and covers the first and second metal layers 14a and 14b.

【0011】リード細線15はCuから成り、電極14
のボンディングパッド領域、即ち、第1の金属層14a
と第2の金属層14bと第3の金属層14cが縦方向に
積層された領域にボールボンディングされている。この
ボールボンディングを行う時には、リード細線15の先
端部分を加熱して球状部(ボール)を形成し、これを電
極14に対して垂直方向に押し付けて接続する。このた
め、リード細線15のボールボンディング部15aを形
成すると、電極14は従来例と同様に潰されて肉薄化す
る。
The lead wire 15 is made of Cu, and the electrode 14
Bonding pad region, that is, the first metal layer 14a
And a second metal layer 14b and a third metal layer 14c are ball-bonded to a region where the metal layers are vertically stacked. this
When performing ball bonding, the distal end portion of the fine lead wire 15 is heated to form a spherical portion (ball) , which is pressed against the electrode 14 in the vertical direction to be connected. Therefore, the ball bonding portion 15a of the fine lead 15 is formed.
Then, the electrode 14 is crushed and thinned as in the conventional example.

【0012】本実施例は次の効果を有する。 (1) 電極14のボンディングパッド領域の下方にM
oから成る第2の金属層14bが介在し、これがリード
細線15のCu成分が下方に拡散するのを抑制する。こ
のため、電極14の半導体領域11に対するオーミック
コンタクトが良好にとれる。特に高温環境の下で使用し
た場合、従来例では、このCu拡散に起因するオーミッ
ク性の低下が生じ易かったが、本実施例ではこの問題が
解消される。 (2) 第1及び第2の金属層14a、14bが第3の
金属層14cによって被覆されているから、信頼性の高
い電極構造となっている。即ち、第1、第2及び第3の
金属層14a、14b、14cを連続蒸着して、これら
金属層の外周側を一度にエッチング除去して形成された
電極であっても、上記(1)の効果は得られる。しかし
ながら、MoはAlに比べてリン酸系のエッチング液に
対するエッチレートが早いため、エッチング断面に段差
が生じる。この段差部分は保護樹脂等で被覆することが
困難であるため、水分等の有害物質が侵入し易く、特性
劣化の原因となる。本実施例では、第2の金属層14b
の側面が第3の金属層14cで被覆され、電極14の側
面に段差が生じないので、この問題が解消されている。 (3) Moから成る第2の金属層14bは上面のみな
らず、側面も第3の金属層14cで被覆されているの
で、第2の金属層14bの上面のみならず側面も酸化ま
たはエッチング液等から保護することができる。 (4) 第1及び第2の金属層14a、14bは絶縁膜
12の開口13の中に配置されているので、絶縁膜12
の開口13の縁における第3の金属層14cの段差が小
さくなり、この段切れが発生し難い。 (5) リード線15のボールボンティング部15aは
絶縁膜12の上に延在しないので、絶縁膜12を損傷さ
せることがない。
This embodiment has the following effects. (1) M is provided below the bonding pad region of the electrode 14.
The second metal layer 14b made of o intervenes, and this suppresses the Cu component of the fine lead wire 15 from diffusing downward. Therefore, an ohmic contact between the electrode 14 and the semiconductor region 11 can be made well. In particular, when used in a high-temperature environment, in the conventional example, the reduction in ohmic properties due to the Cu diffusion was apt to occur, but this embodiment solves this problem. (2) Since the first and second metal layers 14a and 14b are covered with the third metal layer 14c, a highly reliable electrode structure is provided. That is, even if the electrode is formed by continuously depositing the first, second and third metal layers 14a, 14b and 14c and etching away the outer peripheral side of these metal layers at once, the above (1) The effect is obtained. However, since Mo has a higher etch rate with respect to a phosphoric acid-based etchant than Al, a step occurs in an etched cross section. Since it is difficult to cover the step portion with a protective resin or the like, harmful substances such as moisture easily enter and cause deterioration of characteristics. In the present embodiment, the second metal layer 14b
Is covered with the third metal layer 14c, and no step is formed on the side surface of the electrode 14, so that this problem is solved. (3) Since the second metal layer 14b made of Mo is covered not only with the top surface but also with the side surface with the third metal layer 14c, not only the top surface but also the side surface of the second metal layer 14b is oxidized or etched. Etc. can be protected. (4) Since the first and second metal layers 14a and 14b are arranged in the opening 13 of the insulating film 12, the insulating film 12
The step of the third metal layer 14c at the edge of the opening 13 becomes small, and this step is hardly generated. (5) Since the ball bonding portion 15a of the lead wire 15 does not extend over the insulating film 12, the insulating film 12 is not damaged.

【0013】[0013]

【変形例】本考案は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 (1) 第2の金属層6b、14bの厚さを変えること
ができる。しかし、Tiの場合の第2の金属層6bはC
u成分の下方への侵入を有効に防止するために3000
オングストローム以上に設定すべきである。またMoの
場合は0.1μm以上に設定すべきである。
[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The thickness of the second metal layers 6b and 14b can be changed. However, the second metal layer 6b in the case of Ti is C
In order to effectively prevent the u component from penetrating downward, 3000
Should be set to angstrom or higher. In the case of Mo, it should be set to 0.1 μm or more.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施例の半導体装置の一部を示す断面図
である。
FIG. 1 is a sectional view showing a part of a semiconductor device according to a first embodiment.

【図2】従来の半導体装置の一部を示す断面図である。FIG. 2 is a cross-sectional view showing a part of a conventional semiconductor device.

【図3】第2の実施例の半導体装置の一部を示す断面図
である。
FIG. 3 is a sectional view showing a part of the semiconductor device according to a second embodiment;

【符号の説明】[Explanation of symbols]

1 半導体基体 2 絶縁膜 3 開口 6 電極 6a 第1の金属層 6b 第2の金属層 6c 第3の金属層 6d 第4の金属層 DESCRIPTION OF SYMBOLS 1 Semiconductor base 2 Insulating film 3 Opening 6 Electrode 6a 1st metal layer 6b 2nd metal layer 6c 3rd metal layer 6d 4th metal layer

Claims (2)

(57)【実用新案登録請求の範囲】(57) [Scope of request for utility model registration] 【請求項1】 半導体基体と、前記半導体基体上に形成され且つ開口を有している絶縁
膜と、 前記半導体基体の前記開口によって露出された表面上に
形成され且つ前記絶縁膜の上には延在しないように形成
されたアルミニウム(Al)又はアルミニウム(Al)
を主成分とする物質から成る第1の金属層と、 前記第1の金属層の上に形成され且つ前記開口との間に
間隙が生じるように前記開口よりも小さく形成された
タン(Ti)又はチタン(Ti)を主成分とする物質又
はモリブデン(Mo)又はモリブデン(Mo)を主成分
とする物質から成る第2の金属層と、 前記第2の金属層の上及び側面を覆うように形成され
且つ前記絶縁膜の上に延在するように形成されたアルミ
ニウム(Al)又はアルミニウム(Al)を主成分とす
る物質から成る第3の金属層と、ボールボンディング部を有し、このボールボンディング
部が前記絶縁膜の上には延在しないように 前記第1、第
2及び第3の金属層積層領域上に接続されているリー
ド線とを備えた半導体装置。
A semiconductor substrate and an insulation formed on the semiconductor substrate and having an opening.
A film, formed on the surface of the semiconductor substrate exposed by the opening, and formed so as not to extend on the insulating film.
Aluminum (Al) or aluminum (Al)
A first metal layer made of a material having, as a main component, a first metal layer formed on the first metal layer and between the first metal layer and the opening;
From titanium (Ti) or a material containing titanium (Ti) as a main component or molybdenum (Mo) or a material containing molybdenum (Mo) as a main component, formed smaller than the opening so as to form a gap. a second metal layer made, are formed so as to cover the upper and side surfaces of the second metal layer
And a third metal layer formed of aluminum (Al) or a material containing aluminum (Al) as a main component formed so as to extend on the insulating film, and a ball bonding portion. This ball bonding
The first so as not to extend to the upper parts is the insulating film, a semiconductor device that includes a Li <br/> lead wires connected to the deposition area of the second and third metal layers.
【請求項2】 半導体基体と、前記半導体基体上に形成され且つ開口を有している絶縁
膜と、 前記半導体基体の前記開口によって露出された表面上に
形成され且つ前記開口との間に間隙が生じるように前記
開口よりも小さく形成され且つ前記絶縁膜の上には延在
しないように形成されたアルミニウム(Al)又はアル
ミニウム(Al)を主成分とする物質から成る第1の金
属層と、 前記第1の金属層の上に形成され且つ平面的に見て前記
第1の金属層とほぼ同じ面積を有するように形成された
チタン(Ti)又はチタン(Ti)を主成分とする物質
又はモリブデン(Mo)又はモリブデン(Mo)を主成
分とする物質から成る第2の金属層と、前記第2の金属層の上に形成され且つ平面的に見て前記
第2の金属層とほぼ同じ面積を有するように形成された
アルミニウム又はアルミニウムを主成分とする物質から
成る第3の金属層と、 前記第3の金属層の上及び前記第1、第2、第3の金
属層の側面を覆うように形成され且つ前記絶縁膜の上に
延在するように形成されたアルミニウム(Al)又はア
ルミニウム(Al)を主成分とする物質から成る第4の
金属層と、ボールボンディング部を有し、このボールボンディング
部が前記絶縁膜の上には延在しないように 前記第1、第
2、第3及び第4の金属層積層領域上に接続されてい
リード線とを備えた半導体装置。
2. A semiconductor substrate and an insulation formed on the semiconductor substrate and having an opening.
A film and a surface exposed by the opening of the semiconductor substrate.
So that a gap is formed between the opening and the opening.
Formed smaller than the opening and extending over the insulating film
A first metal layer made of aluminum (Al) or a material containing aluminum (Al) as a main component formed so as not to be formed; and a first metal layer formed on the first metal layer and viewed in plan.
Titanium (Ti) or a material containing titanium (Ti) as a main component or molybdenum (Mo) or a material containing molybdenum (Mo) as a main component formed so as to have substantially the same area as the first metal layer. A second metal layer made of a material; and a second metal layer formed on the second metal layer and viewed in plan.
Formed to have approximately the same area as the second metal layer
From aluminum or substances containing aluminum as the main component
The third metal layer, said third upper surface and the first metal layer, the second, third gold comprising
And formed on the insulating film so as to cover the side surfaces of the metal layer.
A fourth metal layer formed of aluminum (Al) or a material containing aluminum (Al) as a main component formed so as to extend, and a ball bonding portion;
The first so as not to extend to the upper parts is the insulating film, the second, is connected to the deposition area of the third and fourth metal layers Tei
Semiconductor device having a lead wire that.
JP1990407101U 1990-12-29 1990-12-29 Semiconductor device Expired - Fee Related JP2541391Y2 (en)

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Application Number Priority Date Filing Date Title
JP1990407101U JP2541391Y2 (en) 1990-12-29 1990-12-29 Semiconductor device

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JPH0494752U JPH0494752U (en) 1992-08-17
JP2541391Y2 true JP2541391Y2 (en) 1997-07-16

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Publication number Priority date Publication date Assignee Title
JPWO2012005073A1 (en) * 2010-07-08 2013-09-02 三菱電機株式会社 Semiconductor device, semiconductor package and manufacturing method thereof
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