JP2538232B2 - Digital servo device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a digital servo device for controlling a rotating body, particularly a cylinder motor or a capstan motor of a VTR.

(B) Prior Art As a conventional digital servo device, a device as shown in FIG. 4 is disclosed in Japanese Patent Laid-Open No. 61-94577.

In FIG. 4, (1) is a motor, which is provided with a speed detection pulse generator (1a) and a phase detection pulse generator (1b). The counter (2) is a cyclic phase reference counter which counts the signals of the reference clock signal generator (3) and is reset in synchronization with the phase reference signal input from the terminal (4) (see FIG. 5). . The two latch circuits (5) and (6) sequentially read the count values of the counter (2) in synchronization with the output (FG pulse) of the speed detection pulse generator (1a), and those values are compared by the comparator (7). ) And the difference between the two is calculated. The calculated value corresponds to the number of reference clocks existing between adjacent FG pulses, that is, the period of the FG pulse, and is input to the speed error signal calculator (8). On the other hand, the latch circuit (9) outputs the phase detection pulse generator (1b) (PG
The count value of the counter (2) is read in synchronization with the pulse. As can be seen from FIG. 5, the read value corresponds to the number of reference clocks existing between the input of the phase reference signal and the generation of the PG pulse, that is, the amount of phase shift of the motor (1) with respect to the phase reference signal. It is input to the phase error signal calculator (10).

The speed error signal calculator (8) receives the output of the comparator (7) and calculates a speed error signal having a gain and a discrimination characteristic suitable for the motor (1). The phase error signal calculator (10) receives the output of the latch circuit (9) as an input,
A phase error signal having a gain and a discrimination characteristic suitable for the motor (1) is calculated. The speed error signal and the phase error signal respectively pass through the DA converters (11) and (12) to be analog signals, and are added by the adder (13). Adder (13)
Output of the drive circuit (14) is input to the drive circuit (14), and the output of the drive circuit (14) is led to the motor (1) for speed control,
Phase control is performed.

In the comparator (7), normally two latch circuits (5)
In (6), the difference between adjacent data (count number) read in synchronization with the FG pulse is calculated. That is, as shown in FIG. 5, assuming that the counter values at the rising edges of a series of FG pulses FG ₁ and FG ₂ are N ₁ and N ₂ , N ₂ −N ₁ is calculated. However, a series of FG pulses FG ₃ and FG ₄ (counter values are N ₃ and
When the counter (2) is reset between the two like N ₄ ), the speed control cannot be performed if the comparator (7) is operating as described above. Therefore, the comparator (7) is controlled using the controller (15) that receives the FG pulse and the phase reference signal input from the terminal (4), and after the phase reference signal is generated, the next FG pulse At the rising edge, the comparator (7) calculates N ₄ + N _M −N ₃ . However, N _M is the maximum value of the counter (2).

The cycle of the FG pulse in the set speed state is set to be smaller than the cycle of the phase reference signal input from the terminal (4), and the cycle of the PG pulse in the set phase state is the same as the cycle of the phase reference signal. Is set.

The digital servo device for a general motor has been described above. Next, a specific case will be described.

When the motor (1) is a VTR cylinder motor, a vertical synchronizing signal of a video signal to be recorded as a phase reference signal is input to the terminal (4) during recording.

At the time of reproduction, if the count value of the counter (2) exceeds a predetermined value instead of inputting the vertical synchronizing signal to the terminal (4), self-reset is performed so that the cyclic cycle is the cycle of the phase reference signal at the time of reproduction. Be the same as. In this case, instead of the phase reference signal, the counter (2)
Input the control signal to notify the reset of. Also,
The counter (2) is not reset during both recording and playback.
When a certain value is preset as shown in the figure, the certain value corresponds to the DC bias value of the phase servo.

(C) Problems to be solved by the invention The timing chart shown in FIG.
Indicates that the phase is locked. However, in a so-called transient state until the phase is locked such as when the motor (1) is started, a PG pulse may be input immediately before or immediately after the counter (2) is reset. In that case, the timing of the phase reference signal, that is, the counter (2)
Although there is a slight difference between the timing at which the counter is reset and the timing at which the PG pulse is generated, the latch circuit (9) is provided before and after the counter (2) is reset.
The value that is latched in is greatly different, and the phase error signal corresponding to that value is also greatly different. An example of a timing chart in a transient state is shown in FIG. The period error of the PG pulse is slight, but the phase error signal fluctuates greatly. In such a state, the phase servo becomes unstable,
The motor (1) vibrates. When the motor (1) is a brushless motor, a large current flows through the drive circuit (14), power consumption in the drive circuit (14) increases, and there is a risk of heating.

If the counter (2) is present in the microcomputer, the problem is more likely to occur. Generally, resetting or presetting of the counter in the microcomputer is performed by interrupt processing. It goes without saying that the interrupt processing is prioritized over other processing in the microcomputer when the counter is a cyclic phase reference counter. As shown in FIG. 8, even if the PG pulse is generated at the timing A, if the counter is reset or preset at that time, the timing at which the counter count value is actually latched becomes B. I will end up. Further, the latching of the count value of the counter uses the interrupt processing by the PG pulse, and is latched at the timing as accurate as possible. However, when the microcomputer is also performing other work besides controlling the motor (1), the time from the occurrence of the PG pulse to the detection of the interrupt is not zero, so the PG pulse is generated. May be before the counter is reset, and the interrupt is detected after it is reset.

When the motor (1) is a VTR cylinder motor, the following may occur. When two VTRs are connected and dubbed, if special playback such as fast-forward playback is performed on the playback VTR, the servo of the cylinder motor of the recording VTR cannot pull in the vertical sync signal with a changed cycle,
The transient state will continue for a long time. Therefore, the abrupt change of the phase error signal is likely to occur.

(D) Means for Solving the Problems In order to solve the above problems, the present invention provides:
The phase error signal change suppressor for suppressing the change of the phase error signal to a constant value is provided in the digital servo device.

(E) Action Abrupt changes in the phase error signal are suppressed.

(F) Example An example of the present invention is shown in FIG. The same components as those in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted here. The phase error signal output from the phase error signal calculator (10) is input to the phase error signal change suppressor (16). The phase error signal change suppressor (16) uses the register A (17) and the register B (18) to process the phase error signal according to the claw chart shown in FIG. That is, the phase error signal is first input to the register A (17). Next, a value obtained by adding a constant value C to the value of the previously processed phase error signal held in the register B (18) and the value of the register A (17) are compared in magnitude. Register A
When the value of (17) is larger, the value obtained by adding the constant value C to the value of the register B (18) is input to the register A (17).
On the other hand, if it is less than or equal to the value in register A (17),
Further, the value obtained by subtracting the constant value C from the value of the register B (18) is compared with the value of the register A (17). When the value of the register A (17) is smaller, the value obtained by subtracting the constant value C from the value of the register B (18) is input to the register A (17). When the value of the register A (17) is equal to or larger than the value of the register A (17), the value of the register A (17) remains the input phase error signal. Next, register A to register B (18)
Input the value of (17) and prepare for the processing for the next phase error signal. Finally, the value of the register B (18) is output as a processed phase error signal, and its output is input to the adder (13) through the DA converter (12). Therefore, when the difference between the values of the phase error signals that are temporally adjacent to each other exceeds the constant value C, the change of the phase error signal is suppressed to the constant value C. For example, assuming that the waveform diagram A shown in FIG. 3 is the output waveform of the phase error signal calculator (10), the output waveform of the phase error signal change suppressor (16) is as shown in the waveform diagram B. The constant value C is determined in consideration of the characteristics of the motor (1) and the pull-in characteristics of the phase servo. If the constant value C is too large, the suppression effect will be small, and conversely, if it is too small, the time until the phase is pulled in will be long.

(G) Effect of the Invention According to the present invention, the disturbance of the phase servo during the so-called transition period until the motor is phase locked can be prevented, and the effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital servo device which is an embodiment of the present invention. 2 and 3 are a flow chart and a waveform diagram showing the operation of the main part in FIG. FIG. 4 is a block diagram of a conventional digital servo device, and FIGS. 5 and 6 are operation explanatory diagrams thereof. 7 and 8 are views for explaining the problems in FIG. (1) …… Motor, (1b) …… Phase detection pulse generator,
(2) …… Counter (cyclic phase reference counter), (1
0) ... phase error signal calculator, (16) ... phase error signal change suppressor, (17) ... register A, (18) ... register B.

Claims (3)

(57) [Claims] 1. In a digital servo device for a rotating body, a cyclic type phase reference counter for resetting or presetting a certain value when a phase reference pulse or a count value exceeds a predetermined value, and the cyclic type phase reference counter. A phase error signal calculator that reads out the count value for each pulse depending on the rotation of the rotating body and calculates a phase error signal using the value,
A digital servo characterized by comprising a phase error signal change suppressor for suppressing the change of the phase error signal to a constant value when the difference between the values of the phase error signals temporally adjacent to each other exceeds a constant value. apparatus. 2. The digital servo apparatus according to claim 1, wherein the cyclic phase reference counter is present in a microcomputer, and reset or preset is performed by interrupt processing. 3. The digital servo apparatus according to claim 1, wherein the cyclic phase reference counter is present in a microcomputer, and the count value is read by interrupt processing.