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JP2535645B2 - Semiconductor substrate manufacturing method - Google Patents

Semiconductor substrate manufacturing method

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Publication number
JP2535645B2
JP2535645B2 JP2106055A JP10605590A JP2535645B2 JP 2535645 B2 JP2535645 B2 JP 2535645B2 JP 2106055 A JP2106055 A JP 2106055A JP 10605590 A JP10605590 A JP 10605590A JP 2535645 B2 JP2535645 B2 JP 2535645B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor substrate
insulating film
warp
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2106055A
Other languages
Japanese (ja)
Other versions
JPH043908A (en
Inventor
隆雄 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2106055A priority Critical patent/JP2535645B2/en
Publication of JPH043908A publication Critical patent/JPH043908A/en
Application granted granted Critical
Publication of JP2535645B2 publication Critical patent/JP2535645B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔概要〕 半導体基板の製造方法に係り,特にSOI基板の製造方
法に関し, 反りの小さいSOI基板あるいは制御された反り量を持
つSOI基板の提供を目的とし, 反りのある半導体基板にその凹面から表面に結晶層を
残すほどの高加速で絶縁膜を形成するためのイオン注入
を行った後アニールを行い,内部に埋没した絶縁膜を形
成し,その絶縁膜の下を支持基板としその絶縁膜の上を
素子基板とするSOI基板を得る半導体基板の製造方法に
より構成する。
DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing an SOI substrate, which aims to provide an SOI substrate with a small warp or an SOI substrate with a controlled warp amount. The semiconductor substrate is annealed after ion implantation for forming an insulating film at a high acceleration so as to leave a crystal layer on the surface, and then an insulating film buried inside is formed. A semiconductor substrate is manufactured by a method for manufacturing an SOI substrate, which uses a supporting substrate as an element substrate on the insulating film.

〔産業上の利用分野〕[Industrial applications]

本発明は半導体基板の製造方法に係り,特にSOI基板
の製造方法に関する。
The present invention relates to a semiconductor substrate manufacturing method, and more particularly to a SOI substrate manufacturing method.

SOI基板を用いた半導体装置は,トレンチ素子分離な
どを併用することによって完全分離が可能となり,放射
線耐性の向上,ラッチアップ現象の消失,高速化の達成
といった数々の利点を有する。しかし,欠点として,SOI
基板は厚い絶縁層,例えばSiO2の絶縁層を有するため,S
i層が機械的ストレスを受けて反っていた。ウエハーの
反りは微細パターンの描画を阻害するばかりでなく,ス
トレスによって結晶欠陥を生じたり,ストレスの集中す
る部分に不要な不純物を偏析させて素子の特性を劣化さ
せる原因にもなっており,それゆえ,反りの小さいSOI
基板の製造方法の開発が望まれている。
A semiconductor device using an SOI substrate can be completely separated by using trench element separation and the like together, and has various advantages such as improved radiation resistance, elimination of latch-up phenomenon, and achievement of higher speed. However, the drawback is that SOI
Since the substrate has a thick insulating layer, such as an SiO 2 insulating layer, S
The i-layer was warped due to mechanical stress. The warp of the wafer not only hinders the drawing of a fine pattern, but also causes crystal defects due to stress, and segregates unnecessary impurities in a portion where stress is concentrated, thereby deteriorating device characteristics. Therefore, SOI with small warpage
Development of a substrate manufacturing method is desired.

〔従来の技術〕[Conventional technology]

第1図(a)乃至(c)は張合わせSOI基板における
従来の問題点を説明するための図であり,1は第1の半導
体基板,1a,1bは絶縁膜,2は第2の半導体基板,3は厚さを
減じた半導体層を表す。
FIGS. 1 (a) to 1 (c) are views for explaining conventional problems in a bonded SOI substrate, where 1 is a first semiconductor substrate, 1a and 1b are insulating films, and 2 is a second semiconductor. Substrate, 3 represents a semiconductor layer of reduced thickness.

絶縁膜1a,1bの形成された第1の半導体基板1,及び第
2の半導体基板2は張り合わせる前は反りはないが,張
り合わせた後第1の半導体基板1の表面を形削・研磨し
て絶縁層1aを除去し,厚さを減じた半導体層3を形成す
ると,厚さを減じた半導体層3が凸面になるような反り
を生じる。ウエハーの最終的な反りは素子を形成するプ
ロセスによって決まるものであり,従ってウエハーの初
期の反りはただ単に小さければよいというものではな
く,プロセスに合わせて決定しなければならないが,従
来の張合わせSOI基板の場合,絶縁膜によって反りが律
則されていて,反りを自由に制御することができなかっ
た。
The first semiconductor substrate 1 and the second semiconductor substrate 2 on which the insulating films 1a and 1b are formed do not warp before being bonded, but after the bonding, the surface of the first semiconductor substrate 1 is shaped and polished. When the insulating layer 1a is removed to form the semiconductor layer 3 with a reduced thickness, the semiconductor layer 3 with a reduced thickness has a warp such that it becomes a convex surface. The final warp of the wafer is determined by the process of forming the element, and therefore the initial warp of the wafer is not merely required to be small, but it must be determined according to the process. In the case of the SOI substrate, the warpage cannot be controlled freely because the warpage is regulated by the insulating film.

その点,Si基板単体の場合は,従来でもスライシング
工程や研削工程などで反りを自由に制御することができ
ていた。
On the other hand, in the case of a Si substrate alone, it has been possible to freely control warpage in the slicing process and grinding process.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

本発明は,従来の張り合わせSOI基板における反り原
因を考究し,反りの小さいSOI基板の製造方法あるいは
反り量を自由に制御できるSOI基板の製造方法を提供す
ることを目的とする。
An object of the present invention is to provide a method for manufacturing an SOI substrate having a small warp or a method for manufacturing an SOI substrate in which the amount of warp can be freely controlled by investigating the cause of warpage in a conventional bonded SOI substrate.

〔課題を解決するための手段〕[Means for solving the problem]

上記課題は、反りのある半導体基板4にその凹面から
表面に結晶層を残すほどの高加速で絶縁膜を形成するた
めのイオン注入を行った後アニールを行い,内部に埋没
した絶縁膜6を形成し,前記絶縁膜6の下を支持基板8,
前記絶縁膜6の上を素子基板7とするSOI基板を得る半
導体基板の製造方法によって解決される。
The above-mentioned problem is to perform annealing after performing ion implantation for forming an insulating film on the warped semiconductor substrate 4 from the concave surface at such a high acceleration as to leave a crystal layer on the surface, and then performing annealing on the buried insulating film 6. And forming a support substrate 8 under the insulating film 6,
This is solved by a method of manufacturing a semiconductor substrate, which obtains an SOI substrate having the element substrate 7 on the insulating film 6.

〔作用〕[Action]

反りのある半導体基板4にその凹面から表面に結晶層
を残すほどの高加速で絶縁膜を形成するためのイオン注
入を行った後アニールを行い,内部に埋没した絶縁膜6
を形成すると、絶縁膜6と半導体基板4の熱膨張係数の
差は,凹面の曲がりを緩和して凸面とする方向に作用す
るから,反りを小さくしたり,反り量を調節することが
可能となる。素子基板7の部分は支持基板8の部分に比
べて圧倒的に薄いから素子基板の反りに対する寄与は無
視できる。
The semiconductor substrate 4 having a warp is annealed after ion implantation for forming an insulating film from the concave surface at such a high acceleration as to leave a crystal layer on the surface, and then annealing is performed.
When the film is formed, the difference in the coefficient of thermal expansion between the insulating film 6 and the semiconductor substrate 4 acts in the direction in which the curvature of the concave surface is relaxed to make it convex, so that it is possible to reduce the warp or adjust the warp amount. Become. Since the portion of the element substrate 7 is overwhelmingly thinner than the portion of the support substrate 8, the contribution to the warp of the element substrate can be ignored.

〔実施例〕〔Example〕

第2図は本願発明の実施例を示す。 FIG. 2 shows an embodiment of the present invention.

半導体基板4は厚さ500〜600μm,表面に反り量が約80
μmの凹面を持つ6インチSiウエハーである。
The semiconductor substrate 4 has a thickness of 500 to 600 μm, and the amount of warpage on the surface is about 80.
It is a 6 inch Si wafer with a concave surface of μm.

その凹面から,加速電圧200keV,ドーズ量2×1018cm
-2の条件で酸素(O+)をイオン注入する。表面に0.1〜
0.5μm程度の結晶層を残して,内部に0.5〜1μmの厚
さの酸素イオン濃度の大きい酸素イオン注入領域5が形
成される。(第2図(a)参照)。
From the concave surface, acceleration voltage 200 keV, dose 2 × 10 18 cm
Oxygen (O + ) is ion-implanted under the condition of -2 . 0.1 to the surface
An oxygen ion implantation region 5 having a high oxygen ion concentration and having a thickness of 0.5 to 1 μm is formed inside, leaving a crystal layer of about 0.5 μm. (See FIG. 2 (a)).

1250℃,30分の高温アニールを行い,埋没した絶縁膜
6を形成する。
High temperature annealing is performed at 1250 ° C. for 30 minutes to form the buried insulating film 6.

このようにして,埋没した絶縁膜6の下を支持基板8,
上を素子基板7とするほぼ平坦なSOI基板を得た。(第
2図(b)参照) なお,絶縁膜6を形成するためのイオンとして,O+
他にN+,O2 +,N2 +,O2+,N2+,O2 2+,N2 2+等を用いるこ
ともできる。
In this way, under the buried insulating film 6, the supporting substrate 8,
A substantially flat SOI substrate having the element substrate 7 on the top was obtained. (See FIG. 2B) As ions for forming the insulating film 6, in addition to O + , N + , O 2 + , N 2 + , O 2+ , N 2+ , O 2 2+ , N 2 2+, etc. can also be used.

〔発明の効果〕〔The invention's effect〕

以上説明したように,本発明によれば,反りの小さ
い,あるいは反り量の制御されたSOI基板を得ることが
できる。本発明のSOI基板を用いることにより,素子の
安定動作が確保でき,信頼性が向上することができる。
As described above, according to the present invention, it is possible to obtain an SOI substrate with a small warp or a controlled warp amount. By using the SOI substrate of the present invention, stable operation of the device can be ensured and reliability can be improved.

本発明は素子の微細化,歩留りの向上に寄与するとろ
ころが大きい。
The present invention contributes to the miniaturization of the device and the improvement of the yield, and has a large number of rollers.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)乃至(c)は実施例Iを説明するための断
面図, 第1図(a)乃至(c)は従来の問題点を説明するため
の図、 第2図(a)及び(b)は実施例を説明するための断面
図である。 図において, 1は第1の半導体基板, 2は第2の半導体基板, 1a,1bは絶縁膜であって酸化膜, 3は厚さを減じた半導体層, 4は半導体基板, 5は酸素イオン注入領域, 6は埋没した絶縁膜, 7は素子基板, 8は支持基板 を表す。
1 (a) to 1 (c) are sectional views for explaining the embodiment I, FIGS. 1 (a) to 1 (c) are views for explaining conventional problems, and FIG. 2 (a). And (b) are sectional views for explaining the embodiment. In the figure, 1 is a first semiconductor substrate, 2 is a second semiconductor substrate, 1a and 1b are insulating films and oxide films, 3 is a semiconductor layer with reduced thickness, 4 is a semiconductor substrate, and 5 is oxygen ion. An implantation region, 6 is a buried insulating film, 7 is an element substrate, and 8 is a supporting substrate.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】反りのある半導体基板(4)にその凹面か
ら表面に結晶層を残すほどの高加速で絶縁膜を形成する
ためのイオン注入を行った後アニールを行い,内部に埋
没した絶縁膜(6)を形成し,前記絶縁膜(6)の下を
支持基板(8)とし前記絶縁膜(6)の上を素子基板
(7)とするSOI基板を得ることを特徴とする半導体基
板の製造方法。
1. A semiconductor substrate (4) having a warp is annealed after ion implantation for forming an insulating film from the concave surface at such a high acceleration as to leave a crystal layer on the surface, followed by annealing. A semiconductor substrate obtained by forming a film (6) to obtain a SOI substrate having a support substrate (8) below the insulating film (6) and an element substrate (7) above the insulating film (6). Manufacturing method.
【請求項2】絶縁膜を形成するためのイオンとして, O+,N+,O2 +,N2 +,O2+,N2+,O2 2+,N2 2+を用いること
を特徴とする請求項1記載の半導体基板の製造方法。
2. Use of O + , N + , O 2 + , N 2 + , O 2+ , N 2+ , O 2 2+ , N 2 2+ as ions for forming an insulating film. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is manufactured.
JP2106055A 1990-04-20 1990-04-20 Semiconductor substrate manufacturing method Expired - Lifetime JP2535645B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2106055A JP2535645B2 (en) 1990-04-20 1990-04-20 Semiconductor substrate manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2106055A JP2535645B2 (en) 1990-04-20 1990-04-20 Semiconductor substrate manufacturing method

Publications (2)

Publication Number Publication Date
JPH043908A JPH043908A (en) 1992-01-08
JP2535645B2 true JP2535645B2 (en) 1996-09-18

Family

ID=14423934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2106055A Expired - Lifetime JP2535645B2 (en) 1990-04-20 1990-04-20 Semiconductor substrate manufacturing method

Country Status (1)

Country Link
JP (1) JP2535645B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4224395A1 (en) * 1992-07-23 1994-01-27 Wacker Chemitronic Semiconductor wafers with defined ground deformation and process for their production
JPH1022184A (en) * 1996-06-28 1998-01-23 Sony Corp Substrate bonding device
FR2848336B1 (en) * 2002-12-09 2005-10-28 Commissariat Energie Atomique METHOD FOR PRODUCING A STRESS STRUCTURE FOR DISSOCIATING
JP4552858B2 (en) * 2003-09-08 2010-09-29 株式会社Sumco Manufacturing method of bonded wafer
US7262112B2 (en) * 2005-06-27 2007-08-28 The Regents Of The University Of California Method for producing dislocation-free strained crystalline films
JP5233111B2 (en) * 2006-11-30 2013-07-10 株式会社Sumco Manufacturing method of bonded SOI wafer
JP2012004296A (en) * 2010-06-16 2012-01-05 Sumitomo Electric Ind Ltd Manufacturing method of composite substrate and composite substrate
JP2013008921A (en) 2011-06-27 2013-01-10 Toshiba Corp Semiconductor manufacturing apparatus and manufacturing method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355822A (en) * 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd Manufacture of substrate for forming semiconductor element

Also Published As

Publication number Publication date
JPH043908A (en) 1992-01-08

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