JP2512999B2 - DRAM controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to a DRAM (Dynamic Random
The present invention relates to a DRAM control device having a DRAM controller for controlling read / write and refresh for an access memory array as a core, and particularly to improving a refresh method of a DRAM array.

<Prior Art> DRAM is often used in a memory system requiring a large capacity such as a main frame memory, a buffer memory, and an image memory.

A typical example of a conventional DRAM system is shown in the block diagram of FIG.

The system shown in this figure is roughly divided into a DMA unit 1 and a DMC.
It is composed of two main parts of the part 2.

The DMA unit 1 is a DRAM array and includes banks # 1 to #N.
Of N memory banks, each memory
A bank consists of k DRAM memory elements. That is, the data width is k bits.

The DMC unit 2 is a DRAM controller that controls the DMA unit 1, and includes a DMC 21, a refresh timer RFT22, and a wait state generation unit WG23.

The DMC21 is a DRAM controller, for example, a memory bank selection signal BS (l bit), a row address from the CPU side.
In response to RA, column address CA, memory read / write access request signal MREQ, read / write signal R /, only one memory bank selected by memory bank selection signal BS has address AD (Including row address RA and column address CA), row address
It outputs a strobe signal ▲ ▼, a column address strobe signal ▲ ▼, and a write valid signal ▲ ▼.

The refresh timer RFT22 has a fixed interval T ₀ (eg T
DMC2 at ₀ <15.6 μs = 8 ms / 512 refresh cycle)
It is a timer that gives a refresh request RFREQ to 1.

The wait state generation unit WG23 receives the ready signal RDY from the access request signals MREQ and DMC21 and generates an end signal END in order to notify the end of the read / write operation of the DRAM to the CPU side, for example.

With this configuration, each memory bank has an address signal AD and a row address strobe signal ▲
▼, column address strobe signal ▲ ▼,
When write valid signal ▲ ▼ is received and ▲ ▼ = "H", read operation is performed and read data DOUT (k bit)
Is sent to the data bus DB, and when ▲ ▼ = "L", a write operation is performed to fetch the write data DIN (k bits) from the data bus DB. Normally, any one memory bank in which the row address strobe signal ▲ ▼ and the column address strobe signal ▲ ▼ are valid is accessed.

During the refresh (rewrite) operation, the timing shown in FIG.
Refresh or (b) ▲ ▼ Before ▲
▼ Refresh is performed.

(A) ▲ ▼ Only when refreshing
Refresh or (b) ▲ ▼ Before ▲
▼ Memory bank selection signal regardless of refresh
All row address strobe signals regardless of BS ▲
▼ to ▲ ▼ (or row address strobe signal ▲ ▼ to ▲ ▼ and column
Address strobe signal ▲ ▼ 〜 ▲
)) Becomes valid, whereby the memory banks # 1 to #N are simultaneously refreshed.

Further, the ready signal RDY of the DMC21 during the refresh operation is "L". When the memory read / write request signal MREQ is generated during the refresh operation, the memory access is kept waiting until the refresh request is completed, and the WG23 confirms that the ready signal RDY has become “H” and then the completion signal. Output END.

<Problems to be Solved by the Invention> In the DRAM control device as described above, all memory banks are refreshed at the same time during the refresh operation. Therefore, when the number N of memory banks increases, the number N of memory banks is proportional to the number N of banks. Need refresh current. Therefore,
During the refresh operation, it is unavoidable to supply much more current than the power supply current required for normal read / write operation, which results in an increase in the output capacity of the power supply.
Not preferred.

For example, if a 1-megabit DRAM device is used and N = 4, k = 32, the average power supply current is 2.7AMax during normal read / write operation, and about 7.7 during refresh operation.
It becomes AMax.

In addition, when the refresh current flows, generally, crosstalk noise and common impedance noise are easily generated, and the entire circuit system becomes unstable, which is not preferable.

Further, when a manufacturer's standard device (for example, model 1431 or the like) is used as the DRAM controller, the specification of refreshing all memory banks at the same time cannot be changed, which causes a further problem.

An object of the present invention is to solve the above problems, that is, to suppress a large current generated during refreshing to a low level, and to always realize stable operation of a memory system circuit system.

<Means for Solving the Problems> According to the present invention, in a DRAM control device having a DRAM controller for performing read / write and refresh for a DRAM array including a plurality of memory banks, refresh is performed at a cycle faster than a normal refresh interval. A refresh request generation circuit that generates a request, a refresh request counting circuit that sets a preset value and counts the refresh request, and a count value from the refresh request counting circuit that is input according to a preset logical configuration. At least one set of row address strobe signals provided from the DRAM controller according to the result of logical operation,
And a selection logic circuit for selectively outputting a column address strobe signal.

The refresh request generating circuit has switch means for externally setting a predetermined value so that a refresh request is generated at 1 / k of a normal refresh request interval time T when the number of memory banks is k, and clock generation is performed. The clock from the unit may be counted, and the refresh request may be issued when the count value reaches the predetermined value.

The refresh request counting circuit has switch means for externally setting a set value corresponding to the number of memory banks k, counts the refresh request, and cyclically outputs the count value according to the number of memory banks k. You may do it.

By the operation on the CPU side, appropriate data is sequentially written / read to / from the plurality of memory banks, and the number of matched data is taken as the number of mounted memory banks, and the refresh request generation circuit determines the number of memory banks. A predetermined value may be set in the internal register based on the above, and the refresh request counting circuit may set the set value in the internal register based on the number of memory banks.

<Operation> The DRAM control device of the present invention generates a refresh request at a faster cycle than usual, while counting the refresh request, selecting at least one memory bank corresponding to this count value, and performing a refresh operation. To execute.

<Embodiment> FIG. 1 is a diagram showing the configuration of a DRAM control device embodying the present invention.

The device of the present invention comprises a DRAM controller DMC21 (the same as the conventional one shown in FIG. 7), a refresh request generation circuit (refresh timer) RFT024, a refresh request counting circuit RBS30, and a selection logic circuit LC31.

Refresh request generation circuit (refresh timer) RF
The T0 24 has the same function as the conventional refresh timer RFT22 shown in FIG. 7, but the clock oscillator OC241
A switch means SW1 243 for giving a count set value Vs1 is added to a counter RFC242 which counts the clock CLK of. RFC242 is a down counter, switch means SW
1 Once the value Vs1 set to 243 is fetched, clock CLK
When the counter counts down and the content becomes "0", the refresh request RFREQ is given to the DMC21.

The refresh request counting circuit RBS30 is a counting circuit that counts the refresh request RFREQ generated from the RFT024, and is composed of a counter CNT301 and a switch means SW2302. CNT301 is, for example, a down counter, SW2
The value Vs2 set in 302 is once taken in, and every time the refresh request signal RFREQ becomes valid, it is down-counted, and when the content becomes "0", the value Vs2 is taken in again and operates cyclically. For example, if the value Vs2 = 2,
Counting as "2", "1", "0", "2", "1", "0", ..., This count value D is given to the selection logic unit LC by 1 bit.

Select logic circuit LC31 is DMC21 during read / write operation
The row address strobe signal ▲ ▼ and the column address strobe signal ▲ ▼ are passed through as they are and output to the DMA unit (DRAM element; not shown).
During the refresh operation, the row address strobe signal ▲ ▼ to ▲ according to the count value D of RBS30.
▼ (or ▲ ▼ to ▲ ▼ and column address strobe signal ▲ ▼ to ▲
One or several of ▼) are valid (“L”). LC31
Is a programmable logic device PLD (P
LS161 etc.) is used.

The operation of the DRAM control device of the present invention configured as above will be described below.

Here, the number of memory banks that can be mounted N = 4, the number of memory banks that are actually mounted k = 3 (1 ≦ k ≦ N), l =
Two bits (s = s0, s1) are taken as an example. In addition, ▲ ▼ before ▲ ▼ refresh is handled as the refresh mode.

It should be noted that one memory bank is refreshed during the refresh operation. Therefore, the LC31 is divided into the second read / write operation and the second refresh operation in the normal operation.
Program the logic shown.

In addition, the SW1 243 of the RFT0 24 has about 1/3 of the conventional refresh request interval time T ₀ (1/3 when the number of memory banks is k).
Set the value Vs1 (= T / t; t is the clock CLK period) required to generate time T corresponding to
In SW2 302 of 30, the value "2" is set as the value Vs2.

Next, the case of (1) memory read / write cycle and (2) memory refresh cycle will be described separately using the time chart of FIG.

(1) Read / write cycle The memory access request MREQ becomes valid "H", and the address signal MAD (including signals AD, RA, CA) and the read / write signal R / are input to the DMC21. The DMC 21 determines the priority of the read / write cycle by the access request signal MREQ and the refresh cycle by the refresh request signal RFREQ. DMC21 if refresh is not in progress
When the ready signal RDY is "H", the read / write cycle is started, and if the refresh is being executed, acceptance of read / write is waited.

From the DMC21, along with the address AD and the write enable signal ▲ ▼, the row address strobe signal ▲ ▼ and the column data corresponding to the corresponding memory bank #i (i = 1,2,3) selected by the bank selection signal BS Only the address strobe signal ▲ ▼ is output as "L" level.

The LC31 learns that the read / write cycle has started with the ready signal RDY “H”, and then detects the row address strobe signal ▲ ▼ “L” and the column address strobe signal ▲ ▼ “L” generated by the DMC21. Input as signals ▲ ▼, ▲ ▼, and corresponding signals ▲ ▼, ▲ according to the logic table of FIG.
Set ▼ to “L” level in sequence.

On the other hand, the address AD and the write valid signal ▲ ▼ are input to the DRAM side (not shown), and the row address strobe signal ▲ ▼ and the column address strobe signal ▲ ▼ are set to "L" to the corresponding memory bank #i. "Given at level, read / write operations are performed. In the operation example of the time chart of FIG. 3, i = 1 (bank # 1).

In WG23, access request signal MREQ “H” and ready signal RD
Detects "H", waits for a certain time (time corresponding to memory access time), then outputs end signal END.

This completes the memory read / write cycle.

(2) Refresh cycle Refresh request signal RFREQ from RFT0 24 is valid “H”
Then, the signal RFREQ is given to the CNT 301 in the DMC 21 and RBS 30.

The DMC 21 determines the priority of the refresh cycle by the refresh request signal RFREQ and the read / write cycle by the access request signal MREQ. Access request signal M when refresh request RFREQ becomes valid
If it is REQ "H", the refresh request is not accepted until the access request signal MREQ "L". When the access request signal MREQ is "L", the refresh operation starts immediately. When the refresh cycle starts, the ready signal RDY of DMC21 becomes “L”.

At this time, the row corresponding to all memory banks from DMC21
Address strobe signal ▲ ▼ 〜 ▲
▼, column address strobe signal ▲ ▼
▲ ▼ are all "L". CNT301 in RBS30 is
The refresh request signal RFREQ is counted down by +1 and the result is 1 bit (l = 2, that is, in FIG. 3,
It is output to LC31 as s1 = "H", s0 = "L" and s1 = "L", s0 = "H" (down count).

The LC31 knows that the refresh cycle has started due to the ready signal RDY "L", and corresponds to the count value (s1 = "L", s0 = "H") according to the logic table shown in FIG. Select memory bank #i (memory bank # 2 in this example) and select the corresponding signal ▲ ▼, ▲
Output ▼ as (i = 2) "L".

On the DRAM side, the row address strobe signal ▲ ▼ and the column address strobe signal ▲ ▼ are given only to the memory bank # 2 to start the refresh operation.

When the refresh operation is completed, DMC21 returns ready signal R
Set DY to “L”.

This completes the refresh operation of memory bank # 2.

In the above description of the example, the refresh mode is the before-refresh mode. However, the refresh mode can be handled in the same manner.

Further, in the above example, the logic of LC31 is configured so that only one memory bank is selected at the time of refreshing, but it may be configured so that several banks are refreshed at the same time. At this time, the SW1 243 setting in the RFT0 24 is changed to a correspondingly larger value so that many refresh requests are generated. For example, the table of FIG. 4 shows the logical configuration of the LC31 when two memory banks are refreshed simultaneously (banks # 1 and # 2 simultaneously or banks # 3 and # 4 simultaneously).

In the embodiment shown in FIG. 1, RFT0 24 and RBS30 are set according to the number k of memory banks actually mounted (1 ≦ k ≦ N).
Values are manually set for SW1 243 and SW2 302 in the above, but when the number of memory banks is different depending on the system to be built, it is bothersome and erroneous to manually set the optimum value each time. It is not preferable because there is a risk of setting.

In such a case, instead of SW1 243 and SW2 302, as shown in FIGS. 5 (a) and 5 (b), the refresh request generation circuit RFT0 24 has a register RGE1 244 and the refresh request counting circuit RBS has a register REG2 303. For example, the sixth
The operation program of the flow chart as shown in the figure
Set the value to Vs1 and Vs2 from the CPU to register REG1 244, REG
It may be set to 2 302.

That is, the maximum number of memory banks that can be mounted is N, and (N
-1) is set in REG1 244, and a value necessary to generate the refresh request interval time in the case of the number of memory banks N is set in REG2 303.

Then, appropriate data is sequentially written / read to / from the mounted memory banks, and the number of matching data (j
-1) is the number of memory banks actually mounted,
The value (j-2) is set in REG2 303 as the value Vs2. On the other hand, the value Vs1 necessary for generating the refresh request interval time according to the number of memory banks (j-2) is reset in REG1 244.

By determining the values Vs1, V, s2 in this way,
It can support various systems.

Although the logic selection circuit LC31 and the refresh request counting circuit RBS30 are separately configured and added in the example of FIG. 1, they may be incorporated in the DRAM controller DMC21.

<Effects of the Invention> According to the DRAM control device of the present invention, the following effects can be obtained.

In a DRAM array consisting of multiple memory banks, when performing a refresh operation, either one or multiple memory banks are refreshed based on previously designated information, so that all memory banks are refreshed at the same time. The refresh current can be significantly reduced as compared with the case of performing.

If the number of memory banks actually mounted is smaller than the number of memory banks that can be mounted, the refresh request interval time is set according to the number of memory banks. Compared with the conventional device, useless refresh operation can be omitted, and reduction in processing efficiency of memory read / write operation can be prevented.

Furthermore, it is possible to configure the registers to automatically set the values corresponding to the actual number of memory banks and refresh request interval time, so that even if the number of memory banks differs depending on the system, manual setting is possible. You don't have to rely on it.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a DRAM control device embodying the present invention, and FIG. 2 is a selection logic circuit in the device of the present invention.
FIG. 3 is a time chart showing the operation of the device of the present invention. FIG. 4 is a table showing another logic configuration programmed in the selection logic circuit LC31 in the device of the present invention. 5 (a) is another configuration example of the refresh request generation circuit RFT024 in the device of the present invention, FIG. 5 (b) is another configuration example of the refresh request counting circuit RBS30 of the device of the present invention, and FIG. Fig. 5 (a),
FIG. 7 is a time chart showing the operation of the device of the present invention in the case of using the configuration of (b), FIG. 7 is a block diagram showing a conventional DRAM control device, and FIGS. 8 (a) and 8 (b) are refreshing in the conventional device. It is a time chart showing an operation. 1 ... DMA block, 2 ... DMC block, 21 ... DRAM controller DMC, 22 ... Refresh timer RFT, 23 ... Wait state generating section WG, 24 ... Refresh request generating circuit RFT0, 241 ... Clock Generator OC, 242 ...... Down counter RFC, 243 ...... Switch means SW1, 244 ...... Register REG1, 30 ...... Refresh request counting circuit RBS, 31 ...... Selection logic circuit LC, 301 ...... Down counter CNT, 302 …… Switch means SW2, 303 …… Register REG2.

Claims (4)

(57) [Claims] 1. A refresh request generation circuit for generating a refresh request at a cycle faster than a normal refresh interval in a DRAM controller having a DRAM controller for reading / writing and refreshing a DRAM array composed of a plurality of memory banks. A refresh request counting circuit that sets a preset value and counts the refresh request; and a count value from the refresh request counting circuit that is input to perform a logical operation according to a preset logical configuration At least one set of row address strobe signals provided from the DRAM controller,
A DRAM control device comprising: a selection logic circuit which selectively outputs a column address strobe signal. 2. The refresh request generating circuit comprises a switch means for externally setting a predetermined value so that a refresh request is generated at 1 / k of a normal refresh request interval time T when the number of memory banks is k. 2. The DRAM control device according to claim 1, further comprising: counting a clock from the clock generation unit and issuing a refresh request when the count value reaches the predetermined value. 3. The refresh request counting circuit has switch means for externally setting a set value corresponding to the number k of memory banks, counting the refresh requests and cyclically according to the number k of memory banks. The DRAM control device according to claim 2, wherein the DRAM control device outputs a count value. 4. The operation on the CPU side sequentially writes / reads appropriate data in the plurality of memory banks, and sets the number of the matched data as the number of mounted memory banks, and the refresh request generation circuit The predetermined value is set in the internal register based on the number of memory banks, and the refresh request counting circuit is set to the set value in the internal register based on the number of memory banks. The DRAM control device described.