JP3151832B2 - DMA controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller, and more particularly to a DMA controller which executes a DMA transfer by a two-bus cycle transfer method.

[0002]

2. Description of the Related Art As is well known, a DMA controller is a peripheral input / output device (hereinafter referred to as a peripheral I / O) such as a magnetic disk device, a communication device, and a display device.
The data transfer between the central processing unit (CPU) and the main storage device (hereinafter referred to as a memory) is executed.

As the processing efficiency and speed of the CPU have been improved, the data bus width has become larger, for example, 32 bits. When an information processing system is constructed using a CPU having such a large data bus width, not all peripheral I / Os used in the system have the same bus width as the CPU. For example, a peripheral I / O of 8 bits (1 byte) or 16 bits (half word) for a CPU of 32 bits (1 word) can be used in the system. In such a case, DMA transfer between the peripheral I / O and the memory having different bus widths is required.

[0004] For such a request, a DMA controller using a two-bus cycle transfer system is used. The two-bus cycle transfer method is to perform a DMA transfer in two bus cycles, a read bus cycle and a write bus cycle. The DMA controller first executes a read bus cycle to fetch data from the memory or the transfer source of the peripheral I / O, and transfers the fetched data to the peripheral I / O.
O or internally arranged according to the bus width and / or storage address of the transfer destination of the memory, and write data is written to the transfer destination by executing a write bus cycle.

[0005]

As described above, the DMA controller based on the two-bus cycle transfer system executes the DMA transfer between the peripheral I / O and the memory having different bus widths. Requires array processing. The array processing can be completed within a read bus cycle when the number of operation peripherals is low. However,
If the operating frequency is increased and the bus cycle is shortened in order to improve the transfer speed, it becomes impossible to complete the array processing within the read bus cycle, and a time for the array processing is provided between two bus cycles. There is a need. That is, the read bus cycle and the write bus cycle cannot be executed consecutively, which limits the improvement of the transfer speed.

Accordingly, it is an object of the present invention to provide an improved DMA controller.

Another object of the present invention is to provide a two-bus cycle transfer type DMA controller which can execute a read bus cycle and a write bus cycle continuously.

[0008]

SUMMARY OF THE INVENTION A DMA controller according to the present invention provides a DMA controller between a first device having a data width of a first byte length and a second device having a data width of a second byte length. In the DMA controller performing the transfer, DM
Prior to the A transfer, a first register for the first device and a second register for the second device for reading and storing information on the data width of the first and second devices from outside the DMA controller. A register, a plurality of registers for respectively storing byte length data located at respective byte positions of an input / output data bus of the DMA controller, and an output data of the first device which is input and has a data width of the DMA controller. A first aligner that rearranges byte positions according to data width information stored in the first register and writes the data to the register when the data width is smaller than an input / output data bus width; and a data width of the second device. Is smaller than the input / output data bus width of the DMA controller, the data is read from the register according to the data width information stored in the second register. And having been a second aligner that in the byte position rearranged data output of the data.

The first aligner includes a first counter for counting the order of inputting data according to an increase / decrease value corresponding to a data width of the first device, and a byte position according to the data width and the counting result. Rearranging and writing input data to the register, wherein the second aligner includes a second counter that counts an output order of data by an increase / decrease value according to a data width of the second device, The byte position of the data read from the register is rearranged in accordance with the data width and the counting result, and the data is output.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system using a DMA controller 1 according to one embodiment of the present invention. This system comprises a DMA controller 1, a CPU 2,
It comprises a memory 3 and a plurality of peripheral I / Os (only two I / Os 4 and 5 are shown), which are a system control bus 6, a system address bus 7 and a 32 bit (4 byte) wide. They are interconnected via a system data bus 8. The memory 3 reads / writes 4 bytes (1 word) of data in one bus cycle.
Since data can be written, the branch data bus 30 having a width of 32 bits is used.
Is connected to the SDB 8 via the. On the other hand, the first and second
Since the data widths of the peripheral I / Os 4 and 5, ie, the port widths in this embodiment are 1 byte and 2 bytes, respectively,
/ O4 is SD via an 8-bit branch data bus 40.
The peripheral I / O 5 is connected to the lower 2 byte data bus of the SDB 8 via the branch data bus 40 having a width of 16 bits.
The DMA controller 1 has a memory 3 and a first peripheral I / O 4
Between the memory 3, the second peripheral I / O 5, and the memory 3
To transfer data between other peripheral I / Os (not shown) and between two areas in the memory 3, and is connected to the SDB 8 via a branch data bus 10 having a 32-bit width. D
The MA controller 1 issues a DMA transfer request signal (DDMARE).
Q) Peripheral I / O 4 corresponding to 12-1 and 13-1,
5 is detected. When the request is detected, a right to use the system bus 6-8 is requested to the CPU 2 by the hold request signal (HLDREQ) 11-1. When detecting the HLDREQ signal 11-1, the CPU 2 suspends the program processing being executed and changes the bus use right to the DM.
Yield to A controller 1. This is indicated by the hold acknowledgment signal (HLDACK) 11-2 in the DMA.
Notify the controller 1. Thus, the DMA controller 1 returns DMA acknowledge signals (DMAACK) 12-2 and 13-2 to the requested peripheral I / O,
Execute DMA data transfer.

Referring to FIG. 2, the DMA controller 1
Has data transfer circuits 100-1 and 100-2 for each of a plurality of DMA channels and a read / write controller 200. The first and second channel data transfer circuits 100-1 and 100-2 are provided with first and second peripheral I / Os.
4 and 5, respectively. Since these data transfer circuits have the same configuration, only the circuit 100-1 is shown. That is, the input buffer 101 transfers the data from the bus 10 to the 32 data terminals DT0 to DT3.
1 to the receiving register 102. Register 1
02 is the second clock φ2 and the second state signal T2
And temporarily stores data from input buffer 101 in response to a latch enable signal from AND gate 103. The data is stored in the read aligner controller 10.
5 is subjected to byte array (shift) processing by the read aligner 104 based on the control data from No. 5 and supplied to the data register 106. This register 106 stores the first and second fields 106-1 and 106 according to the present invention.
-2. The first field 106-1 has four one-byte (8-bit) width registers R10-R13, and the second field 106-2 also has four one-byte (8-bit) registers.
The read aligner 10 has width registers R20-R23.
Registers R10-R23 to which data from 4 is written
Are controlled by the register controller 107, and the positions and numbers of the registers R10 to R23 from which the store data is read to the write aligner 108. The write aligner 108 registers the register 10 based on the control data from the write aligner controller 109.
Then, an array (shift) process of the data from step 6 is performed and output to the register 110. The latch timing of this register 110 is controlled by an AND gate 111 receiving the first clock φ1 and the first state signal T1.
Output data of register 110 is temporarily stored in register 112 under the control of AND gate 113 receiving second clock φ2 and first state signal T1, and the data is output buffer activated by write bus cycle signal WC. 114 through the data terminals DT0-DT
31 (bus 10).

The read / write controller 200 controls each D
It has a plurality of parameter registers 201 and 202 provided corresponding to the MA transfer channel and a sequence controller 203 for controlling the operation sequence / timing of the DMA data transfer. Parameter registers 201, 20
2 are the number of bytes to be transferred (BNM), the start address of the memory area (MSTADD), the memory bus width (BW), the port address (PADD) indicating the peripheral I / O address, and the peripheral I / O The port width (PW) indicating the bit width and the transfer direction (TD) indicating the data transfer from the memory to the peripheral I / O or vice versa, and these information are set by the CPU 2 (FIG. 1). Although the sequence controller 203 generates various control signals for DMA transfer in response to the supplied basic clock signal CLK, only a timing control signal to the data transfer circuit 100 is shown in the figure. φ1 and φ2 indicate clock signals, which are in opposite phase relationship. T1 and T2 are state signals, which also have an antiphase relationship. RC is a signal indicating a read bus cycle period, and WC is a write bus cycle period. See FIG. 5 and FIG. 6 for the phase relationship between the signals φ1 and T1 (φ2 and T2).

Referring to FIG. 3, the configurations of register controller 107 and data register 106 are shown in more detail. The register controller 107 includes a write control circuit 1007 for controlling writing of data read from a transfer source in the read bus cycle to the data register 106 and a read control circuit for controlling reading of data from the data register 106 in the write bus cycle. 1008. The write control circuit 1007
Write point (WP) 1073, incrementer (I
NC) 1072, multiplexer (MPX) 1071,
Write decoder 1074, AND gate 1075 for generating an enable signal to decoder 1074, φ2
It has a delay circuit 1076 and an AND gate 1077. MPX 1071 is in the data transfer direction TDGA “1”
The port width PW is selected and output when the transfer is performed from the peripheral I / O to the memory, and the bus width BW is output when the TD is “0” (transfer from the memory to the peripheral I / O).
Each of the port width PW and the bus width BW has 2 bits, "00" represents an 8-bit width, "01" represents a 16-bit width, and "10" represents a 32-bit width. INC
Reference numeral 1072 increases the content of the WP 1073 by the number corresponding to the output data from the MPX 1071 and writes it back. WP107
3 is a 3-bit configuration. When the output of MPX 1071 is “0”
When it is 0, the content of WP 1073 is incremented by one, when it is "01", it is incremented by two, and when it is "10", it is incremented by 4. In response to the content of WP 1073 and the output data of MPX 1071, The write decoder 1074 controls the levels of the eight write enable signals W10 to W23 according to Fig. 4. These signals W10 to W23 are supplied to the write enable terminals WE of the registers R10 to R23, respectively. Pointer (RP) 1083
It has an incrementer (INC) 1082, a multiplexer (MPX) 1081, and a read decoder 1084. Decoder 1084 is activated by signal WC. The MPX 1081 sets the port width PW when ITD, which is inverted data in the data transfer direction TD, is “1”,
When it is "0", the bus width BW is selected. INC1082
The update operation for the RP 1083 is performed by the W of the INC 1072.
Same as for P1073. In response to data from RP 1083 and MPX 1081, read decoder 1084 controls the levels of eight read enable signals R10-R23 according to FIG. These read enable signals R10-R23 correspond to the registers R10-R23.
Are supplied to the read enable terminals RE of the respective terminals. Thus, each register R in the data register 106 stores the corresponding byte data of the data from the read aligner 104 when the write enable signal W is “1”, and stores the stored byte data when the read enable signal R is “1”. The light is supplied to the light aligner 108.

Although not shown, the read aligner controller 105 receives the lower 2 bits of the output of the WP 1073 and the write aligner controller 109
It receives the lower 2 bits of the output of 83. When the lower two bits of the WP 1073 are “00”, the read aligner controller 105 stores the register 102 in the read aligner 104.
Is output as it is, and is shifted upward by one byte for "01", two bytes for "10", and three bytes for "11". Write aligner controller 109 is RP1083
When the lower two bits of the data register 10 are "00", the data register 10
The data from 6 is output as it is, and is shifted to the lower side by 1 byte for "01", 2 bytes for "10", and 3 bytes for "11".

Next, the first channel of the DMA controller 1 is assigned to data transfer from the first peripheral I / O 4 to the memory 3 and the second channel is assigned to data transfer from the memory to the second peripheral I / O 5. The operation will be described assuming that there is. The CPU 2 stores the number of bytes BNM to be transferred, the start address MSTADD of the transfer destination area of the memory 3, “10” as the bus width BW 1, and the port address PADD 1 of the peripheral I / O 4 in the parameter register 201 as initial settings for the DMA controller 1. , Port width PS
“00” as W1 and “1” as transfer direction TD1
Are set respectively. Also, the parameter register 201
The number of bytes to be transferred BNM2, the start address MSTADD of the transfer source area of the memory 3, "10" as the bus width BW2, and the port address PADD of the peripheral I / O5
2. "01" as port width PSW2, transfer direction TD
“0” as 2 is set. Thus, DM
The A controller 1 is in a state where DMA transfer can be executed.

First, a data transfer request from the peripheral I / O 4 will be described. Peripheral I / O 4 is DMAREQ signal 1
When 2-1 is set to the active level, the DMA controller 1 sets the HLDREQ signal 11-1 to the active level and requests the CPU 2 to use the bus 6-8. In response to this, the CPU 2 interrupts the program processing being executed, sets the HLACK signal 11-2 to the active level while holding its internal state, and notifies the DMA controller 1 that the right to use the bus has been handed over. I do.

As a result, the DMA controller 1 executes data transfer from the peripheral I / O 4 to the memory 3 according to the timing chart shown in FIG. The unit bus cycle of the DMA controller 1 is executed for two clocks of the clock φ1 (φ2), that is, one by one each in the T1 and T2 states, outputs an address in the T1 state period, and reads / writes data in the T2 state. . Also, the DMAACK signal 12 corresponding to the start of the T1 state is synchronized.
-2 (13-2). In the system shown in FIG. 1, the DMAACK signal 12-2 (13-2) is
Although supplied to O4 (5) and used for an access instruction, the access may be detected by decoding the port address PADD1 (PADD2).

First, the DMA controller 1 starts a read bus cycle. Therefore, the sequence controller 203 sets the RC signal to the active (high) level,
The WC signal is set to the inactive (low) level. As a result, the data PD00 is read from the peripheral I / O 4 and the DMA controller 1 via the buses 40, 8 and 10.
Is supplied to the data terminal DT. At this time, the peripheral I / O
Since 4 is 8 bits, the read valid data PD00 is supplied to the data terminals DT0-7, and the remaining data terminals DT8-31 are meaningless. As is clear from the description related to FIGS.
Is stored in the data register R10 via the register 102 and the aligner 104. While 8 bits (1 byte) of data are read from the peripheral I / O 4 in one read bus cycle, data of 32 bits (4 bytes) can be written to the memory 3 in one write bus cycle. it can. Therefore, the DMA controller 1 continuously executes the unit bus cycle in the read mode four times for the peripheral I / O 4 specified as the transfer source. In order to continuously execute a read bus cycle and a write bus cycle, the data register 106 has two fields 106-1 and 106-2 each having a capacity of 4 bytes.
have. Therefore, DMA from peripheral I / O4
In the initial operation based on the request, as shown in FIG. 5, the controller 1 continuously executes the unit bus cycle in the read mode eight times. Thus, 8-byte data PD00 to PD07 are read from the peripheral I / O 4 and sequentially supplied to the data terminals DT0-7. These data PD
00-PD07 is temporarily stored in the registers R10-P23 in the data register 16 as described with reference to FIGS.

Subsequent to the read bus cycle, by setting the signals RC and WC at low and high levels, respectively, a write bus cycle with one unit bus cycle is executed. In such a cycle, the read decoder 1084 sets the four read enable signals R10-R13 to "1", so that the store data PD01-PD0 from the registers R10-R13 in the first field 106-1.
3 is read out, the write aligner 108, the register 11
0, 112, and output from the data terminal DT-31 via the output buffer 114, and written to the memory 3.

Subsequently, a read bus cycle of four unit bus cycles is executed, and the four byte data PD08-PD11 from the peripheral I / O 4 are stored in the first field 106.
-1 are temporarily stored in registers R10-R13. Following this, a write bus cycle with one unit bus cycle is executed, and the store data PD0 from the registers R20 to R23 in the second field 106-2 are stored.
4-Read from PD08 and write to memory 3. Then, peripheral I / O is performed by the next read bus cycle.
Four byte data PD12-P read from O4
D15 is stored in registers R20-R23 of the second field, respectively. Thereafter, this operation is performed until the data transfer for the number of bytes specified by the transfer byte number information BNM1 is completed. As described above, the register 10 for data acquisition and output timing adjustment is used.
Despite the presence of 2,110,112 and aligners 104,108 for the data array, it allows for continuous execution of read and write bus cycles.

The read / write controller 200
Checks the level of the DMAREQ signal 12-1 from the peripheral I / O 4 every time a unit bus cycle is executed. At this time, if the DMAREQ signal 12-1 is at the inactive level, the data transfer process is temporarily suspended and the HLDR
The EQ signal 11-1 is set to the inactive level, and the right to use the bus is returned to the CPU 2. For example, when a read bus cycle for data PD09 is executed, the DMAREQ signal 12
If -1 becomes the inactive level, the data PD09
The processing is interrupted at the time when the
Return to The peripheral I / O 4 again outputs the DMAREQ signal 12-1.
Is activated, the right to use the bus is obtained from the CPU 2, and the process is restarted from the read bus cycle for the data PD10. When the number of transfer bytes indicated by the information BNM1 is 6, a write bus cycle is executed following a read bus cycle for the data PD05, and data PD00 to PD03 are written to the memory. The data PD04 executed
PD05 is written to the memory.

On the other hand, the DMA transfer from the peripheral I / O 5 operates according to the timing chart of FIG. That is, the DMA controller 1 first executes a read bus cycle to read data to be transferred from the memory 3. Since the memory 3 has a 32-bit width, 4-byte data MBD00-MBD03 is read at a time, and the data is transferred to the second channel transfer circuit 1 via the data terminals DT0-31.
The data is temporarily stored in registers R10-R13 of the first field 106-1 in 00-2. As described above, in the initial operation, the read bus cycle is executed again,
4 art data MBD10- read from the memory 3
MBD13 is the register R2 of the second field 106-2.
The data is temporarily stored in each of 0-R23. Subsequently, a write bus cycle is executed. As described with reference to FIGS. 3 and 4, the data M from the registers R10 and R11 are read.
BD00 and MBD01 are read and transferred to the peripheral I / O5. The write bus cycle is executed again, and data MBD02 and MBD03 from registers R12 and R13 are supplied to peripheral I / O5. Subsequently, a read bus cycle is executed, and 4-byte data MBD20 from memory 3 is read.
-MBD 23 is the register R of the first field 106-1
Stored temporarily in 10-R13. By the following two read bus cycles of the unit bus cycle, the second field 1
06-2 Data MBD from registers R20 and R21
10, MBD11 and data MBD12 and MBD13 from R22 and R23 are transferred to the peripheral I / O5.

Also in this operation, as described above, the DMAREQ signal 13-1 from the peripheral I / O 5 and the information BNM
The operation is controlled according to the number of transfer bytes indicated by 2.

[0025]

As described above, the DMA according to the present invention is
The controller is a two-bus cycle system of a read bus cycle and a write bus cycle, and can execute DMA transfer from a transfer source to a transfer destination by continuously executing both bus cycles.

The present invention is not limited to the above embodiment, but can increase the number of clocks per unit bus cycle or increase the bus width. The address information of the DMA transfer area of the memory 3 is stored in the controller 105, 107, 1
Further use as part of the control information to 09 provides more fine-grained data transfer.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing system using a DMA controller according to one embodiment of the present invention.

FIG. 2 is an internal block diagram of the DMA controller shown in FIG.

FIG. 3 is a block diagram showing a register controller and a data register shown in FIG. 2;

FIG. 4 is a diagram illustrating a relationship between output data and input data of each decoder illustrated in FIG. 3;

FIG. 5 is a timing chart showing an example of a DMA transfer operation by the DMA controller of the embodiment.

FIG. 6 is a timing chart showing another example of the DMA transfer operation by the DMA controller of the embodiment.

Claims (2)

(57) [Claims] 1. A DMA controller for performing a DMA transfer between a first device having a data width of a first byte length and a second device having a data width of a second byte length.
Prior to MA transfer, a first register for the first device and a second register for the second device for reading and storing information on the data width of the first and second devices from outside the DMA controller. A register, a plurality of registers for respectively storing byte length data located at respective byte positions of an input / output data bus of the DMA controller, and an output data of the first device which is input and has a data width of the DMA controller. A first aligner that rearranges byte positions according to data width information stored in the first register and writes the data to the register when the data width is smaller than an input / output data bus width; and a data width of the second device. Is smaller than the input / output data bus width of the DMA controller, the data is read from the register according to the data width information stored in the second register. DMA controller; and a second aligner re-arrayed and the byte position of the data to the data output. 2. The apparatus according to claim 1, wherein the first aligner includes a first counter that counts an input order of data according to an increase / decrease value according to a data width of the first device, and a byte according to the data width and the counting result. The input data is written to the register by rearranging the positions, and the second aligner includes:
A second counter that counts an output order of data according to an increase / decrease value according to a data width of the second device, and rearranges byte positions of data read from the register according to the data width and the counting result. 2. The DMA controller according to claim 1, wherein the data is output from the DMA controller.