JP2503504B2 - Power supply circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit, and more particularly to a power supply circuit provided in an integrated circuit having MOS transistors as constituent elements.

[Conventional technology]

The recent improvement in the processing accuracy of semiconductor integrated circuits has caused a reduction in the breakdown voltage against the power supply voltage as the integration degree has improved and the constituent elements have become finer. For this reason, a semiconductor integrated circuit that has achieved a high degree of integration has a power supply circuit inside, and by using that power supply circuit as a potential supply means for other circuit parts on the same semiconductor integrated circuit, It is becoming more common to have a circuit form configured so that a potential higher than the set potential is not applied to a specific portion of the.

FIG. 3 is a circuit diagram showing an example of a power supply circuit conventionally used, and FIG. 4 is a characteristic diagram showing a change in output potential with respect to a change in power supply potential of the power supply circuit shown in FIG.

In FIG. 3, transistors Q ₁ , Q ₂ , Q ₃ , and Q ₄ are N-channel MOS enhancement transistors with their gates and drains connected in common, and the source and drain of each transistor are between node N ₁ and ground potential. Are connected in series. Transistors _{Q 1, Q 2, Q 3} , Q 4 constitute a reference potential generating means for a reference potential on the total of the threshold of each transistor.

Transistor Q ₅ is a P-channel MOS enhancement transistor, with its gate connected to ground potential, its source connected to the power supply potential, and its drain connected to node N ₁ .
The transistor Q ₆ is an N-channel MOS enhancement transistor, and has its gate connected to the node N ₁ , its drain connected to the power supply potential, and its source connected to the output node of the power supply circuit.

When the power supply potential becomes higher than the absolute value of the threshold value of the transistor Q ₅ , the node N ₁ becomes the power supply potential because the transistor Q ₅ is turned on. When the power supply potential rises, the potential of the node N ₁ also rises because the transistor Q ₅ keeps the power supply potential and the node N ₁ conductive. The potential of the node N ₁ is the transistor Q ₁ , Q ₂ ,
If the total of the thresholds of the transistors of Q ₃ and Q ₄ is exceeded,
Transistors _{Q 1, Q 2, Q 3} , Q 4 are turned on, the potential of the node N ₁ becomes a value determined by the transistors _{Q 1, Q 2, Q 3} , Q 4 , the current driving capability of the transistors of Q ₅ . Since the current drive capacity of the transistor Q ₅ is set to be much smaller than the current drive capacity from the node N ₁ to the ground potential due to the series connection of the transistors Q ₁ , Q ₂ , Q ₃ , and Q ₄ ,
The value is kept almost equal to the sum of the threshold values of the transistors Q ₁ , Q ₂ , Q ₃ , and Q ₄ .

Therefore, when the power supply potential is low, the potential of the node N ₁ remains substantially equal to the sum of the threshold values of the transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ regardless of the power supply potential.

Node N ₁ and the gate is the output potential of the power supply circuit shown in FIG. 3,
Since it is the source potential of the transistor Q ₆ whose drain is the power source potential, a potential lower than the potential of the node N ₁ by the threshold value of the transistor Q ₆ is generated as the output potential. Therefore, when the power supply potential is low, an output potential that fluctuates according to the fluctuation of the power supply potential is output, and when the power supply potential is higher than the reference potential preset by one reference voltage generating means, that output potential is output regardless of the power supply potential. The output potential according to the reference potential is output. That is, the power supply circuit as described above has a function of protecting the circuit portion connected as a load from being applied with a potential higher than a certain potential, and reducing the change in the characteristics due to the fluctuation of the power supply voltage. .

FIG. 4 shows the above characteristics, where 10 is the potential of the node N ₁ and 20 is the output potential.

[Problems to be solved by the invention]

Generally, in a semiconductor integrated circuit including a MOS transistor as a constituent element, characteristics change or initial failure occurs during use due to ions contained in the insulating film of the MOS transistor in the manufacturing process. Therefore, generally, in the manufacturing process of a semiconductor integrated circuit having MOS transistors as constituent elements, a test called “burn-in test,“ applying a high potential to the semiconductor integrated circuit at high temperature to accelerate characteristic fluctuations and initial defects ”” is performed. And ensures reliability. However, in the above-mentioned power supply circuit, it is difficult to apply a high potential to the load circuit of the power supply circuit, so that there is a drawback that it is difficult to secure reliability against the occurrence of defects in the load circuit.

It is an object of the present invention to provide a power supply circuit in which the above-mentioned drawbacks have been ameliorated by providing means for withstanding the application of high potential.

In contrast to the conventional power supply circuit described above, the present invention uses a control means other than the power supply potential at the same time as protection against a rise in the power supply potential of the load circuit due to the stabilization of the output potential, or a reduction in the characteristic variation due to the power supply potential variation. It has an original content that enables a burn-in test by applying a high electric potential without a need.

[Means for solving problems]

A power supply circuit according to the present invention comprises first and second reference potential generating means formed by connecting a plurality of N-channel MOS transistors each having a gate and a drain connected, and the first and second reference potential generating means. A P-channel MOS transistor in which the drain is connected to the connecting node, a source is connected to the power supply potential, and a gate is connected to the ground potential, and an N-channel MOS transistor is connected to the contact, the gate is connected to the power supply potential, and the output terminal is connected to the source. A first reference potential generating means, the first reference potential generating means outputs a potential that fluctuates according to the fluctuation of the power source potential when the power source potential is lower than the reference potential set by the first reference potential generating means. When the power supply potential is higher than the reference potential to be set and lower than the reference potential set by the second reference potential generating means, a substantially constant potential is output, Serial constructed so as to output a potential which varies as a function of fluctuations in the power source potential when the power supply potential higher than the reference potential is a second reference potential generating means sets.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
The figure is a characteristic diagram showing the variation of the output potential with respect to the variation of the power source potential of the circuit shown in FIG.

The power supply circuit shown in FIG. 1 has a second reference voltage generating means 1 added between the power supply potential and the node N _{1 in} the conventional power supply circuit (see FIG. 3). In the same figure, the potential of the node N ₁ is equal to the power supply potential when the power supply potential is low, and the power supply potential of the transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ is the same as in the conventional power supply circuit shown in FIG. When the threshold voltage is higher than the sum of the threshold values, the value is kept slightly higher than the sum of the above values due to the difference in the current driving capability of the transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ and Q ₅ .

Here, the power supply potential further rises, and the potential difference between the power supply potential and the sum of the threshold values of the transistors Q ₁ , Q ₂ , Q ₃ , and Q ₄ becomes the transistors Q ₇ , Q ₈ , Q ₉ , and Q _10. larger the than the sum of the threshold value of each transistor, the transistor Q _1, Q
₂ , Q ₃ , Q ₄ , Q ₅ , Q ₇ , Q ₈ , Q ₉ , and Q ₁₀ are all turned on. The potential of the node N ₁ is connected in series between the power supply potential and the transistor Q ₇ connected in series between the node _{N 1, Q 8, Q 9} , Q 10 according to the current driving capability and a ground potential and the node N ₁ Transistor Q ₁ , Q ₂ ,
Although the value is determined by the ratio with the current driving capability of Q ₃ and Q ₄ , the above ratio is set to a ratio at which the potential of the node N ₁ can rise in accordance with the rise of the power supply potential.

Therefore, the potential of the node N ₁ is the power supply potential transistors Q ₁ , Q ₂ ,
If it is lower than the sum of the thresholds of the transistors of Q ₃ and Q ₄ , it becomes the power supply potential. If the power supply potential is higher than the sum of the thresholds, it keeps a value slightly higher than the threshold voltage. its potential in response to an increase in the power supply potential is higher than the sum of the threshold of each transistor of the power supply potential and the potential difference is the transistor Q ₇ and the sum of the _{threshold, Q 8, Q 9, Q} 10 is To rise. The output potential node N ₁ and the gate of the power supply circuit shown in FIG. 1, the transistor Q ₆ serving as a drain supply potential, always a threshold amount corresponding lower potential of the transistor Q ₆ than the potential of the node N _1.

Figure 2 shows the above characteristics, where 10 is a node.
The potential of N ₁ and 20 indicate the output potential, respectively.

〔The invention's effect〕

As described above, in the power supply circuit according to the present invention, the two reference potentials determined by the two reference potential generating means are set to appropriate values, so that the load circuit to be connected has a constant value in the normal operating power supply voltage range. By supplying the potential, protection against the overpotential of the load circuit and stabilization of the characteristics are realized, and there is an effect that a burn-in test can be performed by applying a high potential to the load circuit in the manufacturing process.

Although the N-channel MOS transistor is used as the reference potential generating means in the above description, the same effect can be obtained by using the P-channel MOS transistor or the junction potential of the PN forward junction.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a power supply circuit according to the present invention, FIG. 2 is a characteristic diagram thereof, FIG. 3 is a circuit diagram of a conventional power supply circuit, and FIG. 4 is a characteristic diagram thereof. 1 ...... the second reference voltage generating _{means, Q 1, Q 2, Q} 3, Q 4, Q 6, Q 7,
_{Q 8, Q 9, Q 10} ...... N -channel MOS enhancement transistor, Q ₅ ...... P-channel MOS enhancement transistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/04

Claims (2)

(57) [Claims] 1. A first and second reference potential generating means, which is formed by connecting a plurality of N-channel MOS transistors each having a gate and a drain connected to each other, and the first and second reference potential generating means are connected to each other. A P-channel MOS transistor in which a drain is connected to the node, a source is connected to the power supply potential, and a gate is connected to the ground potential; and an N-channel MOS transistor is connected to the contact, the drain is connected to the power supply potential, and the source is connected to the output terminal. When the power supply potential is lower than the reference potential set by the first reference potential generation means, a potential that fluctuates according to the fluctuation of the power supply potential is output, and the first reference potential generation means sets When the power source potential is higher than the reference potential and lower than the reference potential set by the second reference potential generating means, a substantially constant potential is output and the second base potential is output. A power supply circuit, which outputs a potential that fluctuates according to fluctuations in the power supply potential when the power supply potential is higher than the reference potential set by the quasi-potential generation means. 2. A power supply circuit according to claim 1, wherein a potential is supplied to a bit line in a MOS dynamic random access memory.