JP2025008651A - Semiconductor integrated circuit wiring design device, semiconductor integrated circuit wiring design method, and semiconductor integrated circuit wiring design program - Google Patents

Abstract

To provide a wiring design device for a semiconductor integrated circuit that can handle an obstacle in a complicated shape.SOLUTION: A wiring design device for a semiconductor integrated circuit comprises: first-time candidate cell acquisition means 35 which acquires a first cell candidate until a starting-point section cell is extended up to a space region forward in a longitudinal direction from the starting-point section cell to the end point of wiring in parallel with a longitudinal segment or a lateral segment; second-time candidate cell acquisition means 36 which acquires a second cell candidate until the cell is extended up to a space region newly forward in the direction of the end point as a lateral direction orthogonal to the longitudinal direction; and similarly fourth-, fifth-, ..., (n)th-time candidate cell acquisition means 38 which acquire necessary fourth, fifth, ..., n-th (integer) cell candidates.SELECTED DRAWING: Figure 2

Description

This invention relates to a wiring design device for semiconductor integrated circuits, a wiring design method for semiconductor integrated circuits, and a wiring design program for semiconductor integrated circuits.

In semiconductor layout design, when there are complex design rules such as multi-spacing rules or obstacles with complex shapes, there are problems with conventional shape-based automatic routing, such as not being able to complete the routing or creating detour routes.

Patent Document 1 discloses an invention relating to a wiring design method that can prevent noise errors occurring between clock nets while keeping the consumption of wiring resources small. That is, this invention is a wiring design method for wiring both clock nets and non-clock nets of a semiconductor integrated circuit, characterized in that the conditions for defining the spacing between the wires are that the clock net is wired under a first condition that leaves space between the wires to allow for other wiring, and that the non-clock net is wired under a second condition that provides a narrower spacing between the wires than the first condition.

Patent document 2 discloses a wiring design method for a semiconductor integrated circuit in which, when determining wiring paths between input/output terminals of circuit cells or circuit blocks on a semiconductor substrate by automatic wiring processing, the semiconductor substrate is divided into a plurality of circuit regions including the circuit cells or circuit blocks, position information of obstacles present in the circuit regions is detected, wiring paths between the circuit regions are determined according to the position information of the obstacles, and a portion of the determined wiring paths is used to determine the wiring paths within the divided circuit regions. In this patent document 2, a line segment search method is used as a method for determining the wiring paths between the circuit regions.

Patent Document 3 discloses a layout design technique suitable for the wiring process in the layout design of semiconductor integrated circuits. The layout design method of Patent Document 3 includes the steps of storing in a rectangular area list storage unit a rectangular area that is the starting point of wiring from a wiring area of multiple layers divided into multiple areas by a grid, as a starting area, and a rectangular area that is the end area, as an end area; a wiring cost addition unit adds a wiring cost each time the search for a wiring path from the starting area to the end area is advanced by one rectangular area; a via cost multiplication unit multiplies the wiring cost by the via cost of a multi-cut via that is placed in one of the wiring areas of the multiple layers; and The method includes a cost adder adding an obstacle cost based on the obstacle information stored in the obstacle list storage unit, a tallying unit storing the tally of the wiring cost, the via cost, and the obstacle cost in the rectangular area list, a route search unit searching for the wiring route in the wiring area of the multiple layers based on the tallying result, a wiring unit connecting the start area and the end area, and a via placement unit placing the multi-cut via in one of the wiring areas of the multiple layers.

Patent document 4 shows a method for designing a semiconductor integrated circuit device that takes into account the area where a wiring obstacle is placed when placing a target wiring with multiple thin wires. This invention includes the steps of generating circuit diagram data representing multiple macros and their connections, generating a netlist representing the wiring between each of the multiple macros and the nodes connected to it based on the circuit diagram data, generating division shape data representing the target wiring among the multiple wirings and including the number of narrowest thin wires based on the netlist, placing the multiple macros in a coordinate area, determining a wiring path for placing the target wiring in an area of the coordinate area other than the area where the multiple macros are placed, and changing the number included in the division shape data to the number per layer and the number of layers based on the wiring path.

JP 2006-278886 A Japanese Patent Application Publication No. 3-124045 JP 2006-65403 A JP 2010-211332 A

As described above, in conventional semiconductor layout design, various efforts have been made to deal with the existence of complex design rules such as multi-spacing rules and the presence of obstacles with complex shapes, but there has been a problem in that automatic shape-based routing cannot complete the wiring. The present invention aims to provide a wiring design device for semiconductor integrated circuits, a wiring design method for semiconductor integrated circuits, and a wiring design program for semiconductor integrated circuits that can deal with the existence of such complex design rules and the presence of obstacles with complex shapes.

The wiring design device for a semiconductor integrated circuit according to this embodiment includes a wiring area/non-wiring area information calculation means for calculating wiring area information and non-wiring area information based on size information of existing metal provided in the design target area and size information of the wiring to be drawn in, a matrix division means for dividing the wiring area into a matrix and generating rectangular cells, a division cell generation means for generating vertical and horizontal line segments throughout the design target area based on corners generated in the wiring area by the rectangular cells to generate division cells of existing wiring, division cells of space, and division cells of the wiring area, an origin division cell selection means for selecting an origin division cell based on the start point of wiring, and a first cell candidate selection means for selecting a first cell candidate in a direction parallel to the vertical line or horizontal line segment, with the vertical direction from the origin division cell to the end point of the wiring as the forward direction, by extending the origin division cell until it hits the space area. a first candidate cell acquisition means for acquiring a second cell candidate from among the first cell candidates, starting from the cell that has hit the space area at the shortest distance, and extending the cell in the horizontal direction perpendicular to the vertical direction to the end point direction as the new forward direction until it hits the space area; a third candidate cell acquisition means for acquiring a third cell candidate from among the second cell candidates, starting from the cell that has hit the space area at the shortest distance, and extending the cell in the vertical direction perpendicular to the horizontal direction to the end point direction as the new forward direction until it hits the space area; and a fourth, fifth, ..., nth candidate cell acquisition means for acquiring the necessary fourth, fifth, ..., n (integer) cell candidates in the same manner, and the nth candidate cell acquisition means is characterized in that it acquires the nth cell candidate until it hits the end point.

In the wiring design device for a semiconductor integrated circuit according to this embodiment, the starting point partition cell selection means and each-time candidate cell acquisition means select partition cells so that they have a width (design-time cell width) equal to or greater than a predetermined wiring width.

The wiring design device for semiconductor integrated circuits according to this embodiment is characterized in that the size information of the existing metal provided in the design target area is its width and space dimensions, and the size information of the wiring to be drawn in is its width and space dimensions.

The wiring design device for a semiconductor integrated circuit according to this embodiment is characterized by having a final wiring area selection means that generates a confirmed cell by connecting cell candidates from a start point to an end point, and selects a wiring area drawn with an optimal wiring width as a final wiring area within the wiring area generated by the confirmed cell.

In the wiring design device for a semiconductor integrated circuit according to this embodiment, the final wiring area selection means creates several candidate wiring areas using optimal wiring widths within the wiring area generated by the confirmed cells, and selects the optimal candidate wiring area as the final wiring area using the area edge method.

The wiring design method for a semiconductor integrated circuit according to this embodiment includes a wiring area/non-wiring area information calculation step for calculating wiring area information and non-wiring area information based on size information of existing metal provided in the design target area and size information of the wiring to be drawn in, a matrix division step for dividing the wiring area into a matrix and generating rectangular cells, a partition cell generation step for generating vertical and horizontal line segments throughout the design target area based on corners generated in the wiring area by the rectangular cells to generate partition cells of existing wiring, partition cells of space, and partition cells of the wiring area, an origin partition cell selection step for selecting an origin partition cell based on the start point of wiring, and a first cell candidate selection step for selecting a first cell candidate in a direction parallel to the vertical line segment or the horizontal line segment, the vertical direction from the origin partition cell to the end point of the wiring being the forward direction, by extending the origin partition cell until it hits the space area. a first candidate cell acquisition step for obtaining a second cell candidate from among the first cell candidates, starting from the cell that has hit the space area at the shortest distance, and extending the cell in the horizontal direction perpendicular to the vertical direction as the new forward direction to the end point direction until it hits the space area; a third candidate cell acquisition step for obtaining a third cell candidate from among the second cell candidates, starting from the cell that has hit the space area at the shortest distance, and extending the cell in the vertical direction perpendicular to the horizontal direction as the new forward direction to the end point direction until it hits the space area; and a fourth, fifth, ..., nth candidate cell acquisition step for obtaining the necessary fourth, fifth, ..., n (integer) cell candidates in the same manner, and the nth candidate cell acquisition step is characterized in that it obtains the nth cell candidate until it hits the end point.

In the wiring design method for a semiconductor integrated circuit according to this embodiment, the starting point partition cell selection step and each candidate cell acquisition step are characterized in that the partition cell is selected so that it has a width (design time cell width) equal to or greater than a predetermined wiring width.

The wiring design method for semiconductor integrated circuits according to this embodiment is characterized in that the size information of the existing metal provided in the design target area is its width and space dimensions, and the size information of the wiring to be drawn in is its width and space dimensions.

The wiring design method for a semiconductor integrated circuit according to this embodiment is characterized by including a final wiring area selection step in which a final cell is generated by connecting cell candidates from a start point to an end point, and a wiring area drawn with an optimal wiring width within the wiring area generated by the final cell is selected as the final wiring area.

In the wiring design method for semiconductor integrated circuits according to this embodiment, the final wiring region selection step is characterized in that several candidate wiring regions are created with optimal wiring widths within the wiring area generated by the confirmed cells, and the optimal candidate wiring region is selected as the final wiring region by the area edge method.

The wiring program for a semiconductor integrated circuit according to this embodiment includes a wiring area/non-wiring area information calculation means for calculating wiring area information and non-wiring area information based on size information of existing metal provided in a design target area and size information of wiring to be drawn in, a matrix division means for dividing a wiring area into a matrix and generating rectangular cells, a division cell generation means for generating vertical and horizontal line segments throughout the entire design target area based on corners generated in the wiring area by the rectangular cells to generate division cells of existing wiring, division cells of space, and division cells of the wiring area, a starting point division cell selection means for selecting a starting point division cell based on the start point of wiring, a first section extending the starting point division cell until it hits the space area, in a direction parallel to the vertical line segment or the horizontal line segment, with the vertical direction from the starting point division cell to the end point of the wiring as the forward direction, The method is characterized in that the computer functions as a first candidate cell acquisition means for acquiring a cell candidate, a second candidate cell acquisition means for acquiring a second cell candidate by extending the cell in the new forward direction until it hits the space area, starting from the cell that hits the space area at the shortest distance among the first cell candidates, in a horizontal direction perpendicular to the vertical direction, with the direction of the end point as the new forward direction, and extending the cell in the new forward direction until it hits the space area, and a third candidate cell acquisition means for acquiring a third cell candidate by extending the cell in the new forward direction until it hits the space area, starting from the cell that hits the space area at the shortest distance among the second cell candidates, in a vertical direction perpendicular to the horizontal direction, with the direction of the end point as the new forward direction, and a fourth, fifth, ..., nth candidate cell acquisition means for acquiring the necessary fourth, fifth, ..., n (integer) cell candidates, and the computer functions as an nth candidate cell acquisition means to acquire the nth cell candidate until it hits the end point.

The wiring program for a semiconductor integrated circuit according to this embodiment is characterized in that it causes the computer to function as the starting point partition cell selection means and each-time candidate cell acquisition means to select partition cells having a width equal to or greater than a predetermined wiring width (design-time cell width).

The wiring program for semiconductor integrated circuits according to this embodiment is characterized in that the size information of the existing metal provided in the design target area is its width and space dimensions, and the size information of the wiring to be drawn in is its width and space dimensions.

In the wiring program for a semiconductor integrated circuit according to the present embodiment, the computer further comprises:
The method is characterized in that it functions as a final wiring area selection means for generating a confirmed cell by connecting cell candidates from a starting point to an end point, and selecting a wiring area drawn with an optimal wiring width as a final wiring area within the wiring area generated by the confirmed cell.

The wiring program for semiconductor integrated circuits according to this embodiment is characterized in that the computer is caused to function as the final wiring area selection means to create several candidate wiring areas with optimal wiring widths within the wiring area generated by the confirmed cells, and to select the optimal candidate wiring area as the final wiring area using the area edge method.

FIG. 1 is a configuration diagram of a wiring design device for a semiconductor integrated circuit according to an embodiment of the present invention implemented by a computer. FIG. 2 is a diagram showing each unit for realizing a wiring design program for a semiconductor integrated circuit according to an embodiment of the present invention. 4 is a flowchart showing the operation of the wiring design apparatus for a semiconductor integrated circuit according to the present embodiment. 1 is a diagram showing an example of the inside of a design target area in which design is performed by the wiring design device for a semiconductor integrated circuit according to the present embodiment; 1 is a diagram showing an example of length and width, which is size information relating to a design target area designed by the wiring design device for a semiconductor integrated circuit according to the embodiment, and size information of existing metal provided in the design target area; 4 is a diagram showing a non-wiring area calculated by the wiring design device for a semiconductor integrated circuit according to the embodiment; 2 is a diagram showing a wiring area calculated by the wiring design device for a semiconductor integrated circuit according to the embodiment; 1 is a diagram showing a matrix division by the wiring design device for a semiconductor integrated circuit according to the embodiment; 2 is a diagram showing a wiring area generated by the wiring design device for a semiconductor integrated circuit according to the embodiment; 4 is a diagram showing a divided area generated by the wiring design device for a semiconductor integrated circuit according to the embodiment; 1 is a diagram showing the initial state of a wiring area of wiring generated by the wiring design device for a semiconductor integrated circuit according to the embodiment; 13 is a diagram showing the state of the wiring area when a section cell is selected so as to have a width equal to or greater than a predetermined wiring width (designed cell width) at the beginning of wiring generated by the wiring design device for a semiconductor integrated circuit according to the present embodiment. FIG. 1 is a diagram showing the state of the wiring area when a first candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; 11 is a diagram showing the state of the wiring area when a second candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; FIG. 11 is a diagram showing the state of the wiring area when a third candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; FIG. 13 is a diagram showing the state of the wiring area when a fourth candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; FIG. 13 is a diagram showing the state of the wiring area when a fifth candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; FIG. 13 is a diagram showing the state of the wiring area when a sixth candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; FIG. 13 is a diagram showing the state of the wiring area when a seventh candidate cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; FIG. 1 is a diagram showing the state of a wiring area when a confirmed cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment; 1 is a diagram showing the state of the wiring area after a confirmed cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment, until a final wiring area is obtained by the area edge method; 1 is a diagram showing the state of the wiring area after a confirmed cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment, until a final wiring area is obtained by the area edge method; 1 is a diagram showing the state of the wiring area after a confirmed cell is obtained by the wiring design device for a semiconductor integrated circuit according to the embodiment, until a final wiring area is obtained by the area edge method; FIG. 1 is a diagram for explaining the first stage of the wiring procedure according to the area edge method. FIG. 13 is a diagram for explaining a second stage of the wiring procedure according to the area edge method. FIG. 13 is a diagram for explaining a third stage of the wiring procedure according to the area edge method. FIG. 13 is a diagram for explaining the fourth stage of the wiring procedure according to the area edge method. FIG. 13 is a diagram for explaining a fifth stage of the wiring procedure according to the area edge method. 1 is a diagram showing a transition state of a wiring area for explaining a specific example of the area edge method adopted by the wiring design device for a semiconductor integrated circuit according to the embodiment;

The wiring design device for a semiconductor integrated circuit, the wiring design method for a semiconductor integrated circuit, and the wiring design program for a semiconductor integrated circuit according to the embodiment of the present invention will be described below with reference to the attached drawings. In each drawing, the same reference numerals are used for overlapping configurations, and overlapping descriptions will be omitted. The wiring design device for a semiconductor integrated circuit according to the embodiment of the present invention can be configured by a computer such as a personal computer or a workstation as shown in FIG. 1.

In this computer, the CPU 10 configures a wiring design device for semiconductor integrated circuits using programs and data in the main memory 11. The CPU 10 is connected to an external memory interface 13, an input interface 14, a display interface 15, and a network interface 16 via a bus 12.

The external storage interface 13 is connected to an external storage device 23. The external storage device 23 stores programs and data for the operation of the wiring design device for semiconductor integrated circuits, which can be read by the CPU 10 into the main memory 11 as appropriate for use. For this reason, the external storage device 23 stores programs for implementing each means of the wiring design device for semiconductor integrated circuits, which will be described later. The input interface 14 is connected to an input device 24 such as a keyboard or touch panel, and a pointing device 22 such as a mouse. The display interface 15 is connected to a display device 25 having a screen such as an LCD, which realizes the display of images and the like required for the wiring design device for semiconductor integrated circuits. The network interface 16 is connected to a network, and the wiring design device for semiconductor integrated circuits can import data and the like to be used for wiring design. The input interface 14 is connected to an input device 24 such as a keyboard for inputting data and commands, and a pointing device 22 such as a mouse, and the input device 24 and the mouse 22 can be operated to cause the wiring design device for semiconductor integrated circuits to perform the necessary operations and processing.

The external storage device 23 stores the various means for implementing a wiring design program for semiconductor integrated circuits, as shown in FIG. 2. These means are composed of a wiring area/non-wiring area information calculation means 31, a matrix division means 32, a section cell generation means 33, a starting point section cell selection means 34, a first candidate cell acquisition means 35, a second candidate cell acquisition means 36, a third candidate cell acquisition means 37, ..., an nth candidate cell acquisition means 38, and a final wiring area selection means 39.

The wiring design device for semiconductor integrated circuits according to this embodiment operates according to a program corresponding to the flowchart shown in FIG. 3. The operation will be described below based on this flowchart. First, size information related to the design target area, size information of existing metal (existing wiring) provided in the design target area, size information of wiring to be drawn in, etc. are retrieved from, for example, the external storage device 23, and the design is started (S11).

For example, assume that there is a design target area R as shown in FIG. 4, and that the width and space are determined as size information of the existing metal provided in the design target area R, and the width and space are determined as size information of the wiring to be drawn in. Here, as shown in FIG. 5, two types of existing metal, "thick" and "thin", are arranged as shown in the filled-in rectangle within the dashed line in FIG. 4. In this case, the length and width dimensions as size information related to the design target area R, the width and space dimensions as size information of the existing metal provided in the design target area, and the width and space dimensions as size information of the wiring to be drawn in are stored in the external storage device 23 in the form of a table as shown in FIG. 5.

In step S11 above, based on the size information of the existing metal provided in the design target area retrieved from the external storage device 23 and the size information of the wiring to be drawn in, wiring area information and non-wiring area information are calculated (S12, wiring area/non-wiring area information calculation means 31). At this time, the non-wiring area described as "NO#PATH##AREA" in FIG. 6 is calculated. At this time, the area is calculated taking into account the MSR (multi-spacing rule) of the existing metal and the wiring to be drawn in. Furthermore, by performing a NOT logical operation on the area in FIG. 6, the wiring area described as "PATH##AREA" in FIG. 7 is calculated.

Next, the wiring area is divided into a matrix to generate rectangular cells (S13, matrix division means 32). That is, the wiring area shown in FIG. 7 is originally divided into a matrix, but here, an example is simplified for explanation. In the case of a design using the maze method, it is assumed that a matrix of squares that maintain the wiring width is laid out. However, since this embodiment is a method that takes MSR into account, it is difficult to lay out squares with a regular shape. For this reason, rectangular squares are created based on the corners (vertices) of the polygonal wiring area. As a result, the generated squares are not square, but are rectangular with various shapes. The coordinate extraction method is shown in FIG. 8. That is, the wiring area shown in FIG. 8(a) is divided into several rectangular cells as shown in FIG. 8(b).

Next, using the corners created in the wiring area by the rectangular cells as a reference, vertical and horizontal line segments are generated throughout the entire design area to generate partition cells for existing wiring, partition cells for space, and partition cells for the wiring area (S14, partition cell generation means 33). As a result, partition cells as shown in FIG. 10 are generated for the wiring area as shown in FIG. 9. The difference between FIG. 10 and FIG. 8(b) is that in FIG. 10, spare (extra) line segments are generated so that the partition cells have a width equal to or greater than a predetermined wiring width (design time cell width). For example, one horizontal partition cell is generated between partition cells M and N in FIG. 10.

Once the segment cells have been generated, the starting segment cell S and the ending segment cell G are then selected based on the starting point of the wiring (S15, starting segment cell selection means 34). This determines the extension direction shown by the arrow in FIG. 11. Here, the starting segment cell selection means 34 selects segment cells that have a width equal to or greater than the specified wiring width (design time cell width). As a result, the starting segment cell has three times the width in the horizontal direction, as shown in FIG. 12.

Next, the starting point section cell is extended in a direction parallel to the vertical or horizontal line segment, from the starting point section cell to the end point of the wiring, to obtain a first (i=1) cell candidate up to the space region (S16, first candidate cell acquisition means 35). As a result, the first candidate cell is obtained, as shown by hatching in FIG. 13.

Next, it is detected whether the wiring has reached the end point (S17), and if the result is NO, i is incremented by one (S18), and the process returns to step S16. The cell that hits the space area at the shortest distance among the first cell candidates is taken as the starting point, and the direction of the end point in the horizontal direction perpendicular to the vertical direction is taken as the new forward direction, and the cell is extended forward to hit the space area to obtain a second (i=2) cell candidate (S16, second candidate cell acquisition means 36). Here, the first cell candidate hits the space area at the partition cell G, so it bends and extends in the horizontal line direction. Here, the each-time candidate cell acquisition means (second candidate cell acquisition means 36) selects a partition cell so that it has a width (design time cell width) greater than or equal to a predetermined wiring width. The horizontal line direction is set to be greater than or equal to the width of the two partition cells used in this embodiment. As a result, a second candidate cell is obtained as shown by hatching in FIG. 14. When a second candidate cell is obtained, the previous candidate cell, the first candidate cell, is made the confirmed cell (a cell whose width or length does not change).

Next, it is detected whether the wiring has reached the end point (S17), and if it is NO, i is incremented by one (S18) and the process returns to step S16. Next, the third (i=3) cell candidate is obtained by extending the cell in the vertical direction perpendicular to the horizontal direction until it reaches the space area, using the cell that hits the space area in the shortest distance among the second cell candidates as the starting point and extending the cell in the new forward direction until it hits the space area (S16, third candidate cell acquisition means 37). As a result, the third candidate cell is the three divided cells "11" to "13" that extend vertically as shown in FIG. 15, which extend to "k" and hit the space area.

The same process is carried out thereafter, with the fourth candidate cell shown in FIG. 16, the fifth candidate cell shown in FIG. 17, the sixth candidate cell shown in FIG. 18, and the seventh candidate cell shown in FIG. 19, and in this embodiment, the seventh candidate cell reaches the end point. When the candidate cell reaches the end point, the previous candidate cell is set as a confirmed cell (a cell whose width and length are selected as being appropriate according to the rules of this embodiment) as shown in FIG. 20. From this point onwards, the computer performs processing as the final wiring area selection means 39. Note that when the fourth candidate cell shown in FIG. 16 hits the space area, when changing direction and moving vertically, the hit division cell "19" is not used, and division cell "18" is set as the fourth candidate cell because the width of division cell "19" is narrow and one division cell "18" is wide enough.

When the starting point and the end point are connected by the confirmed cells in the manner described above, the wiring area drawn with the optimal wiring width within the wiring area generated by the confirmed cells is selected as the final wiring area. Here, the optimal wiring width refers to a wiring width set based on a concept different from the width (design time cell width) that is equal to or greater than the predetermined wiring width used when the starting point division cell selection means and each time candidate cell acquisition means find and select division cells at the time of design within the wiring area generated by the confirmed cells. In general, it can be the smallest wiring width that can be adopted.

Then, in order to select the final wiring area, several candidate wiring areas are created with the optimal wiring width within the wiring area generated by the above-mentioned confirmed cells, and the optimal candidate wiring area is selected as the final wiring area by the area edge method. For example, in the example of FIG. 20, a wiring area is generated by the confirmed cells. As shown in FIG. 21, a candidate wiring area 10A having an optimal wiring width can be created so as to follow the upper boundary of the wiring area, and as shown in FIG. 22, a candidate wiring area 10B having an optimal wiring width can be created so as to follow the lower boundary of the wiring area. For the candidate wiring area 10A and the candidate wiring area 10B, the area with the shortest wiring length is basically selected as the final wiring area by the area edge method. As a result, as shown in FIG. 23, only the candidate wiring area 10A is selected as the final wiring area.

Next, the area edge method will be described with reference to Figures 23A, 23B, 23C, 23D, and 23E. As shown in Figures 23A to 23E, the non-routable area is obtained as the hatched portion IH. The start point S and end point E are shown in Figures 23A to 23E. The area that can be wired including the start point S and end point E is extracted as a polygonal shape as the frame W in Figure 23B. The vertex coordinates of the figure are listed. Note that a vertex refers to the corner of the figure. Next, the distance of the upper route UR (Figure 23C) that connects the vertex coordinates from the listed start point S to the end point E is recalculated, and the distance of the lower route DR (Figure 23D) that connects the vertex coordinates from the listed start point S to the end point E is calculated, and an appropriate route is selected after evaluating the route. Here, the appropriate route can be a route with a short route, a route with a small number of vertices, or a route with a fixed lower route, which can be set appropriately by the operator in advance. Then, by forming a wiring LL from a starting point S to an end point E along the path extracted above, taking into account factors such as the wiring width, as shown in FIG. 23E, the wiring area can be compacted and connected, making it possible to minimize dead space and ensure a large free space.

Figure 24 shows a specific example of wiring performed by the area edge method. In the area edge method of this embodiment, when the wiring-prohibited area is obtained as a black part as shown in Figure 24 (a), a polygonal shape as shown in Figure 24 (b) is generated as a wiring area for the NOT operation area of the wiring-prohibited area. For example, candidate wiring area 20A and candidate wiring area 20B are obtained along the edge (boundary) of this wiring area (Figure 24 (c)). Of course, a large number of candidate wiring areas may be generated between candidate wiring area 20A and candidate wiring area 20B. Among these candidate wiring areas, the optimal one is selected as the final wiring area. The optimal one may be the one with the shortest wiring length. Also, when there are multiple ones with the shortest wiring length, the one with the fewest number of vertices (number of bends) can be selected as the final wiring area. In the example of Figure 24, candidate wiring area 20B is selected as the final wiring area as shown in Figure 24 (d).

This embodiment makes it possible to connect routes that could not be routed using conventional shape-based automatic routing, leading to improved wiring quality and design shrink.

10 CPU
10A Candidate wiring area 10B Candidate wiring area 11 Main memory 12 Bus 13 External storage interface 14 Input interface 15 Display interface 16 Network interface 20A Candidate wiring area 20B Candidate wiring area 22 Pointing device 23 External storage device 24 Input device 25 Display device 31 Wiring area/non-wiring area information calculation means 32 Matrix division means 33 Section cell generation means 34 Starting point section cell selection means 35 First candidate cell acquisition means 36 Second candidate cell acquisition means 37 Third candidate cell acquisition means 38 nth candidate cell acquisition means 39 Final wiring area selection means

Based on the size information of the existing metal provided in the design target area and the size information of the wiring to be drawn in, which are retrieved from the external storage device 23 in step S11, wiring area information and non-wiring area information are calculated (S12, wiring area/non-wiring area information calculation means 31). At this time, the non-wiring area described as " NO_PATH_AREA " in Fig. 6 is calculated. At this time, the area is calculated taking into account the MSR (multi-spacing rule) of the existing metal and the wiring to be drawn in. Furthermore, by performing a NOT logical operation on the areas in Fig. 6, the wiring area described as " PATH_AREA " in Fig. 7 is calculated.

Claims (15)

a wiring area/non-wiring area information calculation means for calculating wiring area information and non-wiring area information based on size information of existing metal provided in a design target area and size information of wiring to be drawn in;
a matrix division means for dividing a wiring area into a matrix and generating rectangular cells;
a partition cell generating means for generating vertical and horizontal line segments throughout a design target area based on corners generated in a wiring area by the rectangular cells, thereby generating partition cells of existing wiring, partition cells of spaces, and partition cells of wiring areas;
a starting point cell selection means for selecting a starting point cell based on a starting point of wiring;
a first candidate cell acquiring means for acquiring a first candidate cell by extending the starting point section cell in a direction parallel to the vertical line segment or the horizontal line segment, the vertical direction being from the starting point section cell to an end point of the wiring, until the starting point section cell abuts on a space region;
a second candidate cell acquisition means for acquiring a second cell candidate from among the first cell candidates, which is determined as a starting point from a cell that abuts on the space region at the shortest distance, and which extends the cells in a horizontal direction perpendicular to the vertical direction and toward the end point as a new forward direction, until the cell abuts on the space region;
a third candidate cell acquisition means for acquiring a third cell candidate from among the second cell candidates, starting from a cell that abuts on the space region at the shortest distance, and extending the cell in the new forward direction up to the space region by setting a direction of the end point in a vertical direction perpendicular to the horizontal direction as a new forward direction;
Similarly, there are provided fourth, fifth, ..., n-th candidate cell acquisition means for acquiring necessary fourth, fifth, ..., n-th (integer) cell candidates,
The n-th candidate cell acquisition means acquires n-th candidate cells up to the end point, in accordance with the wiring design apparatus for a semiconductor integrated circuit. The wiring design device for a semiconductor integrated circuit according to claim 1, characterized in that the starting point section cell selection means and each-time candidate cell acquisition means select section cells having a width (design time cell width) equal to or greater than a predetermined wiring width. The wiring design device for semiconductor integrated circuits according to claim 1, characterized in that the size information of the existing metal provided in the design target area is its width and space dimensions, and the size information of the wiring to be drawn in is its width and space dimensions. The wiring design device for a semiconductor integrated circuit according to claim 1, further comprising a final wiring area selection means for generating a confirmed cell by connecting cell candidates from a start point to an end point, and selecting a wiring area drawn with an optimal wiring width as a final wiring area within the wiring area generated by the confirmed cell. The wiring design device for a semiconductor integrated circuit according to claim 4, characterized in that the final wiring area selection means creates several candidate wiring areas with optimal wiring widths within the wiring area generated by the confirmed cells, and selects the optimal candidate wiring area as the final wiring area using an area edge method. a wiring area/non-wiring area information calculation step of calculating wiring area information and non-wiring area information based on size information of existing metal provided in the design target area and size information of wiring to be drawn in;
a matrix division step of dividing a wiring area into a matrix and generating rectangular cells;
a partition cell generating step of generating vertical and horizontal line segments throughout the entire design target area based on corners generated in the wiring area by the rectangular cells, thereby generating partition cells of existing wiring, partition cells of spaces, and partition cells of the wiring area;
a starting point cell selection step of selecting a starting point cell based on a starting point of wiring;
a first candidate cell acquisition step of acquiring a first cell candidate by extending the starting point section cell in a direction parallel to the vertical line or the horizontal line segment, the vertical direction being from the starting point section cell to an end point of the wiring, until the starting point section cell hits a space region;
a second candidate cell acquisition step of obtaining a second cell candidate from among the first cell candidates, starting from a cell that abuts on the space region at the shortest distance, and extending the cell in the new forward direction until the cell abuts on the space region in a horizontal direction perpendicular to the vertical direction and the direction of the end point as a new forward direction;
a third candidate cell acquisition step of obtaining a third cell candidate by extending the cell in the new forward direction from the second cell candidate that is the shortest distance from the starting point to the end point in a vertical direction perpendicular to the horizontal direction, until the cell reaches the space region;
and a fourth, fifth, ..., n-th candidate cell acquisition step of acquiring necessary fourth, fifth, ..., n-th (integer) cell candidates in the same manner.
The n-th candidate cell acquisition step is characterized in that the n-th cell candidate is acquired up to the end point. The wiring design method for a semiconductor integrated circuit according to claim 6, characterized in that the starting point partition cell selection step and each candidate cell acquisition step select partition cells so that they have a width (design time cell width) greater than or equal to a predetermined wiring width. The wiring design method for semiconductor integrated circuits described in claim 6, characterized in that the size information of the existing metal provided in the design target area is its width and space dimensions, and the size information of the wiring to be drawn in is its width and space dimensions. The wiring design method for a semiconductor integrated circuit according to claim 6, further comprising a final wiring area selection step of generating a confirmed cell by connecting cell candidates from a start point to an end point, and selecting a wiring area drawn with an optimal wiring width within the wiring area generated by the confirmed cell as a final wiring area. The wiring design method for a semiconductor integrated circuit according to claim 9, characterized in that in the final wiring region selection step, several candidate wiring regions are created with optimal wiring widths within the wiring area generated by the confirmed cells, and the optimal candidate wiring region is selected as the final wiring region by an area edge method. A computer constituting a wiring design device for a semiconductor integrated circuit,
a wiring area/non-wiring area information calculation means for calculating wiring area information and non-wiring area information based on size information of existing metal provided in a design target area and size information of wiring to be drawn in;
A matrix division means for dividing a wiring area into a matrix and generating rectangular cells;
a partition cell generating means for generating vertical and horizontal line segments throughout the entire design target area based on corners generated in the wiring area by the rectangular cells, thereby generating partition cells of existing wiring, partition cells of spaces, and partition cells of the wiring area;
a starting point cell selection means for selecting a starting point cell based on a starting point of wiring;
a first candidate cell acquiring means for acquiring a first candidate cell by extending the starting point section cell in a direction parallel to the vertical line or the horizontal line segment, the vertical direction being from the starting point section cell to an end point of the wiring, until the starting point section cell abuts on a space region;
a second candidate cell acquisition means for acquiring a second cell candidate from among the first cell candidates, which is determined as a starting point from a cell that abuts on the space region at the shortest distance, and which extends the cells in a horizontal direction perpendicular to the vertical direction and toward the end point as a new forward direction, until the cell abuts on the space region;
a third candidate cell acquisition means for acquiring a third cell candidate from among the second cell candidates, starting from a cell that abuts on the space region at the shortest distance, and extending the cells in the new forward direction up to the point where the third cell candidate abuts on the space region, the third candidate cell acquisition means defining a direction of the end point in a vertical direction perpendicular to the horizontal direction as a new forward direction;
Similarly, a fourth, fifth, ..., nth candidate cell acquisition means acquires necessary fourth, fifth, ..., nth (integer) cell candidates;
Function as a
a program for designing wiring for a semiconductor integrated circuit, the program causing the computer to function as n-th candidate cell acquisition means for acquiring an n-th candidate cell up to the end point; The program for wiring design of a semiconductor integrated circuit according to claim 11, characterized in that the computer is made to function as the starting point division cell selection means and each time candidate cell acquisition means to select a division cell having a width equal to or greater than a predetermined wiring width (design time cell width). The wiring design program for semiconductor integrated circuits described in claim 11, characterized in that the size information of the existing metal provided in the design target area is its width and space dimensions, and the size information of the wiring to be drawn in is its width and space dimensions. The computer further comprises:
12. The program for wiring design of a semiconductor integrated circuit according to claim 11, characterized in that the program functions as a final wiring area selection means for generating a confirmed cell by connecting cell candidates from a start point to an end point, and selecting a wiring area drawn with an optimal wiring width as a final wiring area within a wiring area generated by the confirmed cell. The program for wiring design of a semiconductor integrated circuit according to claim 14, characterized in that the computer is made to function as the final wiring area selection means by creating several candidate wiring areas with optimal wiring widths within the wiring area generated by the confirmed cells, and selecting the optimal candidate wiring area as the final wiring area using an area edge method.

Images