JP2015210703A - Cad device, cell and layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve efficiency of design task of a circuit.SOLUTION: A CAD device 101 comprises an ECO-DOT cell D and plural ECO cells C1-C4 in a layout area r of a design target circuit, based on layout data of the design target circuit. The ECO-DOT cell D comprises plural input terminal I1-I4, and output terminal Y connected to respective input terminals of the plural input terminals, by wirings having the same length. The CAD device 101 is configured so that, respective output terminals of the plural ECO cells C1-C4 are connected to respective input terminals I1-I4 of the ECO-DOT cell D, by wirings having the same length.

Description

  The present invention relates to a CAD (Computer Aided Design) device, a cell, and a layout method.

  Conventionally, in the circuit design work, when the input cell drive capacity is insufficient due to the distance from the input cell to the output cell on the circuit to be designed, a buffer having the drive capacity is input without logically doing anything. A drive capacity may be supplemented by connecting between the cell and the output cell. At this time, the deficient driving capability can be compensated by connecting a buffer corresponding to the deficient driving capability between the input cell and the output cell from among the buffers having different driving capabilities. Here, as the drive capacity of the buffer increases, the area occupied by the buffer in the layout area increases. Related prior art includes, for example, searching for logic synthesis using wired AND or wired OR if the target technology allows dot connections, ie, wired AND or wired OR. Also, a protective circuit is inserted that converts the selector circuit to a wired OR type selector circuit and prevents the output of the wired OR type selector circuit from going into a high impedance state when nothing is selected in the 3-state buffer of the wired OR type selector circuit. There is technology to do.

JP-A-61-88371 JP-A-10-171844

  However, according to the prior art, when an area where a buffer according to the deficient driving capability cannot be secured cannot be secured, for example, an area where the buffer can be placed by re-arranging the placement and wiring of the circuit to be designed is secured. It takes time for the design work by the designer.

  In addition, it is conceivable that buffers that can be arranged in an area narrower than an area where buffers corresponding to the deficient driving ability are connected in parallel to obtain a driving ability equivalent to the buffer corresponding to the deficient driving ability. Here, to connect the buffers in parallel to make up for the deficient driving capability, it is required to make the wiring lengths of the dots themselves and the respective buffers the same when connecting a plurality of buffers in dots. However, with existing layout tools, it is not possible to make the wiring length connecting the dot and each buffer the same, so the wiring length of the dot and each buffer is made the same by the designer's manual work. Therefore, it takes time for the design work by the designer.

  In one aspect, an object of the present invention is to provide a CAD device, a cell, and a layout method capable of improving the efficiency of circuit design work.

  According to one aspect of the present invention, a cell having a plurality of input terminals, an output terminal connected to each input terminal of the plurality of input terminals, and a plurality of buffers are used as layout data for the circuit to be designed. Based on the above, a CAD device that is arranged in a layout area of a circuit to be designed, and that connects each output terminal of each of the arranged buffers and each input terminal of a cell by wires of the same length, and a layout method Is proposed.

  According to another aspect of the present invention, there are a plurality of input terminals, and an output terminal connected by a wiring having the same length from each of the plurality of input terminals, and each of the plurality of input terminals A cell is proposed in which the output terminals of a plurality of buffers are connected to each other by wires of the same length.

  According to one embodiment of the present invention, it is possible to improve the efficiency of circuit design work.

FIG. 1 is an explanatory diagram illustrating an operation example of the CAD apparatus 101. FIG. 2 is an explanatory diagram showing a first example of the layout of the ECO-DOT cell D. As shown in FIG. FIG. 3 is an explanatory diagram showing a second example of the layout of the ECO-DOT cell D. As shown in FIG. FIG. 4 is an explanatory diagram showing a third example of the layout of the ECO-DOT cell D. As shown in FIG. FIG. 5 is an explanatory diagram illustrating an example of a logical function of the ECO-DOT cell D. FIG. 6 is a block diagram illustrating a hardware configuration example of the CAD apparatus 101. FIG. 7 is a block diagram illustrating a functional configuration example of the CAD apparatus 101. FIG. 8 is an explanatory diagram showing an example of the layout of the ECO bulk cell. FIG. 9 is an explanatory diagram showing an example of the layout of the ECO cell C. FIG. 10 is an explanatory diagram showing an example of adding an ECO cell C for four times driving. FIG. 11 is an explanatory diagram illustrating an arrangement example of the ECO cells C. FIG. 12 is an explanatory diagram illustrating an arrangement example of the ECO-DOT cells D. FIG. 13 is an explanatory diagram showing a connection example from the ECO-DOT cell D to the output cell B. FIG. 14 is a flowchart illustrating an example of a layout processing procedure. FIG. 15 is a flowchart illustrating an example of the P & R ECO processing procedure.

  Embodiments of a disclosed CAD device, cell, and layout method will be described in detail below with reference to the drawings.

  FIG. 1 is an explanatory diagram illustrating an operation example of the CAD apparatus 101. The CAD device 101 according to the present embodiment is a computer that supports circuit design. The CAD device 101 is a personal computer, for example, and may be a server or the like. Specifically, for example, the CAD device 101 uses, as layout processing, design data of a design target circuit described in RTL (Register Transfer Level), a constraint condition that the design target circuit must comply with, and a library, Perform logic synthesis to obtain a netlist. The net list indicates connection information between cells. Hereinafter, the connection between cells may be referred to as “net”. Next, the CAD apparatus 101 performs placement and routing (Place & Route: P & R) on the net list, performs timing analysis, and outputs the net list and layout data. The layout data is data obtained by placement and routing, for example, data according to a format such as GDS.

  Here, with the high integration of semiconductor integrated circuits, there is a demand for reduction of areas between chip cell arrays and effective use of vacant areas. A technique called ECO (Engineering Change Order) is performed as a technique for effectively utilizing the vacant area. ECO is a technology that partially corrects errors found at the final stage in design and development. Specific examples of the contents to be corrected include partial correction of the logic circuit, improvement of some element arrangements in the layout design, and wiring correction.

  In ECO, after placing and routing a cell of a circuit to be designed, logic adjustment may be performed to correct some error. For example, for a circuit connecting two cells, the wiring length between the two cells may become longer due to a logic change. In a net having a long wiring length between cells, signal delay increases due to parasitic elements in the layout wiring. Therefore, in general, the increase in signal delay is adjusted by inserting a repeater cell and supplementing the driving capability. A repeater cell is a buffer that is inserted in the middle of connection in order to reduce path delay when the wiring connecting circuit blocks is long. In this case, logic adjustment can be performed by ECO without changing the cell arrangement.

  The repeater cell inserted in the ECO is hereinafter referred to as “ECO cell”. Further, the place where the ECO cell can be arranged is on a cell arranged in advance as an area where the ECO cell is arranged before the cell arrangement of the circuit to be designed is determined. The previously arranged cells are referred to as “ECO bulk cells”. An example of the layout of the ECO cell will be described later with reference to FIG. An example of the layout of the ECO bulk cell will be described later with reference to FIG. As shown in FIG. 9, there are a plurality of types of ECO cells depending on the magnitude of the driving capability to be supplemented, and an ECO cell corresponding to the insufficient driving capability is connected between the input cell and the output cell. By doing so, the deficient driving ability can be compensated. Here, as the drive capability of the ECO cell increases, the area occupied by the ECO cell increases. In the following description, when it is simply described as “ECO cell”, it refers to an ECO cell arranged on one ECO bulk cell.

  Here, it is assumed that a situation occurs in which it is desired to obtain a driving capability that is a multiple of the driving capability of an ECO cell for one ECO bulk cell. In this case, when there is a place where a plurality of ECO bulk cells are continuous, it can be replaced with an ECO cell having a multiple of driving capability. However, in recent years, further enhancement of LSI (Large Scale Integration) integration has been sought, and it has become impossible to insert many ECO bulk cells that cause a reduction in integration into the layout area of the circuit to be designed. It has become difficult to place them.

  Therefore, it is conceivable to obtain a plurality of times of driving capability by connecting a plurality of ECO cells in parallel using non-adjacent ECO bulk cells. Here, when a plurality of ECO cells are connected in parallel, dot connection from the output of the plurality of ECO cells occurs. In order to obtain a multiple drive capability by connecting a plurality of ECO cells in parallel, the wiring length from the plurality of ECO cells to the dot connection is made the same.

  However, when making the wiring length the same in automatic wiring, it is possible to set the wiring length to be the same for different nodes, but since a plurality of ECO cells to dot connections are handled as one net, one It is difficult to set the wiring length in one net to be the same. If manual wiring is performed by the designer, the wiring length in one net can be set to be the same, but manual wiring takes a lot of trouble.

  Therefore, the CAD apparatus 101 according to the present embodiment arranges a connection-dedicated cell and a plurality of ECO cells in the layout area, and each of the output terminals of the plurality of arranged ECO cells and the connection-dedicated cell. A plurality of input terminals are connected to each other by wires having the same length. Hereinafter, the cell dedicated for connection is referred to as an “ECO-DOT cell”. The ECO-DOT cell is a cell having a plurality of input terminals and an output terminal connected to each input terminal of the plurality of input terminals by wires having the same length. Further, the ECO-DOT cell does not have a transistor element. Here, the length of the wiring connecting each input terminal and the output terminal is the length of the wiring from each input terminal to the output terminal. Moreover, a part of wiring from each input terminal to an output terminal may be shared.

  Hereinafter, an example in which an ECO-DOT cell and a plurality of ECO cells are arranged using FIG. 1 and wirings between a plurality of input terminals of the ECO-DOT cell and a plurality of ECO cells are set to be equal-length wirings will be described below. Show. FIG. 1A schematically shows the layout data of the circuit to be designed. An input cell A and an output cell B are arranged in the layout region r of the design target circuit shown in FIG. As a result of an increase in the wiring length between the input cell A and the output cell B, an error occurs due to the timing analysis, and as a result of the timing analysis so as to supplement the driving capability four times that of one ECO cell. It is assumed that it has been output. Here, a cell provided with a thin hatch in the layout region r shown in FIG. 1A indicates an ECO bulk cell.

  FIG. 1B shows an example in which four ECO cells C1 to C4 and an ECO-DOT cell D are arranged in the layout region r in FIG. FIG. 1B shows an internal layout of the ECO-DOT cell D. Here, a cell provided with a thin hatch in the layout region r shown in FIG. 1B indicates an ECO bulk cell. Further, the ECO cells C1 to C4 are cells to which a dark hatch is added in the layout region r shown in FIG. Similarly, the ECO-DOT cell D is a cell provided with a medium dark hatch in the layout region r shown in FIG.

  The internal layout of the ECO-DOT cell D will be described. The ECO-DOT cell D has a plurality of input terminals I1 to I4 and an output terminal Y connected to each input terminal of the plurality of input terminals I1 to I4 by wires having the same length. Here, the length of the wiring from the input terminal I1 to the output terminal Y, the length of the wiring from the input terminal I2 to the output terminal Y, the length of the wiring from the input terminal I3 to the output terminal Y, and the output from the input terminal I4 The length of the wiring to the terminal Y is the same. A more detailed layout of the ECO-DOT cell will be described with reference to FIGS.

  The CAD apparatus 101 arranges an ECO-DOT cell D and a plurality of ECO cells C1 to C4 in the layout area r of the circuit to be designed based on the layout data of the circuit to be designed. Specifically, the CAD apparatus 101 arranges the ECO-DOT cell D and the plurality of ECO cells C1 to C4 on the ECO bulk cell in the layout data. The CAD apparatus 101 may arrange the ECO-DOT cell D after arranging the ECO cells C1 to C4, or may arrange the ECO cells C1 to C4 after arranging the ECO-DOT cell D. More detailed arrangement examples of the ECO-DOT cell D and the ECO cells C1 to C4 will be described later with reference to FIGS.

  Then, the CAD device 101 connects the plurality of arranged ECO cells C1 to C4 and the input terminals I1 to I4 of the ECO-DOT cell D by wires having the same length. In FIG. 1B, for example, the CAD device 101 connects the ECO cell C1 and the input terminal I1, connects the ECO cell C2 and the input terminal I2, and connects the ECO cell C3 and the input terminal I3. The ECO cell C4 and the input terminal I4 are connected. The CAD device 101 includes a wiring from the ECO cell C1 to the input terminal I1, a wiring from the ECO cell C2 to the input terminal I2, a wiring from the ECO cell C3 to the input terminal I3, and a wiring from the ECO cell C4 to the input terminal I4. Set the length of the wiring up to the same.

  Next, a layout example of the ECO-DOT cell will be described with reference to FIGS. The contents common to the layouts shown in FIGS. 2 to 4, 8, and 9 will be described below. A portion surrounded by a dark hatch in FIGS. 2 to 4, 8, and 9 indicates a metal layer. 2 to 4, 8, and 9, a portion surrounded by a thin hatch with a diagonal line from the upper right to the lower left indicates a polysilicon layer. 2 to 4, 8, and 9, a portion surrounded by a thin hatch with a diagonal line from the upper left to the lower right indicates a diffusion layer. Moreover, the part surrounded by the hatch of the medium darkness by the spot pattern arranged in equal intervals in FIG. 9 shows a contact layer.

  FIG. 2 is an explanatory diagram showing a first example of the layout of the ECO-DOT cell D. As shown in FIG. The ECO-DOT cell D shown in FIG. 2 has four input terminals I1, I2, I3, I4 and one output terminal Y. Here, the wiring lengths between the input terminal I1 and the output terminal Y, between the input terminal I2 and the output terminal Y, between the input terminal I3 and the output terminal Y, and between the input terminal I4 and the output terminal Y are the same. It becomes.

  FIG. 3 is an explanatory diagram showing a second example of the layout of the ECO-DOT cell D. As shown in FIG. The ECO-DOT cell D shown in FIG. 3 has two input terminals I1 and I2 and one output terminal Y. Here, the length of the wiring between the input terminal I1 and the output terminal Y and between the input terminal I2 and the output terminal Y is the same.

  FIG. 4 is an explanatory diagram showing a third example of the layout of the ECO-DOT cell D. As shown in FIG. The ECO-DOT cell D shown in FIG. 4 has six input terminals I1, I2, I3, I4, I5, and I6 and one output terminal Y. Here, between the input terminal I1 and the output terminal Y, between the input terminal I2 and the output terminal Y, between the input terminal I3 and the output terminal Y, between the input terminal I4 and the output terminal Y, and between the input terminal I5 and the output terminal Y. And the length of the wiring between the input terminal I6 and the output terminal Y are the same.

  Here, the lengths of the wirings of the input terminals and the output terminals in the ECO-DOT cell D are the same as shown in FIGS. However, since the deviation of the length of the wiring inside the ECO-DOT cell D is very small compared to the length of the wiring outside the cell, the through current is caused by the deviation of the wiring length inside the ECO-DOT cell D. It is possible to deviate within a range in which no occurrence occurs. Next, an example of the logical function of the ECO-DOT cell D will be described with reference to FIG.

  FIG. 5 is an explanatory diagram illustrating an example of a logical function of the ECO-DOT cell D. The example of FIG. 5 is an example of a logical function in the ECO-DOT cell D when there are four input terminals shown in FIG. The ECO-DOT cell D may be any logic circuit that outputs the same value as the value of each input terminal. 5A and 5B show an example in which the ECO-DOT cell D outputs the logical sum of the input terminals I1 to I4 from the output terminal Y.

  FIG. 5A shows an example in which the function of the ECO-DOT cell D is described by Verilog-HDL (Hardware Description Language). In FIG. 5B, the function of the ECO-DOT cell D is shown using circuit symbols.

  As an example different from the logic circuit of the ECO-DOT cell D shown in FIGS. 5A and 5B, the logical product of each input terminal may be output from the output terminal Y. Here, since the value of the output terminal changes due to the change of the value of any one of the input terminals by using the logical sum, the logical product is adopted as the logic circuit of the ECO-DOT cell D. The signal transmission speed can be improved by adopting the logical sum.

(Example of hardware configuration of CAD device 101)
FIG. 6 is a block diagram illustrating a hardware configuration example of the CAD apparatus 101. The CAD device 101 includes a CPU (Central Processing Unit) 601, a ROM (Read-Only Memory) 602, and a RAM (Random Access Memory) 603. The CAD device 101 also includes a disk drive 604, a disk 605, and a communication interface 606. The CAD apparatus 101 includes a display 607, a keyboard 608, and a mouse 609. Further, the CPU 601 to the disk drive 604 and the communication interface 606 to the mouse 609 are connected by a bus 610, respectively.

  The CPU 601 is an arithmetic processing device that controls the entire CAD device 101. The ROM 602 is a non-volatile memory that stores programs such as a boot program. A RAM 603 is a volatile memory used as a work area for the CPU 601.

  The disk drive 604 is a control device that controls reading and writing of data with respect to the disk 605 according to the control of the CPU 601. As the disk drive 604, for example, a magnetic disk drive, an optical disk drive, a solid state drive, or the like can be employed. The disk 605 is a non-volatile memory that stores data written under the control of the disk drive 604. For example, when the disk drive 604 is a magnetic disk drive, a magnetic disk can be adopted as the disk 605. When the disk drive 604 is an optical disk drive, an optical disk can be adopted as the disk 605. When the disk drive 604 is a solid state drive, a semiconductor memory formed by a semiconductor element, that is, a so-called semiconductor disk can be used as the disk 605.

  The communication interface 606 is a control device that controls an internal interface with the network and controls data input / output from an external device. As the communication interface 606, for example, a modem or a LAN adapter can be employed.

  The display 607 is a device that displays data such as a document, an image, and function information as well as a mouse cursor, an icon, or a tool box. As the display 607, for example, a CRT (Cathode Ray Tube), a TFT (Thin Film Transistor) liquid crystal display, a plasma display, or the like can be employed.

  A keyboard 608 has keys for inputting characters, numbers, various instructions, and the like, and is a device for inputting data. The keyboard 608 may be a touch panel type input pad or a numeric keypad. A mouse 609 is a device for moving a mouse cursor, selecting a range, moving a window, changing a size, and the like. The mouse 609 may be a trackball or a joystick as long as it has the same function as a pointing device.

(Functional configuration example of CAD device 101)
FIG. 7 is a block diagram illustrating a functional configuration example of the CAD apparatus 101. The CAD device 101 includes a control unit 700. The control unit 700 includes an arrangement unit 701 and a connection unit 702. The control unit 700 implements the functions of the placement unit 701 and the connection unit 702 by causing the CPU 601 to execute a program stored in the storage device. Specifically, the storage device is, for example, the ROM 602, the RAM 603, the disk 605, or the like shown in FIG. Alternatively, the functions of the placement unit 701 and the connection unit 702 may be realized by another CPU executing via the communication interface 606. In addition, the processing result of each unit is stored in a register included in the CPU 601, the RAM 603, or the like.

  The placement unit 701 places an ECO-DOT cell D and a plurality of ECO cells C in the layout area r of the design target circuit based on the layout data of the design target circuit.

  Further, the placement unit 701 may place the ECO-DOT cell D and a plurality of ECO cells in the layout region r based on the placement position of the input cell A and the placement position of the output cell B. The input cell A is a cell for inputting values to a plurality of ECO cells C. The output cell B is a cell to which a value output from the output terminal of the ECO-DOT cell D is input.

  The placement unit 701 may place a plurality of ECO cells C in the layout region r based on the placement position of the input cell A and the placement position of the output cell B. Then, the placement unit 701 places the ECO-DOT cell D in the layout area r based on the placement position of the plurality of placed ECO cells C and the placement position of the output cell B. For example, the arrangement unit 701 arranges a plurality of ECO cells C on an ECO bulk cell included in a rectangle whose apexes are the arrangement position of the input cell A and the arrangement position of the output cell B. Then, the placement unit 701 places the ECO-DOT cell D on the ECO bulk cell included in the rectangle whose vertex is the placement position of any one of the plurality of ECO cells C and the placement position of the output cell B. .

  Further, the placement unit 701 may place a plurality of ECO cells C in the layout region r based on an intermediate point between the placement position of the input cell A and the placement position of the output cell B.

  In addition, the placement unit 701 places cells in the layout area r based on an intermediate point between the placement position of any one of the plurality of placed ECO cells C and the placement position of the output cell B. May be.

  The connection unit 702 connects the ECO cells C of the plurality of ECO cells C arranged by the arrangement unit 701 and the input terminals of the ECO-DOT cells D by wires having the same length.

  The connection unit 702 connects the output terminal of the ECO-DOT cell D and the input terminal of the output cell B based on the layout data, and lengths the output terminal of the input cell A and the plurality of ECO cells C. Are connected by the same wiring.

  FIG. 8 is an explanatory diagram showing an example of the layout of the ECO bulk cell. The ECO bulk cell is a cell that is disposed as an area where the ECO cell and the ECO-DOT cell are disposed. Here, the ECO-DOT cell described above is a cell in which metal wiring is added to the ECO cell.

  FIG. 9 is an explanatory diagram showing an example of the layout of the ECO cell C. An ECO cell C shown in (a) of FIG. 9 is an ECO cell of 1 × driving. FIG. 9B shows an ECO cell that is driven twice.

  Next, using FIGS. 10 to 13, as an example of adding four ECO cells C to non-adjacent ECO bulk cells as a layout process, it is equivalent to an ECO cell C of 4 times drive to adjacent ECO bulk cells. An example of realizing the function will be described. Here, the information that the ECO cell C of 4 times drive should be added is obtained from the timing analysis result, for example.

  In the example of FIGS. 10 to 13, description will be made using the ECO-DOT cell D having the four input terminals I1 to I4 shown in FIG. In the following description, in order to omit the description, the net of the cell x and the cell y may be simply referred to as “net x_y”.

(Explanation of layout processing)
FIG. 10 is an explanatory diagram showing an example of adding an ECO cell C for four times driving. FIG. 10 shows a state before the ECO cell is inserted. FIG. 10A schematically shows the layout data, and shows the layout region r before the ECO cell is inserted. An input cell A and an output cell B are arranged in the layout region r shown in FIG. In addition, a cell with a thin hatch in the layout region r in FIG. 10A indicates an ECO bulk cell. As shown by the layout region r in FIG. 10A, the input cell A and the output cell B are connected. Specifically, the layout data shown in FIG. 10 includes an input cell A arrangement position, an output cell B arrangement position, an ECO bulk cell arrangement position, and a wiring position connecting the input cell A and the output cell B. And information to specify.

  As indicated by the layout region r in FIG. 10A, as a result of the improvement of the LSI integration degree, it is impossible to insert many ECO bulk cells that cause a reduction in the integration degree, and the ECO bulk cells are continuously arranged. It is particularly difficult to do.

  FIG. 10B schematically shows a netlist n of cells in the layout region r in FIG. The netlist n shown in FIG. 10B indicates that the input cell A and the output cell B are connected.

  FIG. 11 is an explanatory diagram illustrating an arrangement example of the ECO cells C. First, the CAD device 101 defines a wiring delay value from the input terminals I1 to I4 to the output terminal Y. Next, in the CAD apparatus 101, the user of the CAD apparatus 101 who is the designer of the circuit to be designed has four repeater cells driven four times, four ECO cells C driven one time, and one ECO-DOT cell D. The Verilog netlist edited so as to be formed is accepted. Subsequently, the CAD device 101 searches the layout region r for a position where the ECO cell C corresponding to the repeater cell driven by 4 times is arranged. Then, the CAD device 101 performs control so that the wiring length from the input cell A to the plurality of ECO cells at the next stage is the same. Here, a technique of wiring from a certain cell so that the wiring length is equal to a plurality of cells is a technique of clock tree wiring.

  The layout region r shown in FIG. 11A searches the layout region r shown in FIG. 10 for a position where the ECO cell C corresponding to the repeater cell driven four times is arranged, and the input cell A and the searched ECO bulk cell This shows a state in which the wiring length is the same. Here, it is assumed that cells C1 to C4 to which dark hatches in the layout region r in FIG. 11A are given are candidates for arranging the ECO cells.

  A search example of a position where an ECO cell is arranged will be shown. First, the CAD apparatus 101 searches for an ECO bulk cell that is closest to an intermediate point between the arrangement position of the input cell A and the arrangement position of the output cell B. In the example of the layout region r shown in FIG. 11A, the CAD device 101 detects the ECO bulk cell C3 as the ECO bulk cell that is closest to the intermediate position between the input cell A and the output cell B. Subsequently, the CAD apparatus 101 sequentially detects ECO bulk cells C2, C4, and C1 as ECO bulk cells located near the ECO bulk cell C3. Hereinafter, the ECO cells are treated as ECO cells C1 to C4, assuming that the ECO cells are arranged at the positions of the ECO bulk cells C1 to C4.

  In addition, an example of a method for making the wiring lengths of the input cell A and the searched ECO cell C the same is shown. First, the CAD device 101 specifies a net having the longest wiring length when the nets A_C1, A_C2, A_C3, and A_C4 are connected in the shortest. Then, the CAD device 101 sets the nets other than the net with the longest wiring length to be detoured instead of the shortest so as to be the same as the wiring length of the net with the longest wiring length.

  FIG. 11B schematically shows a netlist n having the input cell A and the ECO cells C1 to C4 in the layout region r in FIG. The netlist n shown in FIG. 11B indicates that the input cell A and the ECO cells C1 to C4 are connected to each other.

  FIG. 12 is an explanatory diagram illustrating an arrangement example of the ECO-DOT cells D. In FIG. 12, after the CAD device 101 searches for the ECO cells C1 to C4, the ECO-DOTD cell is arranged in the layout region r, and the wiring length from the plurality of ECO bulk cells to the ECO-DOT cell D is increased. The process until control is performed to be the same will be described.

  The layout area r shown in FIG. 12A searches the layout area r shown in FIG. 11A for the position where the ECO-DOT cell D is arranged, and the ECO cells C1 to C4 to the ECO-DOT cell D. The state in which the wiring length is the same is shown. Here, it is shown that a cell D to which a medium dark hatching in the layout region r in FIG. 12A is a cell at the position of the searched ECO-DOT cell.

  The example of a search of the position which arrange | positions the ECO-DOT cell D is shown. First, the CAD apparatus 101 calculates the position of an intermediate point between the arrangement position of the ECO cells C1 to C4 and the arrangement position of the output cell B. The CAD apparatus 101 may calculate the position of an intermediate point between any one of the ECO cells C1 to C4 and the output cell B. The CAD apparatus 101 may calculate the position of the intermediate point between the calculated intermediate point and the arrangement position of the output cell B after calculating the intermediate point of the ECO cells C1 to C4. Then, the CAD apparatus 101 determines the position of the ECO bulk cell that is closest to the calculated intermediate position as the position where the ECO-DOT cell D is disposed.

  In addition, an example of a method for making the wiring lengths of the ECO cells C1 to C4 and the ECO-DOT cell D the same is shown. First, the CAD device 101 identifies a net having the longest wiring length when the nets C1_D, C2_D, net C3_D, and net C4_D are connected in the shortest. Then, the CAD apparatus 101 sets the wiring length of the net other than the net having the longest wiring length so as to make a detour instead of the shortest so as to be the same as the wiring length of the net having the longest wiring length.

  FIG. 12B schematically shows a netlist n having an input cell A, ECO cells C1 to C4, and an ECO-DOT cell D in the layout region r in FIG. is there. The netlist n shown in FIG. 12B shows that the input cell A and the ECO cells C1 to C4 are connected to each other, and the ECO cells C1 to C4 and the ECO-DOT cell D are connected to each other. Show.

  As shown in FIG. 12A and FIG. 12B, by arranging the ECO-DOT cells D, the nets between the ECO cells C1 to C4-ECO-DOT cells D are defined separately. Therefore, the wiring length of each net can be specified.

  FIG. 13 is an explanatory diagram showing a connection example from the ECO-DOT cell D to the output cell B. In FIG. 13, after the ECO-DOT cell D is arranged, the CAD device 101 will be described until the ECO-DOT cell D and the output cell B are connected.

  A layout region r shown in FIG. 13A shows a state where the ECO-DOT cell D and the output cell B are connected from the layout region r shown in FIG. FIG. 13B schematically shows a netlist n having an input cell A, ECO cells C1 to C4, an ECO-DOT cell D, and an output cell B in the layout region r in FIG. It is shown.

  10 to 13, the CAD apparatus 101 determines whether the position where the ECO cell C is disposed and the position where the ECO-DOT cell D is disposed are appropriate. Specific criteria for determining whether or not it is appropriate will be described later with reference to FIG. If the position where the ECO cell C is arranged and the position where the ECO-DOT cell D is arranged are appropriate, the CAD apparatus 101 performs timing analysis. On the other hand, if the position where the ECO cell C is disposed and the position where the ECO-DOT cell D is disposed are not appropriate, the CAD apparatus 101 includes a position where the ECO cell is disposed and a position where the ECO-DOT cell D is disposed. Search again.

  10 to 13, after searching for the position where the ECO cell C is arranged, the position where the ECO-DOT cell D is arranged is searched. However, the position where the ECO-DOT cell D is arranged is searched first. Also good. As a method for searching for the position where the ECO-DOT cell D is first arranged, for example, the CAD apparatus 101 sets the position of the ECO bulk cell closest to the output cell B as the position where the ECO-DOT cell D is arranged. Next, the CAD apparatus 101 sets the position of the ECO bulk cell closest to the midpoint between the position of the input cell A and the position where the ECO-DOT cell D is disposed as the position where the ECO cell C is disposed. Subsequently, the CAD apparatus 101 searches for the position of the ECO bulk cell that is closest from the intermediate position between the position where the ECO-DOT cell is placed and the input cell A, and sequentially from the ECO bulk cell that is closest to the position of the ECO bulk cell from the intermediate position. , ECO cell C is located.

  The layout region r shown in FIGS. 10 to 13 includes a rectangle having apexes of the position of the input cell A and the position of the output cell B. The wiring between the input cell A and the ECO cells C1 to C4, the wiring between the ECO cells C1 to C4 and the ECO-DOT cell D, and the wiring between the ECO-DOT cell D and the output cell B are within the layout region r. Thus, it may exist outside the aforementioned rectangle. In addition, the ECO bulk cell in which the ECO cell and the ECO-DOT cell are arranged may be present in the layout region r and outside the above-described rectangle. However, when searching for the position of the ECO cell C or the ECO-DOT cell D, the ECO bulk cell in the above-mentioned rectangle may be preferentially searched in order to shorten the wiring length.

  Next, a flowchart of a layout processing procedure executed by the CAD apparatus 101 will be described with reference to FIGS. 14 and 15.

  FIG. 14 is a flowchart illustrating an example of a layout processing procedure. The layout process is a process for outputting a net list and layout data from the design data of the design target circuit described in RTL.

  The CAD apparatus 101 performs logic synthesis using the design data of the circuit to be designed, the constraint conditions that the design object circuit should comply with, and the library (step S1401). Through the processing in step S1401, the CAD apparatus 101 obtains a net list. Next, the CAD device 101 executes P & R ECO processing (step S1402). The P & R ECO process will be described later with reference to FIG.

  Then, the CAD device 101 performs timing analysis on the net list that has been subjected to the P & R ECO process (step S1403). Through the processing in step S1403, the CAD apparatus 101 obtains a timing analysis result and layout data.

  Next, the CAD device 101 determines whether or not insertion of an ECO cell has been requested (step S1404). Specifically, if the timing analysis result is a Max_cap error or a Max_tran error, the CAD apparatus 101 determines that insertion of an ECO cell has been requested.

  When insertion of an ECO cell is requested (step S1404: Yes), the CAD device 101 receives a netlist rewritten to insert an ECO cell by a user of the CAD device 101 (step S1405). Then, the CAD apparatus 101 proceeds to the process of step S1402.

  On the other hand, if the insertion of the ECO cell is not requested (step S1404: No), the CAD device 101 ends the layout process. By executing the layout process, the CAD apparatus 101 can perform automatic layout.

  FIG. 15 is a flowchart illustrating an example of the P & R ECO processing procedure. The P & R ECO process is a process of performing placement and routing and performing ECO.

  Based on the layout data, the CAD apparatus 101 searches for an ECO bulk cell at an intermediate position between the input cell A and the output cell B as a candidate for arranging a plurality of ECO cells C (step S1501). Next, based on the layout data, the CAD apparatus 101 searches for an ECO bulk cell from an intermediate position between the plurality of ECO cells C and the output cell B as a candidate for an ECO-DOT cell arrangement position (step S1502). .

  Then, the CAD apparatus 101 determines whether or not the position where the plurality of ECO cells C are arranged and the position where the ECO-DOT cell D is arranged are appropriate (step S1503). Specifically, the CAD apparatus 101 has a position where a plurality of ECO cells C and a position where an ECO-DOT cell D are arranged when both the following expressions (1) and (2) are satisfied. Judge that it is appropriate. In the equations (1) and (2), Max_cap represents the maximum load capacity.

Max_cap of input cell A ≧ (wiring load between input cell A and a plurality of ECO cells C + input capacities of a plurality of ECO cells C) (1)
Sum of Max_cap of a plurality of ECO cells C ≧ (maximum value of wiring load between each ECO cell and ECO-DOT cell D of the plurality of ECO cells C) × number of ECO cells C + ECO-DOT cell D Wiring fixed capacity + wiring load between ECO-DOT cell D and output cell B + input capacity of output cell B (2)

  When the position where the plurality of ECO cells C are arranged and the position where the ECO-DOT cell D is arranged are appropriate (step S1503: Yes), the CAD apparatus 101 is the searched position, and the ECO cell C and the ECO-DOT. The position with the cell D is determined (step S1504). Next, the CAD device 101 sets the net of the input cell A and the plurality of ECO cells C to the equal length wiring (step S1505). Further, the CAD device 101 sets the nets of the plurality of ECO cells C and ECO-DOT cells D to the equal length wiring (step S1506). After the process of step S1506 ends, the CAD device 101 ends the P & R ECO process.

  On the other hand, when the position where the plurality of ECO cells C are arranged and the position where the ECO-DOT cell D is arranged are not appropriate (step S1503: No), the CAD apparatus 101 proceeds to the process of step S1501. When the process of step S1501 is performed again, the CAD apparatus 101 searches for a combination except for a combination of a position where a plurality of ECO cells C determined to be inappropriate and a position where an ECO-DOT cell D is arranged. By executing the P & R ECO process, the CAD apparatus 101 can change the placement positions of the ECO cell and the ECO-DOT cell that can obtain a drive capability multiple of one ECO cell even when the ECO cells are placed in parallel. Can be acquired.

  Here, the P & R ECO process shown in FIG. 15 is executed a plurality of times when Step S1404 becomes Yes. Specifically, for example, the CAD apparatus 101 arranges four ECO cells C in the first P & R ECO process. When step S1404 becomes Yes, the CAD apparatus 101 outputs information indicating how many ECO cells C are required by the timing analysis of step S1403. The user of the CAD apparatus 101 edits the net list so as to add the number of ECO cells C according to the output information.

  For example, it is assumed that the CAD apparatus 101 outputs information indicating that two more ECO cells C are required by timing analysis. In this case, the CAD apparatus 101 accepts a netlist in which two ECO cells C are added by the user of the CAD apparatus 101 by the process of step S1405. Then, the CAD apparatus 101 performs the P & R ECO process shown in FIG. 15 again. At this time, in the process of step S1501, for example, the CAD device 101 searches the positions of the two added ECO cells C while keeping the positions of the four ECO cells C and the ECO-DOT cells D as they are.

  As described above, according to the CAD apparatus 101, when the plurality of ECO cells C are arranged to supplement the driving capability, the ECO-DOT cells D in which the plurality of input terminals and the output terminals are wired at the same length are arranged, The input terminal and each buffer are wired in equal length. As a result, it is possible to obtain a driving capability multiple times the driving capability of one ECO cell C without securing a region in which the plurality of ECO cells C are continuously arranged. The CAD device 101 can perform automatic wiring with an existing layout tool that can obtain the same driving ability as when a plurality of ECO cells C are continuously arranged. Therefore, the user of the CAD apparatus 101 does not need to modify the layout so that the ECO cells C are continuously arranged, and the design work can be made efficient.

  Further, according to the CAD apparatus 101, a plurality of ECO cells C and ECO-DOT cells D may be arranged in the layout area based on the arrangement positions of the input cell A and the output cell B. As a result, the CAD apparatus 101 can improve the efficiency of design work, and can shorten the wiring length as compared with the case where the ECO cell C and the ECO-DOT cell D are randomly arranged.

  Also, according to the CAD apparatus 101, a plurality of ECO cells C are arranged in the layout area based on the arrangement positions of the input cells A and output cells B, and the arrangement positions of the arranged plurality of ECO cells C and output cells B are arranged. The ECO-DOT cell D may be arranged based on the above. As a result, the CAD apparatus 101 can improve the efficiency of the design work and suppress the increase in the wiring length of the net A_C, the net C_D, and the net D_B.

  For example, it is assumed that a plurality of ECO cells C are disposed after the ECO-DOT cell D is disposed first. In this case, in order to prevent the wiring length of the net A_C and the wiring length of the net C_D from becoming long, the ECO in a rectangle whose apex is the arrangement position of the input cell A and the arrangement position of the ECO-DOT cell D is used. Preferably, a plurality of ECO cells are arranged from the bulk cell.

  However, if the number of ECO bulk cells included in the rectangle is smaller than the number of ECO cells to be arranged, the ECO cells are arranged in the ECO bulk cells existing outside the rectangle. If the ECO cell is arranged at the position of the ECO bulk cell existing outside the aforementioned rectangle, the wiring length with the net A_C and the wiring length with the net C_D become long.

  In contrast, it is assumed that the ECO-DOT cell D is disposed after the ECO cell C is disposed. In this case, in order to suppress an increase in the wiring length of the net C_D and the wiring length of the net D_B, a rectangular interior having any one of the ECO cell C and the output cell B as a vertex is used. It is preferable to arrange the ECO-DOT cell D from the ECO bulk cell. Since only one ECO-DOT cell D is arranged, if the number of ECO bulk cells contained in the rectangle is 1 or more, the wiring length of the net C_D and the wiring length of the net D_B are increased. Can be suppressed.

  Further, according to the CAD apparatus 101, a plurality of ECO cells C may be arranged based on an intermediate point between the arrangement position of the input cell A and the arrangement position of the output cell B. As a result, the CAD apparatus 101 has nets A_C, C_D, and D_B as compared with the case where a plurality of ECO cells C are randomly arranged from the ECO bulk cells in the rectangle whose apexes are the arrangement positions of the input cells A and the output cells B. It is possible to shorten each wiring length.

  Further, according to the CAD apparatus 101, the ECO-DOT cell D is arranged based on an intermediate point between the arrangement position of any one of the plurality of arranged ECO cells C and the arrangement position of the output cell B. May be. As a result, the CAD apparatus 101 compares each of the nets C_D and D_B with respect to each of the nets C_D and D_B in comparison with the random arrangement of the ECO-DOT cells D from the ECO bulk cells in the rectangle whose apexes are the arrangement positions of the input cells A and output cells B It is possible to shorten the wiring length.

  Further, the ECO-DOT cell D according to the present embodiment may output a logical sum of values input to a plurality of input terminals. In FIG. 4, it has been explained that the wiring length from the plurality of input terminals to the output terminal in the ECO-DOT cell D may be shifted within a range where no through current or the like is generated. Therefore, the timing of the change of the value of the input terminal when reaching the output terminal may vary within a range where no through current or the like is generated. Then, by outputting the logical sum of the values input to the plurality of input terminals, the value of the output terminal changes due to the change of the value of any one of the plurality of input terminals. Therefore, the signal transmission speed can be improved by adopting the logical sum as the logical circuit of the ECO-DOT cell D rather than the logical product.

  The layout method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. A program for executing this layout method is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM (Compact Disc-Read Only Memory), a DVD (Digital Versatile Disk), and the like. It is executed by being read. A program for executing this layout method may be distributed through a network such as the Internet.

  In addition, the ECO-DOT cell D described in the present embodiment is a special purpose IC such as a standard cell or a structured ASIC (Application Specific Integrated Circuit) (hereinafter simply referred to as “ASIC”) or a PLD (such as an FPGA). It can also be realized by Programmable Logic Device).

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary Note 1) A cell having a plurality of input terminals and an output terminal connected from each of the plurality of input terminals by a wire having the same length, and a plurality of buffers are used as layout data of the circuit to be designed. Based on the layout of the circuit to be designed, each output terminal of the plurality of buffers arranged and the plurality of input terminals of the cell are respectively connected by wires of the same length,
A CAD apparatus comprising a control unit.

(Appendix 2) The control unit
In the layout region, based on an arrangement position of an input cell in which an output terminal is connected to an input terminal of the plurality of buffers and an arrangement position of an output cell in which an output terminal of the cell is connected to the input terminal, The CAD device according to appendix 1, wherein the plurality of buffers are arranged.

(Appendix 3) The control unit
In the layout region, the plurality of buffers are arranged on the basis of an arrangement position of an input cell in which an output terminal is connected to an input terminal of the plurality of buffers and an arrangement position of an output cell in which the output terminal of the cell is connected to an input terminal. Place the buffer,
The CAD device according to appendix 1, wherein the cells are arranged in the layout area based on the arrangement positions of the plurality of buffers arranged and the arrangement positions of the output cells.

(Appendix 4) The control unit
The CAD device according to appendix 2 or 3, wherein the plurality of buffers are arranged in the layout area based on an intermediate point between the arrangement position of the input cell and the arrangement position of the output cell.

(Supplementary Note 5) The control unit
The cell is arranged in the layout area based on an intermediate point between the arrangement position of any one of the plurality of buffers arranged and the arrangement position of the output cell. 5. The CAD device according to any one of 4.

(Supplementary note 6) The CAD device according to any one of Supplementary notes 2 to 5, wherein an output terminal of the cell outputs a logical sum of values inputted to the plurality of input terminals.

(Appendix 7) The control unit
Based on the layout data, the output terminal of the cell and the input terminal of the output cell are connected, and the output terminal of the input cell and the input terminals of the plurality of buffers are connected by wires of the same length. The CAD device according to any one of appendices 2 to 6, characterized in that:

(Appendix 8) a plurality of input terminals;
An output terminal connected by a wire of the same length from each of the plurality of input terminals,
A cell characterized in that each of the plurality of input terminals and each output terminal of the plurality of buffers are connected to each other by a wiring having the same length.

(Supplementary note 9)
Based on the layout data of the circuit to be designed, a plurality of input terminals, a cell having a plurality of input terminals, and an output terminal connected by a wiring having the same length from each of the plurality of input terminals, and a plurality of buffers, Arranged in the layout area of the circuit to be designed, each of the arranged plurality of buffers and each of the plurality of input terminals of the cell are respectively connected by wires of the same length,
A layout method characterized by executing processing.

(Appendix 10)
Based on the layout data of the circuit to be designed, a plurality of input terminals, a cell having a plurality of input terminals, and an output terminal connected by a wiring having the same length from each of the plurality of input terminals, and a plurality of buffers, Arranged in the layout area of the circuit to be designed, each of the arranged plurality of buffers and each of the plurality of input terminals of the cell are respectively connected by wires of the same length,
A layout program characterized by causing a process to be executed.

A input cell B output cell C1 to C4 ECO cell D ECO-DOT cell I1 to I4 input terminal Y output terminal 101 CAD device 700 control unit 701 arrangement unit 702 connection unit

Claims (9)

Based on the layout data of the circuit to be designed, a plurality of input terminals, a cell having a plurality of input terminals, and an output terminal connected by a wiring having the same length from each of the plurality of input terminals, and a plurality of buffers, Arranged in the layout area of the circuit to be designed, each of the arranged plurality of buffers and each of the plurality of input terminals of the cell are respectively connected by wires of the same length,
A CAD apparatus comprising a control unit. The controller is
In the layout region, based on an arrangement position of an input cell in which an output terminal is connected to an input terminal of the plurality of buffers and an arrangement position of an output cell in which an output terminal of the cell is connected to the input terminal, The CAD device according to claim 1, wherein the plurality of buffers are arranged. The controller is
In the layout region, based on the arrangement position of the input cell where the output terminal is connected to the input terminal of the plurality of buffers and the arrangement position of the output cell where the output terminal of the cell is connected to the input terminal, Place the buffer,
2. The CAD device according to claim 1, wherein the cells are arranged in the layout area based on the arrangement positions of the plurality of buffers arranged and the arrangement positions of the output cells. The controller is
4. The CAD device according to claim 2, wherein the plurality of buffers are arranged in the layout area based on an intermediate point between the arrangement position of the input cell and the arrangement position of the output cell. The controller is
3. The cell is arranged in the layout area based on an intermediate point between an arrangement position of any one of the plurality of arranged buffers and an arrangement position of the output cell. The CAD apparatus as described in any one of -4.   The CAD device according to claim 2, wherein an output terminal of the cell outputs a logical sum of values input to the plurality of input terminals. The controller is
Based on the layout data, the output terminal of the cell and the input terminal of the output cell are connected, and the output terminal of the input cell and the input terminals of the plurality of buffers are connected by wires of the same length. The CAD apparatus according to any one of claims 2 to 6, wherein Multiple input terminals,
An output terminal connected by a wire of the same length from each of the plurality of input terminals,
A cell characterized in that each of the plurality of input terminals and each output terminal of the plurality of buffers are connected to each other by a wiring having the same length. Computer
Based on the layout data of the circuit to be designed, a plurality of input terminals, a cell having a plurality of input terminals, and an output terminal connected by a wiring having the same length from each of the plurality of input terminals, and a plurality of buffers, Arranged in the layout area of the circuit to be designed, each of the arranged plurality of buffers and each of the plurality of input terminals of the cell are respectively connected by wires of the same length,
A layout method characterized by executing processing.

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