JP2024102712A - Amplification circuit and ultrasonic flow meter - Google Patents

Abstract

An amplifier circuit capable of switching the gain by n times is provided.
[Solution] An amplifier circuit comprising a first amplifier circuit, a second amplifier circuit, and an attenuator circuit connected in series, the amplifier circuit comprising a switching circuit which switches between setting the gain of the first amplifier circuit to n or nx, or -n or ^-nx , switches between setting the gain of the second amplifier circuit to m or m×n2, and switches between setting the gain of the attenuator circuit to 1 or 1/n, where m is a basic gain of the amplifier circuit, n is a gain increment, m is a number other than 0, n is a number greater than 1, and ^x is an integer selected from among 5, 4, 3, and ² .
[Selected figure] Figure 5

Description

This disclosure relates to an amplifier circuit and an ultrasonic flow meter.

Conventionally, there is known a technique for controlling the amplitude of the amplified received signal by adjusting the gain of an amplifier circuit that amplifies the received signal (see, for example, Patent Document 1).

JP 2003-014515 A

However, it was difficult to realize a configuration that could switch the gain of an amplifier circuit that amplifies relatively high-frequency signals in n-fold increments.

This disclosure provides an amplifier circuit capable of switching the gain by n times and an ultrasonic flowmeter equipped with the amplifier circuit.

In a first aspect of the present disclosure,
An amplifier circuit including a first amplifier circuit, a second amplifier circuit, and an attenuator circuit connected in series,
Let m be the base gain of the amplifier circuit, n be the gain increment, m be a number other than 0, n be a number greater than 1, and x be an integer of 5, 4, 3, or 2.
An amplifier circuit and an ultrasonic flowmeter including the amplifier circuit are provided, the amplifier circuit including a switching circuit that switches between setting the gain of the first amplifier circuit to n or ^nx , or between setting the gain to -n ^{or -nx} , switches between setting the gain of the second amplifier circuit to m or m× ⁿ² , and switches between setting the gain of the attenuator circuit to 1 or 1/n.

In a second aspect of the present disclosure,
An amplifier circuit comprising a first amplifier circuit, a second amplifier circuit, and a third amplifier circuit connected in series,
Let the basic gain of the amplifier circuit be α β m, the gain increment be n, α be a non-zero number, β be a non-zero number, m be a non-zero number, n be a number greater than 1, and y be an integer selected from 4, 3, 2, and 1.
An amplifier circuit and an ultrasonic flowmeter including the amplifier circuit are provided, the amplifier circuit including a switching circuit that switches between setting the gain of the first amplifier circuit to α or α· ^ny , that switches between setting the gain of the second amplifier circuit to m or m× ⁿ² , and that switches between setting the gain of the third amplifier circuit to β or β·n.

The present disclosure provides an amplifier circuit capable of switching the gain by n times and an ultrasonic flowmeter equipped with the amplifier circuit.

FIG. 1 is a diagram illustrating an example of a configuration of an ultrasonic flowmeter according to an embodiment. FIG. 2 is a diagram illustrating Snell's law for determining the angle of incidence in a fluid. FIG. 2 is a diagram illustrating an example of a configuration of a receiving unit. FIG. 4 is a diagram for explaining a reception timing signal. FIG. 2 is a diagram illustrating a configuration example of an amplifier circuit according to the first embodiment. 11 is a table showing a first gain setting method. 11 is a table showing a specific example of a first gain setting method. 13 is a table showing a second gain setting method. 13 is a table showing a specific example of a second gain setting method. FIG. 13 is a diagram illustrating a configuration example of an amplifier circuit according to a second embodiment. 13 is a table showing a third gain setting method. 13 is a table showing a specific example of a third gain setting method. FIG. 13 is a diagram illustrating a configuration example of an amplifier circuit according to a third embodiment. 13 is a table showing a fourth gain setting method. 13 is a table showing a specific example of a fourth gain setting method. FIG. 13 is a diagram illustrating a configuration example of an amplifier circuit according to a fourth embodiment. FIG. 2 illustrates an example of the configuration of a transmission unit. FIG. 1 is a diagram illustrating an example of a configuration of a power supply circuit that generates a variable power supply voltage.

The following describes an embodiment of the present disclosure with reference to the drawings.

Figure 1 is a diagram showing an example of the configuration of an ultrasonic flowmeter according to one embodiment. The ultrasonic flowmeter uses ultrasonic waves to measure the flow rate of a fluid (gas or liquid) flowing through a flow path. The ultrasonic flowmeter includes two or more ultrasonic transducers arranged along or within a measurement pipeline. The two or more ultrasonic transducers include a transmitting transducer and a receiving transducer. The transmitting transducer and the receiving transducer are arranged so that the direction connecting the transmitting transducer and the receiving transducer is oblique to or coincident with the direction of the fluid flow. The ultrasonic flowmeter measures the flow rate of the fluid in the measurement pipeline from the propagation time of ultrasonic waves transmitted and received between the transmitting transducer and the receiving transducer.

The ultrasonic flowmeter 300 shown in FIG. 1 includes an ultrasonic probe 10a, an ultrasonic probe 10b, a control unit 35, a transmitting unit 31, a switch 33a, a switch 33b, a receiving unit 32, a time measuring unit 40, and a flow measuring unit 50.

The control unit 35 controls switching between transmitting ultrasonic waves e from the ultrasonic transducer 11a of the ultrasonic probe 10a and transmitting ultrasonic waves e from the ultrasonic transducer 11b of the ultrasonic probe 10b toward the fluid 102 in the pipe 100.

The ultrasonic probe 10a is disposed upstream of the fluid 102 flowing through the pipe 100 so as to face the outer surface of the pipe 100. The ultrasonic probe 10a has an ultrasonic transducer 11a and a resin wedge 12a. The ultrasonic probe 10b is disposed downstream of the fluid 102 flowing through the pipe 100 so as to face the outer surface of the pipe 100. The ultrasonic probe 10b has an ultrasonic transducer 11b and a resin wedge 12b.

The wedge 12a has a surface that is inclined with respect to the outer surface of the pipe 100, and the ultrasonic transducer 11a is attached to that surface. Therefore, the ultrasonic waves generated by the ultrasonic transducer 11a enter the pipe 100 from the wedge 12a at a predetermined inclination angle, then propagate through the fluid 102 and reach the ultrasonic transducer 11b.

The wedge 12b has a surface that is inclined with respect to the outer surface of the pipe 100, and the ultrasonic transducer 11b is attached to that surface. Therefore, the ultrasonic waves generated by the ultrasonic transducer 11b enter the pipe 100 from the wedge 12b at a predetermined inclination angle, then propagate through the fluid 102 and reach the ultrasonic transducer 11a.

The ultrasonic transducer 11a is selectively connected to the transmitting unit 31 or the receiving unit 32 by the switching operation of the switch 33a. The ultrasonic transducer 11b is selectively connected to the receiving unit 32 or the transmitting unit 31 by the switching operation of the switch 33b.

The control unit 35 is a circuit that generates selection signals a and b that select one of the ultrasonic transducers 11a and 11b from which ultrasonic waves should be transmitted (i.e., one of the transducers to be excited), and a transmission timing signal c that indicates the timing of ultrasonic transmission.

When the ultrasonic transducer 11a is selected as the transducer to transmit the ultrasonic wave e, the switch 33a selects the ultrasonic transducer 11a as the transducer to transmit the ultrasonic wave e in accordance with the selection signal a from the control unit 35. On the other hand, the switch 33b selects the ultrasonic transducer 11b as the transducer to receive the ultrasonic wave e in accordance with the selection signal b from the control unit 35.

The transmitting unit 31 is a circuit that transmits an electric signal d (for example, one or more pulse signals that excite the ultrasonic transducer 11a) to the ultrasonic transducer 11a via the switch 33a in accordance with a transmission timing signal c from the control unit 35, and causes the ultrasonic transducer 11a to generate an ultrasonic wave e. The generated ultrasonic wave e passes through the wedge 12a and the pipe 100 and enters the fluid 102 in the pipe 100. The ultrasonic wave e that enters the fluid 102 in the pipe 100 propagates to the ultrasonic transducer 11b of the ultrasonic probe 10b installed on the outer surface of the opposite side of the pipe 100, and is converted into an electric signal by the ultrasonic transducer 11b. The electric signal output from the ultrasonic transducer 11b is received as a reception signal f by the receiving unit 32 via the switch 33b.

The time measurement unit 40 measures the time from when the ultrasonic wave e is transmitted from the ultrasonic transducer 11a to when it is received by the ultrasonic transducer 11b as the propagation time Tab. The time measurement unit 40 is a circuit that measures the propagation time Tab based on, for example, a transmission timing signal c indicating the timing at which the transmission of the ultrasonic wave e from the ultrasonic transducer 11a starts, and a reception timing signal g indicating the timing at which the ultrasonic wave e is received by the ultrasonic transducer 11b.

Next, the ultrasonic flowmeter 300 switches between switches 33a and 33b in response to a signal from the control unit 35, reversing the transmission/reception relationship between the ultrasonic probes 10a and 10b.

When ultrasonic transducer 11b is selected as the transducer to transmit ultrasonic waves e, switch 33a selects ultrasonic transducer 11a as the transducer to receive ultrasonic waves e in accordance with selection signal a from control unit 35. On the other hand, switch 33b selects ultrasonic transducer 11b as the transducer to transmit ultrasonic waves e in accordance with selection signal b from control unit 35.

The transmitting unit 31 is a circuit that transmits an electric signal d (for example, one or more pulse signals that excite the ultrasonic transducer 11b) to the ultrasonic transducer 11b via the switch 33b in accordance with a transmission timing signal c from the control unit 35, and causes the ultrasonic transducer 11b to generate an ultrasonic wave e. The generated ultrasonic wave e passes through the wedge 12b and the pipe 100, and enters the fluid 102 in the pipe 100. The ultrasonic wave e that enters the fluid 102 in the pipe 100 propagates to the ultrasonic transducer 11a of the ultrasonic probe 10a installed on the outer surface of the opposite side of the pipe 100, and is converted into an electric signal by the ultrasonic transducer 11a. The electric signal output from the ultrasonic transducer 11a is received as a reception signal f by the receiving unit 32 via the switch 33a.

The time measurement unit 40 measures the time from when the ultrasonic wave e is transmitted from the ultrasonic transducer 11b to when it is received by the ultrasonic transducer 11a as the propagation time Tba. The time measurement unit 40 is a circuit that measures the propagation time Tba based on, for example, a transmission timing signal c indicating the timing at which the transmission of the ultrasonic wave e from the ultrasonic transducer 11b starts, and a reception timing signal g indicating the timing at which the ultrasonic wave e is received by the ultrasonic transducer 11a.

The order in which the propagation times Tab and Tba are measured may be reversed.

The flow rate measurement unit 50 calculates the flow rate Q of the fluid 102 using the measurement times (propagation times Tab and Tba) obtained by the time measurement unit 40. Next, the calculation of the flow rate Q will be described.

Regarding the propagation times Tab and Tba,
Tab=Lf/(Cf+Vsinθ _fs )...(1)
Tba=Lf/(Cf-Vsinθ _fs )...(2)
Here, Cf is the sound speed in the fluid 102 in the pipe 100, V is the flow velocity of the fluid 102, _θfs is the angle of incidence in the fluid (the angle of refraction from the pipe 100 to the fluid 102 or the angle of incidence from the fluid 102 to the pipe 100), and Lf is the length of the propagation path 110 of the ultrasonic wave e in the pipe 100.

From equations (1) and (2), solving for V gives
V=Lf/(2sinθ _fs )×((1/Tab)-(1/Tba))...(3)
It becomes.

The flow rate Q is
Q=V×A...(4)
Here, A is the cross-sectional area of the pipe 100. The cross-sectional area A is calculated by using the inner radius r of the pipe 100 as follows:
A=π×r ² ...(5)
This is expressed as:

FIG. 2 is a diagram for explaining Snell's law for determining the angle of incidence θ _fs in a fluid. According to Snell's law,
Cw/sinθ _w = Cp/sinθ _p = Cf/sinθ _fs ...(6)
The following relational expression is established. Here, Cw is the sound speed in the wedge 12a, and _θw is the angle of incidence in the wedge (angle of incidence from the wedge 12a to the pipe 100 or angle of refraction from the pipe 100 to the wedge 12a). Cp is the sound speed in the pipe 100, and _θp is the angle of incidence in the pipe (angle of refraction from the wedge 12a to the pipe 100, angle of incidence from the pipe 100 to the fluid 102, or angle of incidence from the pipe 100 to the wedge 12a). Cf is the sound speed in the fluid 102, and _θfs is the angle of incidence in the fluid (angle of refraction from the pipe 100 to the fluid 102 or angle of incidence from the fluid 102 to the pipe 100).

Since Cw, sin _θw , and Cf are known values, the angle of incidence θ _fs in the fluid can be obtained from equation (6). Therefore, the flow rate measurement unit 50 can calculate the flow rate Q based on equations (1) to (5).

The flow rate measurement unit 50 is, for example, an arithmetic circuit including a processor such as a CPU (Central Processing Unit) and a memory. The arithmetic circuit may include at least one of the control unit 35 and the time measurement unit 40. Each function of the flow rate measurement unit 50, the control unit 35, and the time measurement unit 40 (the processing performed by each unit) is realized, for example, by the processor operating according to a program stored in the memory. Each function may be realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). The control unit 35 or the time measurement unit 40 may be realized by a logic circuit.

Figure 3 is a diagram showing an example of the configuration of the receiving unit. The receiving unit 32 has an amplifier circuit 36, a reception timing detection circuit 38, and a peak hold circuit 37. The amplifier circuit 36 amplifies the reception signal f input via the switch 33a or switch 33b, and outputs a reception wave i which is the amplified reception signal f. The reception timing detection circuit 38 generates a reception timing signal g which indicates the timing at which the ultrasonic transducer 11a or the ultrasonic transducer 11b receives the ultrasonic wave e based on the input reception wave i.

4 is a diagram for explaining the reception timing signal g. The reception timing detection circuit 38 detects the point in time at which the reception wave i crosses the reference level _VCOM after crossing the threshold voltage _VTHLD (FIG. 4 illustrates the zero-cross point in time q8x or the zero-cross point in time q10x).

The reception timing detection circuit 38 detects a specific vibration half wave whose amplitude crosses the threshold voltage _VTHLD among a plurality of vibration half waves included in the reception wave i. For example, the reception timing detection circuit 38 detects the eighth vibration half wave whose amplitude crosses the threshold voltage _VTHLD at the trigger time c8x, or the tenth vibration half wave whose amplitude crosses the threshold voltage _VTHLD at the trigger time c10x, as the specific vibration half wave. The reception timing detection circuit 38 detects the time when the rear end of the specific vibration half wave crosses the reference level _VCOM (FIG. 4 illustrates the zero cross time q8x or the zero cross time q10x) and outputs the stop pulse STOP generated at that time as the reception timing signal g.

The time measurement unit 40 (Figure 3) measures the time from the transmission timing signal c, which indicates the start timing of transmission of ultrasound e from the ultrasound transducer 11a, to the reception timing signal g (stop pulse STOP), which indicates the reception timing of ultrasound e at the ultrasound transducer 11b. The time measurement unit 40 outputs the measurement value of this time as the propagation time Tab. Similarly, the time measurement unit 40 measures the time from the transmission timing signal c, which indicates the start timing of transmission of ultrasound e from the ultrasound transducer 11b, to the reception timing signal g (stop pulse STOP), which indicates the reception timing of ultrasound e at the ultrasound transducer 11a. The time measurement unit 40 outputs the measurement value of this time as the propagation time Tba.

However, if the amplitude or threshold voltage _VTHLD of the received wave i shown in FIG. 4 is out of the expected value, the reception timing signal g (stop pulse STOP) may be generated based on the vibration half wave one wave before or one wave after. In this case, a measurement error of the propagation time Tab or the propagation time Tba may occur. The ultrasonic flowmeter of this embodiment includes a control unit 35 (FIG. 3) that controls the amplitude of the received wave i to a constant value or the threshold voltage _VTHLD to a value that allows a specific vibration half wave to be detected, depending on the peak value of the received wave i measured by the peak hold circuit 37 (FIG. 3). This reduces the measurement error of the propagation time Tab or the propagation time Tba.

In FIG. 3, the received signal f is input to the amplifier circuit 36 via the switch 33a or the switch 33b. The received wave i, which is the received signal f amplified by the amplifier circuit 36, is input to the time measurement unit 40, which measures the propagation time Tab and the propagation time Tba as described above. Meanwhile, the received wave i is also input to the peak hold circuit 37. The peak hold circuit 37 outputs a peak hold value h corresponding to the peak value (minimum or maximum value of the amplitude) of the received wave i to the control unit 35. The peak hold value h is an analog voltage, but may be treated as a digital value converted by an AD converter (not shown).

The control unit 35 may output a gain adjustment signal k for adjusting the gain of the amplifier circuit 36 according to the peak hold value h. The gain of the amplifier circuit 36 represents the ratio of the voltage of the received wave i output to the voltage of the input received signal f. For example, the control unit 35 compares the peak hold value h with a predetermined target peak value. When the control unit 35 detects that the peak hold value h is lower than the target peak value, it outputs a gain adjustment signal k that increases the gain of the amplifier circuit 36. When the control unit 35 detects that the peak hold value h is higher than the target peak value, it outputs a gain adjustment signal k that decreases the gain of the amplifier circuit 36. The control unit 35 controls the amplitude of the received wave i to a constant value by performing feedback control that outputs the gain adjustment signal k according to the peak hold value h output from the peak hold circuit 37.

The control unit 35 may output a threshold voltage adjustment signal l for adjusting the threshold voltage _VTHLD in accordance with the peak hold value h output from the peak hold circuit 37. For example, the control unit 35 outputs a threshold voltage adjustment signal l for adjusting the threshold voltage _VTHLD to a value at which a specific vibration half wave can be detected in accordance with the difference between a predetermined reference voltage and the peak hold value h.

Figure 5 is a diagram showing an example of the configuration of an amplifier circuit of the first embodiment. Amplifier circuit 36A is an example of the amplifier circuit 36 described above. Amplifier circuit 36A amplifies the received signal f and outputs a received wave i, which is the amplified received signal f. The received wave i corresponds to the input wave to the peak hold circuit 37 and the reception timing detection circuit 38 described above. Amplifier circuit 36A includes a first amplifier circuit 60, a second amplifier circuit 80, and an attenuator circuit 70.

In FIG. 5, the signal output terminal of the first amplifier circuit 60 is connected in series to the signal input terminal of the attenuator circuit 70, and the signal output terminal of the attenuator circuit 70 is connected in series to the signal input terminal of the second amplifier circuit 80. The received wave i is output from the signal output terminal of the second amplifier circuit 80.

The first amplifier circuit 60 amplifies the input reception signal f with a gain G1 and outputs a first intermediate signal M1, which is the amplified reception signal f. The gain G1 represents the ratio (amplification factor) of the voltage of the output first intermediate signal M1 to the voltage of the input reception signal f. The gain G1 is a value of 1 or more. The first amplifier circuit 60 has a first amplifier 61, resistors 62, 63, 64, and a first analog switch 65.

The first amplifier 61 receives the received signal f. The first amplifier 61 is an operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates on a power supply voltage VB between a power supply 91 and a ground 92. The received signal f is input to the non-inverting input terminal of the first amplifier 61. Between the output terminal of the first amplifier 61 and an intermediate potential 93, resistors 62 and 64 are connected in series. A connection point 66 between the resistors 62 and 64 is electrically connected to the inverting input terminal of the first amplifier 61. Between the connection point 66 and the intermediate potential 93, resistor 63 and a first analog switch 65 are connected in series. The first intermediate signal M1 is output from the output terminal of the first amplifier 61.

The intermediate potential 93 is, for example, the above-mentioned reference level _VCOM .

The first analog switch 65 switches between electrically connecting the resistor 63 to the intermediate potential 93 and leaving the resistor 63 open without connecting it to the intermediate potential 93 according to the logical level (high level or low level) of the first switching signal k1. The first switching signal k1 is one of the gain adjustment signals k supplied from the control unit 35. In this embodiment, the first analog switch 65 is a single-pole double-throw type, but may be configured using a single-pole single-throw type switch.

The first amplifier circuit 60 has a non-inverting amplifier circuit formed by a combination of a first amplifier 61 and resistors 62, 63, and 64. The amplification factor (gain G1) of the first amplifier circuit 60 is as follows:

When resistor 63 is open, the gain G1 is:
G1a=1+R64/R62...(7)
R64 and R62 represent the resistance values of the resistors 64 and 62, respectively.

When the resistor 63 is connected to the intermediate potential 93, the gain G1 is
G1b=1+R64/(R62・R63/(R62+R63))...(8)
R63 represents the resistance value of the resistor 63.

In other words, the first amplifier circuit 60 can switch the gain G1 between two amplification factors, G1a and G1b, according to the first switching signal k1.

The first amplifier circuit 60 is constructed using versatile electronic components, such as an operational amplifier, resistors, and a single-pole single-throw or single-pole double-throw analog switch, which reduces the risk of component obsolescence. In addition, since it can be easily constructed using versatile small components, the circuit can be made smaller and less expensive. Furthermore, since the input impedance for the input signal is extremely high, it can accurately amplify even a signal (received signal f) input from a signal input terminal with a relatively high impedance.

The attenuator circuit 70 receives the signal (first intermediate signal M1) amplified by the first amplifier circuit 60. The attenuator circuit 70 attenuates the input first intermediate signal M1 by a gain G3 and outputs a second intermediate signal M2, which is the attenuated first intermediate signal M1. The gain G3 represents the ratio (amplification factor, also called attenuation factor) of the voltage of the output second intermediate signal M2 to the voltage of the input first intermediate signal M1. The gain G3 is a non-negative value equal to or less than 1. The attenuator circuit 70 has resistors 71, 72 and a third analog switch 73.

A resistor 72 is connected in series between the signal input terminal and the signal output terminal of the attenuator circuit 70. The resistor 72 and the signal output terminal of the attenuator circuit 70 are connected at a connection point 74. A resistor 71 and a third analog switch 73 are connected in series between the connection point 74 and the intermediate potential 93. The second intermediate signal M2 is output from the connection point 74.

The third analog switch 73 switches between electrically connecting the resistor 71 to the intermediate potential 93 or leaving the resistor 71 open and not connected to the intermediate potential 93 according to the logical level (high level or low level) of the third switching signal k3. The third switching signal k3 is one of the gain adjustment signals k supplied from the control unit 35. In this embodiment, the third analog switch 73 is a single-pole double-throw type, but may be configured using a single-pole single-throw type switch.

The attenuator circuit 70 has a voltage divider circuit formed by a combination of resistors 71 and 72. The amplification factor (gain G3) of the attenuator circuit 70 is as follows:

When resistor 71 is open, the gain G3 is:
G3a=1...(9)
It becomes.

When the resistor 71 is connected to the intermediate potential 93, the gain G3 is
G3b=R71/(R71+R72)...(10)
R71 and R72 represent the resistance values of the resistors 71 and 72, respectively.

In other words, the attenuator circuit 70 can switch the gain G3 between two amplification factors, G3a and G3b, according to the third switching signal k3.

The attenuator circuit 70 is constructed using highly versatile electronic components, such as resistors and single-pole single-throw or single-pole double-throw analog switches, which reduces the risk of component obsolescence. In addition, because it can be easily constructed using small, highly versatile components, the circuit can be made smaller and less expensive.

The first amplifier circuit 60, the attenuator circuit 70, and the second amplifier circuit 80 described later are not limited to being connected in series in the order shown in FIG. 5, and the order in which these three circuits are connected in series may be reversed. When connected in the order shown in FIG. 5, the output impedance of the first amplifier circuit 60 is low and the input impedance of the second amplifier circuit 80 described later is extremely high, so that accurate amplification is possible even if the input impedance of the attenuator circuit 70 is low and the output impedance is high.

The second amplifier circuit 80 receives the second intermediate signal M2 output from the attenuator circuit 70. The second amplifier circuit 80 amplifies the input second intermediate signal M2 with a gain G2, and outputs a received wave i, which is the amplified second intermediate signal M2. The gain G2 represents the ratio (amplification factor) of the voltage of the output received wave i to the voltage of the input second intermediate signal M2. The gain G2 is a positive value.

The second amplifier circuit 80 has a second amplifier 81, resistors 82, 83, 84, 87, 88, and a second analog switch 85.

The second amplifier 81 receives the second intermediate signal M2. The second amplifier 81 is an operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates with a power supply voltage VB between a power supply 91 and a ground 92. The second intermediate signal M2 is input to the non-inverting input terminal of the second amplifier 81. Between the output terminal of the second amplifier 81 and the intermediate potential 93, resistors 82 and 84 are connected in series. A connection point 86 between the resistors 82 and 84 is electrically connected to the inverting input terminal of the second amplifier 81. Between the connection point 86 and the intermediate potential 93, resistors 83 and a second analog switch 85 are connected in series. Between the output terminal of the second amplifier 81 and the intermediate potential 93, resistors 88 and 87 are connected in series. The received wave i is output from the connection point between the resistors 88 and 87.

The second analog switch 85 switches between electrically connecting the resistor 83 to the intermediate potential 93 and leaving the resistor 83 open without connecting it to the intermediate potential 93 according to the logical level (high level or low level) of the second switching signal k2. The second switching signal k2 is one of the gain adjustment signals k supplied from the control unit 35. In this embodiment, the second analog switch 85 is a single-pole double-throw type, but may be configured using a single-pole single-throw type switch.

The second amplifier circuit 80 has a non-inverting amplifier circuit formed by combining a second amplifier 81 with resistors 82, 83, 84, 87, and 88. The amplification factor (gain G2) of the second amplifier circuit 80 is as follows:

When resistor 83 is open, the gain G2 is:
G2a=(1+R84/R82)・(R87/(R87+R88))
...(11)
R84, R82, R87, and R88 represent the resistance values of resistors 84, 82, 87, and 88, respectively. When G2a>1, it is preferable to short-circuit resistor 88 (R88 corresponds to 0Ω) and to leave resistor 87 unused (not mounted; R87 corresponds to infinity). When G2a=1, it is preferable to short-circuit resistor 88 (R88 corresponds to 0Ω) and to leave resistor 87 unused (not mounted; R87 corresponds to infinity), and also to leave resistor 82 unused (not mounted; R82 corresponds to infinity).

When the resistor 83 is connected to the intermediate potential 93, the gain G2 is
G2b=(1+R84/(R82・R83/(R82+R83)))・(R87/(R87+R88)) ・・・(12)
R83 represents the resistance value of the resistor 83.

In other words, the second amplifier circuit 80 can switch the gain G2 between two amplification factors, G2a and G2b, according to the second switching signal k2.

The second amplifier circuit 80 is constructed using versatile electronic components, such as an operational amplifier, resistors, and a single-pole single-throw or single-pole double-throw analog switch, which reduces the risk of component obsolescence. In addition, because it can be easily constructed using versatile small components, the circuit can be made smaller and less expensive.

In this way, the gain G1 of the first amplifier circuit 60 can be switched by the first switching signal k1, the gain G2 of the second amplifier circuit 80 can be switched by the second switching signal k2, and the gain G3 of the attenuator circuit 70 can be switched by the third switching signal k3. Therefore, the first amplifier circuit 60, the second amplifier circuit 80, and the attenuator circuit 70 can switch their gains independently of each other.

Next, the gain settings of the first amplifier circuit 60, the second amplifier circuit 80, and the attenuator circuit 70 will be explained using Figures 6 and 7.

FIG. 6 is a table showing a first gain setting method. In FIG. 6, the basic gain is m and the gain increment is n. m is a positive number. n is a number greater than 1. The gain G1 of the first amplifier circuit 60 is set by combining the resistance values of the resistors 62, 63, and 64 using equations (7) and (8), where G1a is n and G1b is ⁿ⁵ . The gain G2 of the second amplifier circuit 80 is set by combining the resistance values of the resistors 82, 83, 84, 87, and 88 using equations (11) and (12), where G2a is m and G2b is m· ⁿ² . The gain G3 of the attenuator circuit 70 is set by combining the resistance values of the resistors 71 and 72 using equations (9) and (10), where G3a is 1 and G3b is 1/n.

The total amplification factor of the first amplifier circuit 60, the second amplifier circuit 80, and the attenuator circuit 70 (total gain G of the amplifier circuit 36) is the product of the amplification factors of each circuit (G=G1· ^GG2 ·G3). Therefore, as shown in FIG. 6, the total gain G increases n-fold from the minimum basic gain m to the maximum m·n ⁷ , and can be switched in eight stages. In this way, the amplifier circuit 36A can switch the total gain G from the minimum basic gain m to the maximum m·n ⁷ in n-fold increments according to the first switching signal k1, the second switching signal k2, and the third switching signal k3. In this way, the fact that the total gain G can be switched exponentially with the same gain increment n is convenient in terms of signal amplification.

Figure 7 is a table showing a specific example of the first gain setting method. Figure 7 illustrates the case where the base gain m = 3 and the gain increment n = 2. The total gain increases in increments of 2 from a minimum of 3 times to a maximum of 384 times, and can be switched in 8 steps.

Fig. 8 is a table showing a second gain setting method. Fig. 8 differs from Fig. 6 in that the gain G1b of the first amplifier circuit 60 is set to ⁿ⁴ . As a result, the total gain G can be switched in seven steps from m to m· ⁿ⁶ in increments of n, and two "m· ⁿ³ " values overlap.

Figure 9 is a table showing a specific example of the second gain setting method. Figure 9 illustrates the case where the base gain m = 3 and the gain increment n = 2. The total gain increases in increments of 2 from a minimum of 3 times to a maximum of 192 times, and can be switched in 7 steps.

For example, if the maximum value of the total gain G does not need to be m×n ⁷ and m×n ⁶ is sufficient, the second gain setting method may be used. The maximum value of the gain G1 of the first amplifier circuit 60 is n ⁵ in the first setting method (FIG. 6), whereas it is n ⁴ in the second setting method (FIG. 8). When the gain is reduced, the frequency band and speed of the operational amplifier used can be reduced, making it possible to select more versatile, less expensive parts.

8 shows a case where the gain G1b of the first amplifier circuit 60 is set to ⁿ⁴ . However, even if the gain G1b is set to ⁿ³ or ⁿ² instead of ⁿ⁴ , the same effect as when it is set to ⁿ⁴ can be obtained. When G1b is set to ⁿ³ , the total gain G can be switched in six steps from m to m· ⁿ⁵ in increments of n, and two "m· ⁿ³ "s and two "m· ⁿ² "s overlap (not shown). When G1b is set to ⁿ² , the total gain G can be switched in five steps from m to m· ⁿ⁴ in increments of n, and two "m· ⁿ³ "s, two "m· ⁿ² "s, and two "m·n"s overlap (not shown).

Thus, the amplifier circuit 36A includes a first analog switch 65, a second analog switch 85, and a third analog switch 73 as a switching circuit capable of switching the total gain G by n times. The switching circuits switch between setting the gain of the first amplifier circuit 60 to n or ^nx , between setting the gain of the second amplifier circuit 80 to m or m× ⁿ² , and between setting the gain of the attenuator circuit 70 to 1 or 1/n, where x is one of the integers 5, 4, 3, and 2. The amplifier circuit 36A can adjust the amplitude of the received wave i with high precision even for an ultrasonic reception signal f having a frequency of several hundred kHz to several MHz (for example, 100 kHz to 300 MHz).

Figure 10 is a diagram showing an example of the configuration of an amplifier circuit of the second embodiment. Amplifier circuit 36C is an example of the amplifier circuit 36 described above. In the second embodiment, the description of the configuration, action, and effect similar to those of the first embodiment will be omitted or simplified by invoking the above description. The amplifier circuit 36C of the second embodiment includes a first amplifier circuit 60, a second amplifier circuit 80, and an attenuator circuit 70. In the second embodiment, the attenuator circuit 70 has the same configuration as the attenuator circuit 70 in the first embodiment.

In FIG. 10, the signal output terminal of the first amplifier circuit 60 is connected in series to the signal input terminal of the second amplifier circuit 80, and the signal output terminal of the second amplifier circuit 80 is connected in series to the signal input terminal of the attenuator circuit 70. The received wave i is output from the signal output terminal of the attenuator circuit 70.

The first amplifier circuit 60 amplifies the input reception signal f with a gain G6 and outputs a first intermediate signal M1, which is the amplified reception signal f. The gain G6 represents the ratio (amplification factor) of the voltage of the output first intermediate signal M1 to the voltage of the input reception signal f. The gain G6 is a negative value. The first amplifier circuit 60 has a first amplifier 61, resistors 62, 63, 64, and a first analog switch 65.

The first amplifier 61 receives the received signal f. The first amplifier 61 is an operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates at a power supply voltage VB between a power supply 91 and a ground 92. The non-inverting input terminal of the first amplifier 61 is connected to an intermediate potential 93. The received signal f is input to the inverting input terminal of the first amplifier 61. Resistors 62 and 64 are connected in series between the output terminal of the first amplifier 61 and the input terminal of the received signal f (signal input terminal of the first amplifier circuit 60). A connection point 66 between the resistors 62 and 64 is electrically connected to the inverting input terminal of the first amplifier 61. A resistor 63 and a first analog switch 65 are connected in series between the connection point 66 and the output terminal of the first amplifier 61. The first intermediate signal M1 is output from the output terminal of the first amplifier 61.

The first analog switch 65 switches between electrically connecting the resistor 63 to the output terminal of the first amplifier 61 and disconnecting the resistor 63 from the output terminal of the first amplifier 61 and leaving it open according to the logical level (high level or low level) of the first switching signal k1. The first switching signal k1 is one of the gain adjustment signals k supplied from the control unit 35. In this embodiment, the first analog switch 65 is a single-pole double-throw type, but may be configured using a single-pole single-throw type switch.

The first amplifier circuit 60 has an inverting amplifier circuit formed by a combination of a first amplifier 61 and resistors 62, 63, and 64. The amplification factor (gain G6) of the first amplifier circuit 60 is as follows:

When the resistor 63 is connected to the output terminal of the first amplifier 61, the gain G6 is
G6a=-(R64・R63/(R64+R63))/R62...(17)
R62, R63, and R64 represent the resistance values of the resistors 62, 63, and 64, respectively.

When resistor 63 is open, the gain G6 is:
G6b=-R64/R62...(18)
It becomes.

In other words, the first amplifier circuit 60 can switch the gain G6 between two amplification factors, G6a and G6b, according to the first switching signal k1.

The first amplifier circuit 60 is constructed using versatile electronic components, such as an operational amplifier, resistors, and a single-pole single-throw or single-pole double-throw analog switch, which reduces the risk of component obsolescence. In addition, because it can be easily constructed using versatile small components, the circuit can be made smaller and less expensive.

The second amplifier circuit 80 receives the first intermediate signal M1 output from the first amplifier circuit 60. The second amplifier circuit 80 amplifies the input first intermediate signal M1 with a gain G7 and outputs a second intermediate signal M2, which is the amplified first intermediate signal M1. The gain G7 represents the ratio (amplification factor) of the voltage of the output second intermediate signal M2 to the voltage of the input first intermediate signal M1. The gain G7 is a negative value.

The second amplifier circuit 80 has a second amplifier 81, resistors 82, 83, 84, and a second analog switch 85.

The second amplifier 81 receives the first intermediate signal M1. The second amplifier 81 is an operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates with a power supply voltage VB between a power supply 91 and a ground 92. The non-inverting input terminal of the second amplifier 81 is connected to an intermediate potential 93. The first intermediate signal M1 is input to the inverting input terminal of the second amplifier 81. A resistor 82 and a resistor 84 are connected in series between the output terminal of the second amplifier 81 and the input terminal of the first intermediate signal M1 (the signal input terminal of the second amplifier circuit 80). A connection point 86 between the resistor 82 and the resistor 84 is electrically connected to the inverting input terminal of the second amplifier 81. A resistor 83 and a second analog switch 85 are connected in series between the connection point 86 and the output terminal of the second amplifier 81. The second intermediate signal M2 is output from the output terminal of the second amplifier 81.

The second analog switch 85 switches between electrically connecting the resistor 83 to the output terminal of the second amplifier 81 and disconnecting the resistor 83 from the output terminal of the second amplifier 81 and leaving it open according to the logical level (high level or low level) of the second switching signal k2. The second switching signal k2 is one of the gain adjustment signals k supplied from the control unit 35. In this embodiment, the second analog switch 85 is a single-pole double-throw type, but may be configured using a single-pole single-throw type switch.

The second amplifier circuit 80 has an inverting amplifier circuit formed by a combination of a second amplifier 81 and resistors 82, 83, and 84. The amplification factor (gain G7) of the second amplifier circuit 80 is as follows:

When the resistor 83 is connected to the output terminal of the second amplifier 81, the gain G7 is
G7a=-(R84・R83/(R84+R83))/R82...(19)
R82, R83, and R84 represent the resistance values of the resistors 82, 83, and 84, respectively.

When resistor 83 is open, the gain G7 is:
G7b=-R84/R82...(20)
It becomes.

In other words, the second amplifier circuit 80 can switch the gain G7 between two amplification factors, G7a and G7b, according to the second switching signal k2.

The second amplifier circuit 80 is constructed using versatile electronic components, such as an operational amplifier, resistors, and a single-pole single-throw or single-pole double-throw analog switch, which reduces the risk of component obsolescence. In addition, because it can be easily constructed using versatile small components, the circuit can be made smaller and less expensive.

The attenuator circuit 70 receives the signal (second intermediate signal M2) amplified by the second amplifier circuit 80. The attenuator circuit 70 attenuates the input second intermediate signal M2 with a gain G3, and outputs a received wave i, which is the attenuated second intermediate signal M2. The received wave i is output from the connection point 74.

In this way, the gain G6 of the first amplifier circuit 60 can be switched by the first switching signal k1, the gain G7 of the second amplifier circuit 80 can be switched by the second switching signal k2, and the gain G3 of the attenuator circuit 70 can be switched by the third switching signal k3. Therefore, the first amplifier circuit 60, the second amplifier circuit 80, and the attenuator circuit 70 can switch their gains independently of each other.

The first amplifier circuit 60, the second amplifier circuit 80, and the attenuator circuit 70 are not limited to being connected in series in the order shown in FIG. 10, and the order in which these three circuits are connected in series may be reversed. When connected in the order shown in FIG. 10, the output impedance of the first amplifier circuit 60 is low, so accurate amplification is possible even if the input impedance of the second amplifier circuit 80 is low. Also, the output impedance of the second amplifier circuit 80 is low, so accurate amplification is possible even if the input impedance of the attenuator circuit 70 is low.

Next, the gain settings of the first amplifier circuit 60, the second amplifier circuit 80, and the attenuator circuit 70 will be explained using Figures 11 and 12.

FIG. 11 is a table showing a third gain setting method. In FIG. 11, the basic gain is m, and the gain change is n. m is a negative number. n is a number greater than 1. The gain G6 of the first amplifier circuit 60 is set using equations (17) and (18) by combining the resistance values of the resistors 62, 63, and 64, and G6a is set to -n and G6b is set to ^-n5 . The gain G7 of the second amplifier circuit 80 is set using equations (19) and (20) by combining the resistance values of the resistors 82, 83, and 84, and G7a is set to m and G7b is set to m· ⁿ² . The gain G3 of the attenuator circuit 70 is set using equations (9) and (10) by combining the resistance values of the resistors 71 and 72, and G3a is set to 1 and G3b is set to 1/n.

The total amplification factor (total gain G of the amplifier circuit 36) of the first amplifier circuit 60, the second amplifier circuit 80, and the attenuator circuit 70 is the product of the amplification factors of each circuit (G=G6·GG7·G3). Therefore, as shown in FIG. 11, the total gain G changes n times from the basic gain -m to -m·n, -m·n ² , ..., and can be switched in eight stages up to -m·n ^7. In this way, the amplifier circuit 36C can switch the total gain G from -m to -m·n ⁷ in n times in accordance with the first switching signal k1, the second switching signal k2, and the third switching signal k3. In this way, the fact that the total gain G can be switched exponentially with the same gain change amount n is convenient in terms of signal amplification.

Figure 12 is a table showing a specific example of the third gain setting method. Figure 12 illustrates the case where the base gain m = -3 and the gain change n = 2. The total gain increases in increments of 2 from 3 to 384, and can be switched between 8 levels.

11 shows ^a case where the gain G6b of the first amplifier circuit 60 is set to ⁻ⁿ⁵ . However, similar to the first embodiment, even if the gain G6b is set to ⁻ⁿ⁴ , ⁻ⁿ³ , or ⁻ⁿ² instead of −n5, the same effect as when it is set to ⁻ⁿ⁵ can be obtained.

Thus, the amplifier circuit 36C includes a first analog switch 65, a second analog switch 85, and a third analog switch 73 as a switching circuit capable of switching the total gain G by n times. The switching circuits switch between setting the gain of the first amplifier circuit 60 to -n or ^-nx , between setting the gain of the second amplifier circuit 80 to m or m× ⁿ² , and between setting the gain of the attenuator circuit 70 to 1 or 1/n, where x is one of the integers 5, 4, 3, and 2. The amplifier circuit 36C can adjust the amplitude of the received wave i with high precision even for an ultrasonic reception signal f having a frequency of several hundred kHz to several MHz (for example, 100 kHz to 300 MHz).

Figure 13 is a diagram showing an example of the configuration of an amplifier circuit of the third embodiment. Amplifier circuit 36B is an example of the amplifier circuit 36 described above. In the third embodiment, the description of the configuration, action, and effect similar to those of the first embodiment will be omitted or simplified by invoking the above description. The amplifier circuit 36B of the third embodiment includes a first amplifier circuit 60, a second amplifier circuit 80, and a third amplifier circuit 130. In the third embodiment, the first amplifier circuit 60, the second amplifier circuit 80, and the third amplifier circuit 130 have the same configuration as the second amplifier circuit 80 in the first embodiment.

In FIG. 13, the signal output terminal of the first amplifier circuit 60 is connected in series to the signal input terminal of the third amplifier circuit 130, and the signal output terminal of the third amplifier circuit 130 is connected in series to the signal input terminal of the second amplifier circuit 80. The received wave i is output from the signal output terminal of the second amplifier circuit 80.

The third amplifier circuit 130 receives the signal (first intermediate signal M1) amplified by the first amplifier circuit 60. The third amplifier circuit 130 amplifies the input first intermediate signal M1 with a gain G4 and outputs a second intermediate signal M2, which is the amplified first intermediate signal M1. The gain G4 represents the ratio (amplification factor) of the voltage of the output second intermediate signal M2 to the voltage of the input first intermediate signal M1. The gain G4 is a positive value. The third amplifier circuit 130 has a third amplifier 111, resistors 112, 113, 114, 117, 118, and a third analog switch 115.

The third amplifier 111 receives the first intermediate signal M1. The third amplifier 111 is an operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates with a power supply voltage VB between a power supply 91 and a ground 92. The first intermediate signal M1 is input to the non-inverting input terminal of the third amplifier 111. Between the output terminal of the third amplifier 111 and the intermediate potential 93, resistors 112 and 114 are connected in series. A connection point 116 between the resistors 112 and 114 is electrically connected to the inverting input terminal of the third amplifier 111. Between the connection point 116 and the intermediate potential 93, resistors 113 and a third analog switch 115 are connected in series. Between the output terminal of the third amplifier 111 and the intermediate potential 93, resistors 118 and 117 are connected in series. The second intermediate signal M2 is output from the connection point between the resistors 118 and 117.

The third analog switch 115 switches between electrically connecting the resistor 113 to the intermediate potential 93 or leaving the resistor 113 open and not connected to the intermediate potential 93 according to the logical level (high level or low level) of the third switching signal k3. The third switching signal k3 is one of the gain adjustment signals k supplied from the control unit 35. In this embodiment, the third analog switch 115 is a single-pole double-throw type, but may be configured using a single-pole single-throw type switch.

The third amplifier circuit 130 has a non-inverting amplifier circuit formed by combining the third amplifier 111 with resistors 112, 113, 114, 117, and 118. The amplification factor (gain G4) of the third amplifier circuit 130 is as follows:

When the resistor 113 is open, the gain G4 is:
G4a=(1+R114/R112)・(R117/(R117+R118))
...(13)
R114, R112, R117, and R118 represent the resistance values of the resistors 114, 112, 117, and 118, respectively. When G4a>1, it is preferable to short-circuit the resistor 118 (R118 corresponds to 0Ω) and to leave the resistor 117 unused (not mounted; R117 corresponds to infinity). When G4a=1, it is preferable to short-circuit the resistor 118 (R118 corresponds to 0Ω), to leave the resistor 117 unused (not mounted; R117 corresponds to infinity), and to leave the resistor 112 unused (not mounted; R112 corresponds to infinity).

When the resistor 113 is connected to the intermediate potential 93, the gain G4 is
G4b=(1+R114/(R112・R113/(R112+R113)))・(R117/(R117+R118))
...(14)
R113 and R114 represent the resistance values of the resistors 113 and 114, respectively.

In other words, the third amplifier circuit 130 can switch the gain G4 between two amplification factors, G4a and G4b, according to the third switching signal k3.

The first amplifier circuit 60 amplifies the input reception signal f with a gain G5 and outputs a first intermediate signal M1, which is the amplified reception signal f. The gain G5 represents the ratio (amplification factor) of the voltage of the output first intermediate signal M1 to the voltage of the input reception signal f. The gain G5 is a positive value. The first amplifier circuit 60 has a first amplifier 61, resistors 62, 63, 64, 67, 68, and a first analog switch 65.

The first amplifier circuit 60 in the third embodiment differs from the first amplifier circuit 60 in the first embodiment in that resistors 67 and 68 are added. Resistors 68 and 67 are connected in series between the output terminal of the second amplifier 81 and the intermediate potential 93. The first intermediate signal M1 is output from the connection point between resistors 68 and 67.

The first amplifier circuit 60 has a non-inverting amplifier circuit formed by combining a first amplifier 61 with resistors 62, 63, 64, 67, and 68. The amplification factor (gain G5) of the first amplifier circuit 60 in the third embodiment is as follows:

When resistor 63 is open, the gain G5 is:
G5a=(1+R64/R62)・(R67/(R67+R68))
...(15)
R64, R62, R67, and R68 represent the resistance values of resistors 64, 62, 67, and 68, respectively. When G5a>1, it is preferable to short-circuit resistor 68 (R68 corresponds to 0Ω) and to leave resistor 67 unused (not implemented; R67 corresponds to infinity). When G5a=1, it is preferable to short-circuit resistor 68 (R68 corresponds to 0Ω), to leave resistor 67 unused (not implemented; R67 corresponds to infinity), and to leave resistor 62 unused (not implemented; R62 corresponds to infinity).

When the resistor 63 is connected to the intermediate potential 93, the gain G5 is
G5b=(1+R64/(R62・R63/(R62+R63)))・(R67/(R67+R68))
...(16)
It becomes.

In other words, the first amplifier circuit 60 can switch the gain G5 between two amplification factors, G5a and G5b, according to the third switching signal k3.

In this way, the gain G5 of the first amplifier circuit 60 can be switched by the first switching signal k1, the gain G2 of the second amplifier circuit 80 can be switched by the second switching signal k2, and the gain G4 of the third amplifier circuit 130 can be switched by the third switching signal k3. Therefore, the first amplifier circuit 60, the second amplifier circuit 80, and the third amplifier circuit 130 can switch their gains independently of each other.

Next, the gain settings of the first amplifier circuit 60, the second amplifier circuit 80, and the third amplifier circuit 130 will be explained using Figures 14 and 15.

FIG. 14 is a table showing a fourth gain setting method. In FIG. 14, the basic gain is α·β·m, and the gain increment is n. α, β, and m are positive numbers. n is a number greater than 1. The gain G5 of the first amplifier circuit 60 is set using equations (15) and (16) by combining the resistance values of resistors 62, 63, 64, 67, and 68, and G5a is α and G5b is α· ⁿ⁴ . The gain G2 of the second amplifier circuit 80 is set using equations (11) and (12) by combining the resistance values of resistors 82, 83, 84, 87, and 88, and G2a is m and G2b is m· ⁿ² . The gain G4 of the third amplifier circuit 130 is set by combining the resistance values of the resistors 112, 113, 114, 117, and 118 using equations (13) and (14), where G4a is β and G4b is β·n.

In the fourth setting method of FIG. 14, the set gain of each circuit is different from that in the first setting method of FIG. 6, but the total gain G is the same as in the first setting method of FIG. 6.

Figure 15 is a table showing a specific example of the fourth gain setting method. Figure 15 illustrates the case where the basic gains are α, β, and m = 3 (α = 1, β = 1, m = 3) and the gain increment n = 2. The total gain increases in increments of 2 from a minimum of 3 times to a maximum of 384 times, and can be switched between 8 levels.

In the fourth setting method, the total gain is the same as in the first setting method. However, when α is smaller than n (for example, when α=1 and n=2), the maximum value of the gain of the first amplifier circuit 60 is lower in the fourth setting method (=α·n ⁴ ) than in the first setting method (=n ⁵ ). Therefore, although the number of amplifiers (op-amps, etc.) used increases from two to three, the maximum gain decreases, so that the frequency band and speed of the amplifiers (op-amps, etc.) used can be suppressed, and more versatile parts can be selected.

14 shows a case where the gain G5b of the first amplifier circuit 60 is set to α· ⁿ⁴ . However, even if the gain G5b is set to α· ⁿ³ , α· ⁿ² , or α·n instead of α· ⁿ⁴ , the same effect as when it is set to α· ⁿ⁴ can be obtained. When G5b is set to α· ⁿ³ , the total gain G can be switched in seven stages from α·β·m to α·β·m· ⁿ⁶ in increments of n, and two "m· ⁿ³ "s are overlapped (not shown). When G5b is set to α· ⁿ² , the total gain G can be switched in six stages from α·β·m to α·β·m· ⁿ⁵ in increments of n, and two "m· ⁿ³ "s and two "m· ⁿ² "s are overlapped (not shown). When G5b is set to α·n, the total gain G can be switched in five stages from α·β·m to α·β·m· ⁿ⁴ in increments of n, and two "m· ⁿ³ ", two "m· ⁿ² ", and two "m·n" overlap (not shown).

Thus, the amplifier circuit 36B includes a first analog switch 65, a second analog switch 85, and a third analog switch 115 as a switching circuit capable of switching the total gain G by n times. The switching circuits switch between setting the gain of the first amplifier circuit 60 to α or α·n ^y , between setting the gain of the second amplifier circuit 80 to m or m×n ² , and between setting the gain of the third amplifier circuit 130 to β or β·n, where y is an integer of 4, 3, 2, or 1. The amplifier circuit 36B can adjust the amplitude of the received wave i with high precision even for an ultrasonic reception signal f having a frequency of several hundred kHz to several MHz (for example, 100 kHz to 300 MHz).

Figure 16 is a diagram showing an example of the configuration of an amplifier circuit of the fourth embodiment. Amplifier circuit 36D is an example of the amplifier circuit 36 described above. In the fourth embodiment, the description of the configuration, action, and effect similar to those of the second embodiment will be omitted or simplified by invoking the above description. The amplifier circuit 36D of the fourth embodiment includes a first amplifier circuit 60, a second amplifier circuit 80, and a third amplifier circuit 130. In the fourth embodiment, the first amplifier circuit 60, the second amplifier circuit 80, and the third amplifier circuit 130 have the same configuration as the first amplifier circuit 60 in the second embodiment.

In FIG. 16, the signal output terminal of the first amplifier circuit 60 is connected in series to the signal input terminal of the third amplifier circuit 130, and the signal output terminal of the third amplifier circuit 130 is connected in series to the signal input terminal of the second amplifier circuit 80. The received wave i is output from the signal output terminal of the second amplifier circuit 80.

The first amplifier circuit 60 amplifies the input reception signal f with a gain G6 and outputs a first intermediate signal M1, which is the amplified reception signal f. The gain G6 is a negative value. The third amplifier circuit 130 receives the first intermediate signal M1 output from the first amplifier circuit 60.

The third amplifier circuit 130 amplifies the input first intermediate signal M1 with a gain G8 and outputs a second intermediate signal M2, which is the amplified first intermediate signal M1. The gain G8 represents the ratio (amplification factor) of the voltage of the output second intermediate signal M2 to the voltage of the input first intermediate signal M1. The gain G8 is a negative value. The third amplifier circuit 130 has a third amplifier 111, resistors 112, 113, 114, and a third analog switch 115.

The third amplifier 111 receives the first intermediate signal M1. The third amplifier 111 is an operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates at a power supply voltage VB between a power supply 91 and a ground 92. The non-inverting input terminal of the third amplifier 111 is connected to an intermediate potential 93. The first intermediate signal M1 is input to the inverting input terminal of the third amplifier 111. Between the output terminal of the third amplifier 111 and the input terminal of the first intermediate signal M1 (the signal input terminal of the third amplifier circuit 130), a resistor 112 and a resistor 114 are connected in series. A connection point 116 between the resistor 112 and the resistor 114 is electrically connected to the inverting input terminal of the third amplifier 111. Between the connection point 116 and the output terminal of the third amplifier 111, a resistor 113 and a third analog switch 115 are connected in series. The second intermediate signal M2 is output from the output terminal of the third amplifier 111.

The third analog switch 115 switches between electrically connecting the resistor 113 to the output terminal of the third amplifier 111 or leaving the resistor 113 open and unconnected to the output terminal of the third amplifier 111 according to the logical level (high level or low level) of the third switching signal k3. The third switching signal k3 is one of the gain adjustment signals k supplied from the control unit 35. In this embodiment, the third analog switch 115 is a single-pole double-throw type, but may be configured using a single-pole single-throw type switch.

The third amplifier circuit 130 has an inverting amplifier circuit formed by combining the third amplifier 111 with resistors 112, 113, and 114. The amplification factor (gain G8) of the third amplifier circuit 130 is as follows:

When the resistor 113 is connected to the output terminal of the third amplifier 111, the gain G8 is
G8a=-(R114・R113/(R114+R113))/R112
...(21)
R112, R113, and R114 represent the resistance values of the resistors 112, 113, and 114, respectively.

When resistor 113 is open, the gain G8 is:
G8b=-R114/R112...(22)
It becomes.

In other words, the third amplifier circuit 130 can switch the gain G8 between two amplification factors, G8a and G8b, according to the third switching signal k3.

The third amplifier circuit 130 is constructed using versatile electronic components, such as an operational amplifier, resistors, and a single-pole single-throw or single-pole double-throw analog switch, which reduces the risk of component obsolescence. In addition, because it can be easily constructed using versatile small components, the circuit can be made smaller and less expensive.

The second amplifier circuit 80 receives the second intermediate signal M2 output from the third amplifier circuit 130. The second amplifier circuit 80 amplifies the input second intermediate signal M2 with a gain G7 and outputs a received wave i, which is the amplified second intermediate signal M2. The gain G7 represents the ratio (amplification factor) of the voltage of the output received wave i to the voltage of the input second intermediate signal M2. The gain G7 is a negative value.

Therefore, similar to the above-described embodiment, the gain G6 of the first amplifier circuit 60 can be switched by the first switching signal k1, the gain G7 of the second amplifier circuit 80 can be switched by the second switching signal k2, and the gain G8 of the third amplifier circuit 130 can be switched by the third switching signal k3. Therefore, the first amplifier circuit 60, the second amplifier circuit 80, and the third amplifier circuit 130 can switch their gains independently of each other.

In the fourth embodiment, the gain settings of the first amplifier circuit 60, the second amplifier circuit 80, and the third amplifier circuit 130 are explained using the explanation of the third embodiment described above with reference to FIG. 14. The fourth embodiment differs from the third embodiment in that α, β, and m are negative numbers, but is otherwise similar to the third embodiment.

The control unit 35 (Figure 1) may output a signal (hereinafter also referred to as amplitude adjustment signal p) for adjusting the amplitude of the ultrasonic wave e according to the peak hold value h. Since the amplitude of the received signal f is approximately proportional to the amplitude of the ultrasonic wave e, the amplitude of the received signal f can be controlled by varying the amplitude of the ultrasonic wave e. If the amplitude of the received signal f can be controlled, the amplitude of the received wave i, which is the waveform after amplification of the received signal f, can also be controlled.

For example, the control unit 35 compares the peak hold value h with a predetermined target amplitude value. When the control unit 35 detects that the peak hold value h is lower than the target amplitude value, it outputs an amplitude adjustment signal p that increases the amplitude of the ultrasonic wave e. When the control unit 35 detects that the peak hold value h is higher than the target amplitude value, it outputs an amplitude adjustment signal p that decreases the amplitude of the ultrasonic wave e. The control unit 35 controls the amplitude of the received wave i to a constant value by performing feedback control that outputs an amplitude adjustment signal p according to the peak hold value h output from the peak hold circuit 37.

The control unit 35 adjusts the amplitude of the ultrasonic wave e that changes with the change in the amplitude of the electrical signal d by, for example, adjusting the amplitude of the electrical signal d (e.g., one or more pulse signals that excite an ultrasonic transducer) transmitted from the transmission unit 31 using an amplitude adjustment signal p. The control unit 35 may also adjust the amplitude of the electrical signal d that changes with the change in the reference voltage (e.g., power supply voltage, etc.) supplied to the transmission unit 31 using the amplitude adjustment signal p. This adjusts the amplitude of the ultrasonic wave e.

Figure 17 is a diagram showing an example of the configuration of a transmission unit. The transmission unit 31A is an example of the transmission unit 31 described above. The transmission unit 31A has a transmission driver 120 to which the power supply voltage VDD generated by the power supply circuit 200 is input. The transmission driver 120 is, for example, an integrated circuit.

The transmission timing signal c (e.g., a pulse input signal including multiple square waves) supplied from the control unit 35 is input to the transmission driver 120. The transmission driver 120 outputs an electrical signal d that has a higher amplitude than the transmission timing signal c and the same number of pulses as the transmission timing signal c. The transmission driver 120 changes the amplitude of the electrical signal d according to the power supply voltage VDD. The transmission driver 120 increases the amplitude of the electrical signal d as the power supply voltage VDD increases, and decreases the amplitude of the electrical signal d as the power supply voltage VDD decreases.

The electrical signal d is input to the ultrasonic transducer 11a or 11b, which generates an ultrasonic wave e. The amplitude of the ultrasonic wave e is approximately proportional to the amplitude of the electrical signal d. Therefore, the control unit 35 can control the amplitude of the received signal f and the received wave i to the desired target value by adjusting the power supply voltage VDD generated by the power supply circuit 200 using the amplitude adjustment signal p.

Figure 18 is a diagram showing an example of the configuration of a power supply circuit that generates a variable power supply voltage. The power supply circuit 200A is an example of the power supply circuit 200 described above. The power supply circuit 200A is used as a power supply that determines the amplitude of the electrical signal d (and thus the amplitude of the ultrasonic wave e) in the transmission unit 31. A power supply voltage B generated by a separate power supply (not shown) is supplied to the power supply circuit 200A. The power supply circuit 200A generates a variable power supply voltage VDD, which is lower than the power supply voltage B, from the power supply voltage B.

The power supply circuit 200A divides the power supply voltage VDD using resistors 201 and 202, and feeds back the divided voltage value (feedback voltage q) to an amplifier 203, which is composed of, for example, an operational amplifier. The amplifier 203 controls the power supply voltage VDD so that the input amplitude adjustment voltage p1 and the feedback voltage q become the same. The amplitude adjustment voltage p1 is an example of the above-mentioned amplitude adjustment signal p supplied from the control unit 35.

The output terminal of amplifier 203 is connected to the emitter of transistor 204, which has a common base. Resistor 205 is connected between the power supply of power supply voltage B and the collector of transistor 204. The magnitude of the collector current flowing through resistor 205 is controlled by the output signal of amplifier 203, thereby changing the power supply voltage VDD.

The output stage of the power supply circuit 200A has a push-pull circuit formed by a PNP bipolar transistor 206 and an NPN bipolar transistor 207. The push-pull circuit changes the power supply voltage VDD by discharging or absorbing the output current at the output stage. The common base and the push-pull circuit allow the power supply circuit 200A to quickly control the rise and fall of the power supply voltage VDD.

The power supply circuit 200A is constructed using versatile electronic components such as operational amplifiers, transistors, resistors, and capacitors, which reduces the risk of component obsolescence. In addition, since it can be easily constructed using versatile small components, the circuit can be made smaller and less expensive. Furthermore, the amplitude adjustment voltage p1 can be easily generated by a DAC built into a microcomputer (not shown) that realizes the function of the flow measurement unit 50, for example, and a variable amplitude adjustment voltage p1 can be easily generated to control the power supply voltage VDD. Furthermore, the operational amplifier used in the amplifier 203 can keep the voltage of the control power supply low, eliminating the need to use expensive high power supply voltage types, further improving versatility.

The power supply circuit 200A is used as a power supply that determines the amplitude of the ultrasonic wave e. Since the amplitude of the received signal f is approximately proportional to the amplitude of the ultrasonic wave e, the amplitude of the received signal f can be controlled by varying the amplitude of the ultrasonic wave e. The DAC built into the microcontroller has a resolution of about 10 to 14 bits, allowing fine control of the amplitude adjustment voltage p1. By using a circuit that allows fine control of the amplitude adjustment voltage p1 in combination with the above-mentioned amplifier circuit that allows the gain to be switched, fine control is possible within a wide range of amplification factors, and the dynamic range of signal amplitude control can be improved.

Although the embodiments have been described above, they are presented as examples, and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

The amplifier circuit is not limited to ultrasonic flow meters, but may also be applied to other devices such as ultrasonic level meters that use ultrasonic waves to measure the height level of a fluid, such as a water level, and ultrasonic thickness gauges that use ultrasonic waves to measure the thickness of an object.

REFERENCE SIGNS LIST 10a, 10b ultrasonic probe 11a, 11b ultrasonic transducer 12a, 12b wedge 31 transmitter 32 receiver 33a, 33b switch 35 controller 36, 36A, 36B, 36C, 36D amplifier circuit 37 peak hold circuit 38 reception timing detection circuit 40 time measurement unit 50 flow rate measurement unit 60 first amplifier circuit 65 first analog switch 70 attenuator circuit 73 third analog switch 80 second amplifier circuit 85 second analog switch 91 power supply 92 ground 100 piping 102 fluid 115 third analog switch 120 transmission driver 130 third amplifier circuit 200 power supply circuit 300 ultrasonic flow meter

Claims (8)

An amplifier circuit including a first amplifier circuit, a second amplifier circuit, and an attenuator circuit connected in series,
Let m be the base gain of the amplifier circuit, n be the gain increment, m be a number other than 0, n be a number greater than 1, and x be an integer of 5, 4, 3, or 2.
an amplifier circuit comprising: a switching circuit that switches between setting a gain of the first amplifier circuit to n or ^nx , or between setting a gain of -n or ^-nx , switches between setting a gain of the second amplifier circuit to m or m× ⁿ² , and switches between setting a gain of the attenuator circuit to 1 or 1/n. The amplifier circuit of claim 1, wherein the first amplifier circuit, the attenuator circuit, and the second amplifier circuit are connected in series in this order. The amplifier circuit of claim 1, wherein the first amplifier circuit, the second amplifier circuit, and the attenuator circuit are connected in series in this order. The amplifier circuit of claim 1, wherein x is 5. The amplifier circuit of claim 1, wherein x is 4. An amplifier circuit comprising a first amplifier circuit, a second amplifier circuit, and a third amplifier circuit connected in series,
Let the basic gain of the amplifier circuit be α β m, the gain increment be n, α be a non-zero number, β be a non-zero number, m be a non-zero number, n be a number greater than 1, and y be an integer selected from 4, 3, 2, and 1.
an amplifier circuit comprising: a switching circuit for switching between setting a gain of the first amplifier circuit to α or α·n ^y , switching between setting a gain of the second amplifier circuit to m or m×n ² , and switching between setting a gain of the third amplifier circuit to β or β·n. The amplifier circuit of claim 6, wherein y is 4. An amplifier circuit according to any one of claims 1 to 7, which amplifies an input ultrasonic reception signal;
a peak hold circuit that outputs a peak hold value corresponding to a peak value of an input wave, which is the received signal amplified by the amplifier circuit;
a flow rate measuring unit that calculates a flow rate of a fluid through which the ultrasonic waves propagate by using a measured time from a point in time when the transmission of the ultrasonic waves starts to a point in time when the input wave crosses a reference level after the input wave crosses a threshold voltage;
an ultrasonic flowmeter comprising: a control unit that outputs a signal to adjust the gain of the amplifier circuit according to the peak hold value, or that outputs a signal to adjust the gain of the amplifier circuit and a signal to adjust the amplitude of the ultrasonic wave or the threshold voltage.

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