JP2024101224A - Peak hold circuit and ultrasonic flow meter - Google Patents

Abstract

A peak hold circuit is provided that can reduce an error in a voltage that is held according to a peak value.
[Solution] A peak hold circuit comprising: a first amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein an input wave is input to the non-inverting input terminal; a first diode having an anode electrically connected to the inverting input terminal and a cathode electrically connected to the output terminal; a second diode having a cathode electrically connected to the cathode of the first diode and the output terminal; and a capacitor having one end electrically connected to the anode of the second diode, which holds a voltage corresponding to the minimum value of the input wave.
[Selected figure] Figure 5

Description

This disclosure relates to a peak hold circuit and an ultrasonic flow meter.

There is an ultrasonic flowmeter that detects a specific vibration half-wave by transmitting ultrasonic waves twice with a short transmission interval where the change in the amplitude of the received signal can be ignored, detecting the negative peak value of the first received signal, and detecting the intersection point between the second received signal and a variable threshold voltage proportional to the detected negative peak value. This ultrasonic flowmeter measures the time from the start of the second ultrasonic transmission to the zero cross point where the rear end of the specific vibration half-wave intersects with the baseline level as the propagation time of the second ultrasonic wave, and uses this propagation time to measure the flow rate of the fluid through which the ultrasonic wave propagates.

JP 2003-014515 A

When dealing with input waves such as ultrasonic reception signals, as in the ultrasonic flowmeter described above, a peak hold circuit may be used that detects the peak value of the input wave and holds the voltage corresponding to the peak value. However, depending on the configuration of the peak hold circuit, the error in the voltage held according to the peak value may increase.

This disclosure provides a peak hold circuit capable of reducing an error in the voltage held according to the peak value, and an ultrasonic flowmeter equipped with the peak hold circuit.

In a first aspect of the present disclosure,
a first amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein an input wave is input to the non-inverting input terminal or the inverting input terminal;
a first diode having an anode electrically connected to the inverting input terminal and a cathode electrically connected to the output terminal;
a second diode having a cathode electrically connected to the cathode of the first diode and to the output terminal;
A peak hold circuit and an ultrasonic flowmeter including the peak hold circuit are provided, the peak hold circuit including a capacitor whose one end is electrically connected to the anode of the second diode and which holds a voltage corresponding to the peak value of the input wave.

In a second aspect of the present disclosure,
a first amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein an input wave is input to the non-inverting input terminal or the inverting input terminal;
a first diode having a cathode electrically connected to the inverting input terminal and an anode electrically connected to the output terminal;
a second diode having an anode electrically connected to the anode of the first diode and the output terminal;
A peak hold circuit and an ultrasonic flowmeter including the peak hold circuit are provided, the peak hold circuit including a capacitor having one end electrically connected to the cathode of the second diode and holding a voltage corresponding to the peak value of the input wave.

The present disclosure provides a peak hold circuit that can reduce the error in the voltage held according to the peak value, and an ultrasonic flowmeter equipped with the peak hold circuit.

FIG. 1 is a diagram illustrating an example of a configuration of an ultrasonic flowmeter according to an embodiment. FIG. 2 is a diagram illustrating Snell's law for determining the angle of incidence in a fluid. FIG. 2 is a diagram illustrating an example of the configuration of a receiving unit. FIG. 4 is a diagram for explaining a reception timing signal. FIG. 2 is a diagram illustrating a first configuration example of a peak hold circuit. 4 is an operational waveform diagram of a first configuration example of a peak hold circuit; FIG. FIG. 13 is a diagram illustrating a comparative example of a peak hold circuit. FIG. 13 is a diagram illustrating a second configuration example of the peak hold circuit. 11 is an operational waveform diagram of a second configuration example of the peak hold circuit; FIG. FIG. 13 is a diagram illustrating a third configuration example of the peak hold circuit. FIG. 13 is a diagram illustrating a fourth configuration example of the peak hold circuit. FIG. 2 illustrates an example of the configuration of a transmission unit. FIG. 1 is a diagram illustrating an example of a configuration of a power supply circuit that generates a variable power supply voltage.

The following describes an embodiment of the present disclosure with reference to the drawings.

Figure 1 is a diagram showing an example of the configuration of an ultrasonic flowmeter according to one embodiment. The ultrasonic flowmeter uses ultrasonic waves to measure the flow rate of a fluid (gas or liquid) flowing through a flow path. The ultrasonic flowmeter includes two or more ultrasonic transducers arranged along or within a measurement pipeline. The two or more ultrasonic transducers include a transmitting transducer and a receiving transducer. The transmitting transducer and the receiving transducer are arranged so that the direction connecting the transmitting transducer and the receiving transducer is oblique to or coincident with the direction of the fluid flow. The ultrasonic flowmeter measures the flow rate of the fluid in the measurement pipeline from the propagation time of ultrasonic waves transmitted and received between the transmitting transducer and the receiving transducer.

The ultrasonic flowmeter 300 shown in FIG. 1 includes an ultrasonic probe 10a, an ultrasonic probe 10b, a control unit 35, a transmitting unit 31, a switch 33a, a switch 33b, a receiving unit 32, a time measuring unit 40, and a flow measuring unit 50.

The control unit 35 controls switching between transmitting ultrasonic waves e from the ultrasonic transducer 11a of the ultrasonic probe 10a and transmitting ultrasonic waves e from the ultrasonic transducer 11b of the ultrasonic probe 10b toward the fluid 102 in the pipe 100.

The ultrasonic probe 10a is disposed upstream of the fluid 102 flowing through the pipe 100 so as to face the outer surface of the pipe 100. The ultrasonic probe 10a has an ultrasonic transducer 11a and a resin wedge 12a. The ultrasonic probe 10b is disposed downstream of the fluid 102 flowing through the pipe 100 so as to face the outer surface of the pipe 100. The ultrasonic probe 10b has an ultrasonic transducer 11b and a resin wedge 12b.

The wedge 12a has a surface that is inclined relative to the outer surface of the pipe 100, and the ultrasonic transducer 11a is attached to that surface. Therefore, the ultrasonic waves generated by the ultrasonic transducer 11a enter the pipe 100 from the wedge 12a at a predetermined inclination angle, then propagate through the fluid 102 and reach the ultrasonic transducer 11b.

The wedge 12b has a surface that is inclined with respect to the outer surface of the pipe 100, and the ultrasonic transducer 11b is attached to that surface. Therefore, the ultrasonic waves generated by the ultrasonic transducer 11b enter the pipe 100 from the wedge 12b at a predetermined inclination angle, then propagate through the fluid 102 and reach the ultrasonic transducer 11a.

The ultrasonic transducer 11a is selectively connected to the transmitting unit 31 or the receiving unit 32 by the switching operation of the switch 33a. The ultrasonic transducer 11b is selectively connected to the receiving unit 32 or the transmitting unit 31 by the switching operation of the switch 33b.

The control unit 35 is a circuit that generates selection signals a and b that select one of the ultrasonic transducers 11a and 11b from which ultrasonic waves should be transmitted (i.e., one of the transducers to be excited), and a transmission timing signal c that indicates the timing of ultrasonic transmission.

When the ultrasonic transducer 11a is selected as the transducer to transmit the ultrasonic wave e, the switch 33a selects the ultrasonic transducer 11a as the transducer to transmit the ultrasonic wave e in accordance with the selection signal a from the control unit 35. On the other hand, the switch 33b selects the ultrasonic transducer 11b as the transducer to receive the ultrasonic wave e in accordance with the selection signal b from the control unit 35.

The transmitting unit 31 is a circuit that transmits an electric signal d (for example, one or more pulse signals that excite the ultrasonic transducer 11a) to the ultrasonic transducer 11a via the switch 33a in accordance with a transmission timing signal c from the control unit 35, and causes the ultrasonic transducer 11a to generate an ultrasonic wave e. The generated ultrasonic wave e passes through the wedge 12a and the pipe 100 and enters the fluid 102 in the pipe 100. The ultrasonic wave e that enters the fluid 102 in the pipe 100 propagates to the ultrasonic transducer 11b of the ultrasonic probe 10b installed on the outer surface of the opposite side of the pipe 100, and is converted into an electric signal by the ultrasonic transducer 11b. The electric signal output from the ultrasonic transducer 11b is received as a reception signal f by the receiving unit 32 via the switch 33b.

The time measurement unit 40 measures the time from when the ultrasonic wave e is transmitted from the ultrasonic transducer 11a to when it is received by the ultrasonic transducer 11b as the propagation time Tab. The time measurement unit 40 is a circuit that measures the propagation time Tab based on, for example, a transmission timing signal c indicating the timing at which the transmission of the ultrasonic wave e from the ultrasonic transducer 11a starts, and a reception timing signal g indicating the timing at which the ultrasonic wave e is received by the ultrasonic transducer 11b.

Next, the ultrasonic flowmeter 300 switches between switches 33a and 33b in response to a signal from the control unit 35, reversing the transmission/reception relationship between the ultrasonic probes 10a and 10b.

When ultrasonic transducer 11b is selected as the transducer to transmit ultrasonic waves e, switch 33a selects ultrasonic transducer 11a as the transducer to receive ultrasonic waves e in accordance with selection signal a from control unit 35. On the other hand, switch 33b selects ultrasonic transducer 11b as the transducer to transmit ultrasonic waves e in accordance with selection signal b from control unit 35.

The transmitting unit 31 is a circuit that transmits an electric signal d (for example, one or more pulse signals that excite the ultrasonic transducer 11b) to the ultrasonic transducer 11b via the switch 33b in accordance with a transmission timing signal c from the control unit 35, and causes the ultrasonic transducer 11b to generate an ultrasonic wave e. The generated ultrasonic wave e passes through the wedge 12b and the pipe 100, and enters the fluid 102 in the pipe 100. The ultrasonic wave e that enters the fluid 102 in the pipe 100 propagates to the ultrasonic transducer 11a of the ultrasonic probe 10a installed on the outer surface of the opposite side of the pipe 100, and is converted into an electric signal by the ultrasonic transducer 11a. The electric signal output from the ultrasonic transducer 11a is received as a reception signal f by the receiving unit 32 via the switch 33a.

The time measurement unit 40 measures the time from when the ultrasonic wave e is transmitted from the ultrasonic transducer 11b to when it is received by the ultrasonic transducer 11a as the propagation time Tba. The time measurement unit 40 is a circuit that measures the propagation time Tba based on, for example, a transmission timing signal c indicating the timing at which the transmission of the ultrasonic wave e from the ultrasonic transducer 11b starts, and a reception timing signal g indicating the timing at which the ultrasonic wave e is received by the ultrasonic transducer 11a.

The order in which the propagation times Tab and Tba are measured may be reversed.

The flow rate measurement unit 50 calculates the flow rate Q of the fluid 102 using the measurement times (propagation times Tab and Tba) obtained by the time measurement unit 40. Next, the calculation of the flow rate Q will be described.

Regarding the propagation times Tab and Tba,
Tab=Lf/(Cf+Vsinθ _fs )...(1)
Tba=Lf/(Cf-Vsinθ _fs )...(2)
Here, Cf is the sound speed in the fluid 102 in the pipe 100, V is the flow velocity of the fluid 102, _θfs is the angle of incidence in the fluid (the angle of refraction from the pipe 100 to the fluid 102 or the angle of incidence from the fluid 102 to the pipe 100), and Lf is the length of the propagation path 110 of the ultrasonic wave e in the pipe 100.

From equations (1) and (2), solving for V gives
V=Lf/(2sinθ _fs )×((1/Tab)-(1/Tba))...(3)
It becomes.

The flow rate Q is
Q=V×A...(4)
Here, A is the cross-sectional area of the pipe 100. The cross-sectional area A is calculated by using the inner radius r of the pipe 100 as follows:
A=π×r ² ...(5)
This is expressed as:

FIG. 2 is a diagram for explaining Snell's law for determining the angle of incidence θ _fs in a fluid. According to Snell's law,
Cw/sinθ _w = Cp/sinθ _p = Cf/sinθ _fs ...(6)
The following relational expression is established. Here, Cw is the sound speed in the wedge 12a, and _θw is the angle of incidence in the wedge (angle of incidence from the wedge 12a to the pipe 100 or angle of refraction from the pipe 100 to the wedge 12a). Cp is the sound speed in the pipe 100, and _θp is the angle of incidence in the pipe (angle of refraction from the wedge 12a to the pipe 100, angle of incidence from the pipe 100 to the fluid 102, or angle of incidence from the pipe 100 to the wedge 12a). Cf is the sound speed in the fluid 102, and _θfs is the angle of incidence in the fluid (angle of refraction from the pipe 100 to the fluid 102 or angle of incidence from the fluid 102 to the pipe 100).

Since Cw, sin _θw , and Cf are known values, the angle of incidence θ _fs in the fluid can be obtained from equation (6). Therefore, the flow rate measurement unit 50 can calculate the flow rate Q based on equations (1) to (5).

The flow rate measurement unit 50 is, for example, an arithmetic circuit including a processor such as a CPU (Central Processing Unit) and a memory. The arithmetic circuit may include at least one of the control unit 35 and the time measurement unit 40. Each function of the flow rate measurement unit 50, the control unit 35, and the time measurement unit 40 (the processing performed by each unit) is realized, for example, by the processor operating according to a program stored in the memory. Each function may be realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). The control unit 35 or the time measurement unit 40 may be realized by a logic circuit.

Figure 3 is a diagram showing an example of the configuration of the receiving unit. The receiving unit 32 has an amplifier circuit 36, a reception timing detection circuit 38, and a peak hold circuit 37. The amplifier circuit 36 amplifies the reception signal f input via the switch 33a or switch 33b, and outputs a reception wave i which is the amplified reception signal f. The reception timing detection circuit 38 generates a reception timing signal g which indicates the timing at which the ultrasonic transducer 11a or the ultrasonic transducer 11b receives the ultrasonic wave e based on the input reception wave i.

4 is a diagram for explaining the reception timing signal g. The reception timing detection circuit 38 detects the point in time at which the reception wave i crosses the reference level _VCOM after crossing the threshold voltage _VTHLD (FIG. 4 illustrates the zero-cross point in time q8x or the zero-cross point in time q10x).

The reception timing detection circuit 38 detects a specific vibration half wave whose amplitude crosses the threshold voltage _VTHLD among a plurality of vibration half waves included in the reception wave i. For example, the reception timing detection circuit 38 detects the eighth vibration half wave whose amplitude crosses the threshold voltage _VTHLD at the trigger time c8x, or the tenth vibration half wave whose amplitude crosses the threshold voltage _VTHLD at the trigger time c10x, as the specific vibration half wave. The reception timing detection circuit 38 detects the time when the rear end of the specific vibration half wave crosses the reference level _VCOM (FIG. 4 illustrates the zero cross time q8x or the zero cross time q10x) and outputs the stop pulse STOP generated at that time as the reception timing signal g.

The time measurement unit 40 (Figure 3) measures the time from the transmission timing signal c, which indicates the start timing of transmission of ultrasound e from the ultrasound transducer 11a, to the reception timing signal g (stop pulse STOP), which indicates the reception timing of ultrasound e at the ultrasound transducer 11b. The time measurement unit 40 outputs the measurement value of this time as the propagation time Tab. Similarly, the time measurement unit 40 measures the time from the transmission timing signal c, which indicates the start timing of transmission of ultrasound e from the ultrasound transducer 11b, to the reception timing signal g (stop pulse STOP), which indicates the reception timing of ultrasound e at the ultrasound transducer 11a. The time measurement unit 40 outputs the measurement value of this time as the propagation time Tba.

However, if the amplitude or threshold voltage _VTHLD of the received wave i shown in FIG. 4 is out of the expected value, the reception timing signal g (stop pulse STOP) may be generated based on the vibration half wave one wave before or one wave after. In this case, a measurement error of the propagation time Tab or the propagation time Tba may occur. The ultrasonic flowmeter of this embodiment includes a control unit 35 (FIG. 3) that controls the amplitude of the received wave i to a constant value or the threshold voltage _VTHLD to a value that allows a specific vibration half wave to be detected, depending on the peak value of the received wave i measured by the peak hold circuit 37 (FIG. 3). This reduces the measurement error of the propagation time Tab or the propagation time Tba.

In FIG. 3, the received signal f is input to the amplifier circuit 36 via the switch 33a or the switch 33b. The received wave i, which is the received signal f amplified by the amplifier circuit 36, is input to the time measurement unit 40, which measures the propagation time Tab and the propagation time Tba as described above. Meanwhile, the received wave i is also input to the peak hold circuit 37. The peak hold circuit 37 outputs a peak hold value h corresponding to the peak value (minimum or maximum value of the amplitude) of the received wave i to the control unit 35. The peak hold value h is an analog voltage, but may be treated as a digital value converted by an AD converter (not shown).

The control unit 35 may output a gain adjustment signal k for adjusting the gain of the amplifier circuit 36 according to the peak hold value h. The gain of the amplifier circuit 36 represents the ratio of the voltage of the received wave i output to the voltage of the input received signal f. For example, the control unit 35 compares the peak hold value h with a predetermined target peak value. When the control unit 35 detects that the peak hold value h is lower than the target peak value, it outputs a gain adjustment signal k that increases the gain of the amplifier circuit 36. When the control unit 35 detects that the peak hold value h is higher than the target peak value, it outputs a gain adjustment signal k that decreases the gain of the amplifier circuit 36. The control unit 35 controls the amplitude of the received wave i to a constant value by performing feedback control that outputs the gain adjustment signal k according to the peak hold value h output from the peak hold circuit 37.

The control unit 35 may output a threshold voltage adjustment signal l for adjusting the threshold voltage _VTHLD in accordance with the peak hold value h output from the peak hold circuit 37. For example, the control unit 35 outputs a threshold voltage adjustment signal l for adjusting the threshold voltage _VTHLD to a value at which a specific vibration half wave can be detected in accordance with the difference between a predetermined reference voltage and the peak hold value h.

Figure 5 is a diagram showing a first configuration example of a peak hold circuit. Peak hold circuit 37A is an example of the above-mentioned peak hold circuit 37. Peak hold circuit 37A detects the peak value (minimum value) of the input wave (received wave i) and outputs a peak hold voltage corresponding to the detected minimum value as peak hold value h. Peak hold circuit 37A includes a first amplifier 61, a first diode 63, a second diode 65, and a capacitor 67.

The first amplifier 61 receives the received wave i. The first amplifier 61 is an operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates on a power supply voltage VB between a power supply 91 and ground 92. The received wave i is input to the non-inverting input terminal of the first amplifier 61. The output terminal and the inverting input terminal of the first amplifier 61 are electrically connected to each other, forming a voltage follower with high input impedance and low output impedance. By forming a voltage follower, the first amplifier 61 can convert high input impedance to low output impedance, so that a charge (voltage) corresponding to the peak value of the received wave i can be charged to the capacitor 67 in a short period of time.

The anode of the first diode 63 is electrically connected to the inverting input terminal of the first amplifier 61, and the cathode of the first diode 63 is electrically connected to the output terminal of the first amplifier 61. In this example, the anode of the first diode 63 is electrically connected to the inverting input terminal of the first amplifier 61 via a resistive element 62, but the resistive element 62 may be omitted. Since the anode of the first diode 63 is connected to the inverting input terminal and the cathode of the first diode 63 is connected to the output terminal of the first amplifier 61, the first amplifier 61 outputs a voltage V1 from the output terminal that is lower than the voltage of the received wave i by the forward voltage of the first diode 63.

The cathode of the second diode 65 is electrically connected to the cathode of the first diode 63 and the output terminal of the first amplifier 61. The anode of the second diode 65 is electrically connected to one end of the capacitor 67. In this example, the anode of the second diode 65 is electrically connected to one end of the capacitor 67 via a resistive element 66, and the other end of the capacitor 67 is electrically connected to ground 92. The capacitor 67 is a capacitive element that holds a voltage Vc corresponding to the peak value (minimum value) of the received wave i.

The second diode 65 is conductive when the voltage V1 is lower than the voltage Vc minus the forward voltage of the second diode 65, and the capacitor 67 is discharged through the second diode 65. The current discharged from the capacitor 67 through the second diode 65 flows into the output terminal of the first amplifier 61. As a result, a voltage obtained by adding the forward voltage of the second diode 65 to the minimum value of the voltage V1 is held as the voltage Vc by the capacitor 67. Therefore, the peak hold circuit 37A holds the voltage Vc corresponding to the peak value (minimum value) on the negative side of the received wave i (see FIG. 6), and is therefore suitable for the case in which the threshold voltage _VTHLD is on the negative side with respect to the reference level _VCOM as shown in FIG. 4.

In FIG. 5, the cathodes of the first diode 63 and the second diode 65 are connected to each other. A voltage difference equal to the forward voltage of the first diode 63 occurs between the voltage of the received wave i and the voltage V1 of the output terminal of the first amplifier 61 (see FIG. 6). However, this voltage difference is offset by the forward voltage of the second diode 65. Therefore, a voltage approximately equal to the minimum value of the voltage of the received wave i is held as voltage Vc in the capacitor 67, reducing the error in the voltage Vc held according to the peak value of the received wave i.

If the peak hold circuit 37X (Figure 7) does not have the first diode 63 and bias element 64, a voltage difference equal to the forward voltage of the second diode 65 occurs between the voltage Vc held by the capacitor 67 and the voltage of the received wave i. This can cause an error in voltage Vc due to the forward voltage of the second diode 65. However, in the case of the peak hold circuit 37A (Figure 5), a voltage difference equal to the forward voltage of the first diode 63 occurs between the voltage of the received wave i and voltage V1, so the error caused by the forward voltage of the second diode 65 is offset. This improves the error caused by the forward voltage of the second diode 65.

In addition, it is preferable to use a diode with a smaller leakage current than a Schottky diode for the second diode 65 in order to suppress leakage current and reduce the change in the voltage charged to the capacitor 67.

To accurately cancel out the error, it is preferable that the forward voltages of the first diode 63 and the second diode 65 are uniform. Therefore, it is preferable that the forward voltage characteristics (e.g., electrical characteristics or temperature characteristics) of the second diode 65 are the same as those of the first diode 63. For example, diodes of the same type are preferable, and diodes from the same lot are more preferable. Furthermore, if diode components that incorporate multiple diode elements in the same package are used as the first diode 63 and the second diode 65, the characteristics and temperature of both diodes will be uniform, resulting in better effects.

The peak hold circuit 37A may include a bias element 64 that biases the first diode 63. The bias element 64 is interposed between the power supply 91 and the anode of the first diode 63. By including the bias element 64, the first diode 63 is biased so that a current flows from the anode to the cathode, and the voltage V1 is stabilized. If the bias element 64 is a resistive element, the first diode 63 is biased so that a current always flows from the anode to the cathode, and the voltage V1 is stabilized. The bias element 64 is not limited to a resistive element, and may be another element such as a transistor.

The peak hold circuit 37A may include a second amplifier 72 whose input terminal is electrically connected to one end of the capacitor 67. The capacitor 67 is connected to the second amplifier 72 with a high input impedance so that the voltage Vc charged to the capacitor 67 does not change. The second amplifier 72 outputs a peak hold voltage that is approximately equal to the voltage Vc of the capacitor 67 as a peak hold value h. The peak hold voltage is read by an AD converter (not shown), and the peak hold value h is measured.

The second amplifier 72 receives the voltage Vc of the capacitor 67. The second amplifier 72 is an operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, and operates on a power supply voltage VB between a power supply 91 and ground 92. The voltage Vc is input to the non-inverting input terminal of the second amplifier 72. The output terminal and the inverting input terminal of the second amplifier 72 are electrically connected to each other, forming a voltage follower with high input impedance and low output impedance. By forming a voltage follower, the second amplifier 72 can convert a high input impedance to a low output impedance, and can therefore quickly output a peak hold voltage corresponding to the voltage Vc as a peak hold value h.

The output terminal of the second amplifier 72 may be electrically connected to the inverting input terminal of the second amplifier 72 via a filter in which a capacitive element 73 and a resistive element 74 are connected in parallel. This stabilizes the peak hold voltage output from the output terminal of the second amplifier 72.

When the current measurement of the peak value of the received wave i is completed, the voltage Vc charged in the capacitor 67 is reset to prepare for the next measurement. The peak hold circuit 37A includes a reset circuit 75 that resets the voltage Vc according to a reset signal j supplied from the control unit 35.

The reset circuit 75 in FIG. 5 has a transistor 69 whose collector or drain is electrically connected to one end of a capacitor 67. In this example, the collector or drain of the transistor 69 is electrically connected to one end of the capacitor 67 via a resistor 68.

5 is a PNP-type bipolar transistor, but may be a P-channel field effect transistor (FET). In the case of a bipolar transistor, the transistor 69 has a collector electrically connected to one end of the capacitor 67, an emitter electrically connected to an intermediate potential 93 (for example, the above-mentioned reference level V _COM ) or a power supply 91, and a base to which a reset signal j is input via a resistor element 71. In the case of a FET, the transistor 69 has a drain electrically connected to one end of the capacitor 67, a source electrically connected to an intermediate potential 93 (for example, the above-mentioned reference level V _COM ) or a power supply 91, and a gate to which a reset signal j is input via a resistor element 71.

When the reset signal j input to the base or gate becomes close to ground 92, the transistor 69 becomes conductive and the capacitor 67 is reset (see FIG. 6). As a result, the potential of one end of the capacitor 67 becomes the intermediate potential 93 or the potential of the power supply 91.

In Figure 5, leakage current from transistor 69 can cause measurement errors. The voltage Vc held by capacitor 67 changes over time due to leakage current, causing errors. If resistor 70 is electrically connected between the emitter and base of transistor 69, transistor 69 is reliably turned off, suppressing this leakage current. As a result, in the configuration of Figure 5, the rise in held voltage Vc is suppressed and it is kept at an approximately constant value.

In this way, with the peak hold circuit 37A, the forward voltage of one diode is offset by the forward voltage of the other diode, reducing the error in the voltage Vc that is held according to the peak value. Furthermore, since the peak hold circuit 37A does not have a configuration in which the output of the second amplifier 72 is fed back to the first amplifier 61, the error that occurs in the voltage Vc due to insufficient amplifier operating speed is reduced. As a result, the peak hold circuit 37A can accurately hold the minimum value of the received wave i, even for ultrasonic received waves i with frequencies of several hundred kHz to several MHz (for example, 100 kHz to 300 MHz).

Figure 8 is a diagram showing a second configuration example of a peak hold circuit. In the second configuration example, the explanation of the same configuration, action, and effect as the first configuration example will be omitted or simplified by invoking the above explanation. Peak hold circuit 37B is an example of the above peak hold circuit 37. Peak hold circuit 37B detects the peak value (maximum value) of the input wave (received wave i) and outputs a peak hold voltage corresponding to the detected maximum value as a peak hold value h.

In the peak hold circuit 37B shown in FIG. 8, the polarity of the first diode 63 and the second diode 65 is reversed compared to the peak hold circuit 37A shown in FIG. 5. In addition, in the peak hold circuit 37B shown in FIG. 8, the bias element 64 that biases the first diode 63 is interposed between the ground 92 and the cathode of the first diode 63.

The anode of the first diode 63 is electrically connected to the output terminal of the first amplifier 61, and the cathode of the first diode 63 is electrically connected to the inverting input terminal of the first amplifier 61. In this example, the cathode of the first diode 63 is electrically connected to the inverting input terminal of the first amplifier 61 via a resistive element 62, but the resistive element 62 may be omitted. Since the cathode of the first diode 63 is connected to the inverting input terminal and the anode of the first diode 63 is connected to the output terminal of the first amplifier 61, the first amplifier 61 outputs a voltage V1 from the output terminal that is higher than the voltage of the received wave i by the forward voltage of the first diode 63.

The anode of the second diode 65 is electrically connected to the anode of the first diode 63 and the output terminal of the first amplifier 61. The cathode of the second diode 65 is electrically connected to one end of the capacitor 67. In this example, the cathode of the second diode 65 is electrically connected to one end of the capacitor 67 via a resistive element 66, and the other end of the capacitor 67 is electrically connected to ground 92. The capacitor 67 is a capacitive element that holds a voltage Vc corresponding to the peak value (maximum value) of the received wave i.

The second diode 65 is conductive when the voltage V1 is higher than the sum of the voltage Vc and the forward voltage of the second diode 65, and the capacitor 67 is charged via the second diode 65. The current charged from the output terminal of the first amplifier 61 via the second diode 65 flows into the capacitor 67. As a result, a voltage obtained by subtracting the forward voltage of the second diode 65 from the maximum value of the voltage V1 is held in the capacitor 67 as the voltage Vc. Therefore, the peak hold circuit 37B holds the voltage Vc corresponding to the peak value (maximum value) on the positive side of the received wave i (see FIG. 9), and is therefore suitable for the case where the threshold voltage _VTHLD is on the positive side with respect to the reference level _VCOM , as opposed to the case shown in FIG. 4.

In FIG. 8, the anodes of the first diode 63 and the second diode 65 are connected to each other. A voltage difference equal to the forward voltage of the first diode 63 occurs between the voltage of the received wave i and the voltage V1 of the output terminal of the first amplifier 61 (see FIG. 9). However, this voltage difference is offset by the forward voltage of the second diode 65. Therefore, a voltage approximately equal to the maximum value of the voltage of the received wave i is held as voltage Vc in the capacitor 67, reducing the error in the voltage Vc held according to the peak value of the received wave i.

8 is an NPN-type bipolar transistor, but may be an N-channel field effect transistor (FET). In the case of a bipolar transistor, the transistor 69 has a collector electrically connected to one end of the capacitor 67, an emitter electrically connected to an intermediate potential 93 (for example, the above-mentioned reference level V _COM ) or a ground 92, and a base to which a reset signal j is input via a resistor element 71. In the case of a FET, the transistor 69 has a drain electrically connected to one end of the capacitor 67, a source electrically connected to an intermediate potential 93 (for example, the above-mentioned reference level V _COM ) or a ground 92, and a gate to which a reset signal j is input via a resistor element 71.

When the reset signal j input to the base or gate reaches a potential close to the power supply 91, the transistor 69 becomes conductive and the capacitor 67 is reset (see FIG. 9). As a result, the potential of one end of the capacitor 67 becomes the intermediate potential 93 or the ground potential 92.

In Figure 8, leakage current from transistor 69 can cause measurement errors. The voltage Vc held by capacitor 67 changes over time due to leakage current, causing errors. If resistor 70 is electrically connected between the emitter and base of transistor 69, transistor 69 is reliably turned off, suppressing this leakage current. As a result, in the configuration of Figure 8, the drop in held voltage Vc is suppressed and it is maintained at an approximately constant value.

In this way, with the peak hold circuit 37B, the forward voltage of one diode is offset by the forward voltage of the other diode, reducing the error in the voltage Vc that is held according to the peak value. Furthermore, since the peak hold circuit 37B does not have a configuration in which the output of the second amplifier 72 is fed back to the first amplifier 61, the error that occurs in the voltage Vc due to insufficient amplifier operating speed is reduced. As a result, the peak hold circuit 37B can accurately hold the maximum value of the received wave i, even for ultrasonic received waves i with frequencies of several hundred kHz to several MHz (for example, 100 kHz to 300 MHz).

Figure 10 is a diagram showing a third example configuration of a peak hold circuit. In the third example configuration, the explanation of the same configuration, action, and effect as the first example configuration will be omitted or simplified by invoking the above explanation. Peak hold circuit 37C is an example of the above peak hold circuit 37. Peak hold circuit 37C detects the peak value (maximum value) of the input wave (received wave i) and outputs a peak hold voltage corresponding to the detected maximum value as a peak hold value h.

The peak hold circuit 37C shown in FIG. 10 has an inverted terminal to which the input wave (received wave i) is input, compared to the peak hold circuit 37A shown in FIG. 5. In the peak hold circuit 37A shown in FIG. 5, the first amplifier 61 constitutes a non-inverting amplifier circuit that outputs the received wave i without inverting it, and in the peak hold circuit 37C shown in FIG. 10, the first amplifier 61 constitutes an inverting amplifier circuit that inverts and outputs the received wave i. In the peak hold circuit 37C, the received wave i is input to the inverting input terminal of the first amplifier 61, and the non-inverting input terminal of the first amplifier 61 is electrically connected to the intermediate potential 93. Like the peak hold circuit 37A, the peak hold circuit 37C can accurately hold the maximum value of the received wave i even when the received wave i is an ultrasonic wave with a frequency of several hundred kHz to several MHz (for example, 100 kHz to 300 MHz).

Figure 11 is a diagram showing a fourth example configuration of a peak hold circuit. In the fourth example configuration, the explanation of the same configuration, action, and effect as the first and second examples will be omitted or simplified by invoking the above explanation. Peak hold circuit 37D is an example of the above peak hold circuit 37. Peak hold circuit 37D detects the peak value (minimum value) of the input wave (received wave i) and outputs a peak hold voltage corresponding to the detected minimum value as a peak hold value h.

The peak hold circuit 37D shown in FIG. 11 has an inverted terminal to which the input wave (received wave i) is input, compared to the peak hold circuit 37B shown in FIG. 8. In the peak hold circuit 37B shown in FIG. 8, the first amplifier 61 constitutes a non-inverting amplifier circuit that outputs the received wave i without inverting it, and in the peak hold circuit 37D shown in FIG. 11, the first amplifier 61 constitutes an inverting amplifier circuit that inverts and outputs the received wave i. In the peak hold circuit 37D, the received wave i is input to the inverting input terminal of the first amplifier 61, and the non-inverting input terminal of the first amplifier 61 is electrically connected to the intermediate potential 93. As with the peak hold circuit 37B, the peak hold circuit 37D can accurately hold the minimum value of the received wave i even when the received wave i is an ultrasonic wave with a frequency of several hundred kHz to several MHz (for example, 100 kHz to 300 MHz).

The control unit 35 (Figure 1) may output a signal (hereinafter also referred to as amplitude adjustment signal p) for adjusting the amplitude of the ultrasonic wave e according to the peak hold value h. Since the amplitude of the received signal f is approximately proportional to the amplitude of the ultrasonic wave e, the amplitude of the received signal f can be controlled by varying the amplitude of the ultrasonic wave e. If the amplitude of the received signal f can be controlled, the amplitude of the received wave i, which is the waveform after amplification of the received signal f, can also be controlled.

For example, the control unit 35 compares the peak hold value h with a predetermined target amplitude value. When the control unit 35 detects that the peak hold value h is lower than the target amplitude value, it outputs an amplitude adjustment signal p that increases the amplitude of the ultrasonic wave e. When the control unit 35 detects that the peak hold value h is higher than the target amplitude value, it outputs an amplitude adjustment signal p that decreases the amplitude of the ultrasonic wave e. The control unit 35 controls the amplitude of the received wave i to a constant value by performing feedback control that outputs an amplitude adjustment signal p according to the peak hold value h output from the peak hold circuit 37.

The control unit 35 adjusts the amplitude of the ultrasonic wave e that changes with the change in the amplitude of the electrical signal d by, for example, adjusting the amplitude of the electrical signal d (e.g., one or more pulse signals that excite an ultrasonic transducer) transmitted from the transmission unit 31 using an amplitude adjustment signal p. The control unit 35 may also adjust the amplitude of the electrical signal d that changes with the change in the reference voltage (e.g., power supply voltage, etc.) supplied to the transmission unit 31 using the amplitude adjustment signal p. This adjusts the amplitude of the ultrasonic wave e.

Figure 12 is a diagram showing an example of the configuration of a transmission unit. The transmission unit 31A is an example of the transmission unit 31 described above. The transmission unit 31A has a transmission driver 120 to which the power supply voltage VDD generated by the power supply circuit 200 is input. The transmission driver 120 is, for example, an integrated circuit.

The transmission timing signal c (e.g., a pulse input signal including multiple square waves) supplied from the control unit 35 is input to the transmission driver 120. The transmission driver 120 outputs an electrical signal d that has a higher amplitude than the transmission timing signal c and the same number of pulses as the transmission timing signal c. The transmission driver 120 changes the amplitude of the electrical signal d according to the power supply voltage VDD. The transmission driver 120 increases the amplitude of the electrical signal d as the power supply voltage VDD increases, and decreases the amplitude of the electrical signal d as the power supply voltage VDD decreases.

The electrical signal d is input to the ultrasonic transducer 11a or 11b, which generates an ultrasonic wave e. The amplitude of the ultrasonic wave e is approximately proportional to the amplitude of the electrical signal d. Therefore, the control unit 35 can control the amplitude of the received signal f and the received wave i to the desired target value by adjusting the power supply voltage VDD generated by the power supply circuit 200 using the amplitude adjustment signal p.

Figure 13 is a diagram showing an example of the configuration of a power supply circuit that generates a variable power supply voltage. The power supply circuit 200A is an example of the power supply circuit 200 described above. The power supply circuit 200A is used as a power supply that determines the amplitude of the electrical signal d (and thus the amplitude of the ultrasonic wave e) in the transmission unit 31. A power supply voltage B generated by a separate power supply (not shown) is supplied to the power supply circuit 200A. The power supply circuit 200A generates a variable power supply voltage VDD, which is lower than the power supply voltage B, from the power supply voltage B.

The power supply circuit 200A divides the power supply voltage VDD using resistors 201 and 202, and feeds back the divided voltage value (feedback voltage q) to an amplifier 203, which is composed of, for example, an operational amplifier. The amplifier 203 controls the power supply voltage VDD so that the input amplitude adjustment voltage p1 and the feedback voltage q become the same. The amplitude adjustment voltage p1 is an example of the above-mentioned amplitude adjustment signal p supplied from the control unit 35.

The output terminal of amplifier 203 is connected to the emitter of transistor 204, which has a common base. Resistor 205 is connected between the power supply of power supply voltage B and the collector of transistor 204. The magnitude of the collector current flowing through resistor 205 is controlled by the output signal of amplifier 203, thereby changing the power supply voltage VDD.

The output stage of the power supply circuit 200A has a push-pull circuit formed by a PNP bipolar transistor 206 and an NPN bipolar transistor 207. The push-pull circuit changes the power supply voltage VDD by discharging or absorbing the output current at the output stage. The common base and the push-pull circuit allow the power supply circuit 200A to quickly control the rise and fall of the power supply voltage VDD.

The power supply circuit 200A is constructed using versatile electronic components such as operational amplifiers, transistors, resistors, and capacitors, which reduces the risk of component obsolescence. In addition, since it can be easily constructed using versatile small components, the circuit can be made smaller and less expensive. Furthermore, the amplitude adjustment voltage p1 can be easily generated by a DAC built into a microcomputer (not shown) that realizes the function of the flow measurement unit 50, for example, and a variable amplitude adjustment voltage p1 can be easily generated to control the power supply voltage VDD. Furthermore, the operational amplifier used in the amplifier 203 can keep the voltage of the control power supply low, eliminating the need to use expensive high power supply voltage types, further improving versatility.

The power supply circuit 200A is used as a power supply that determines the amplitude of the ultrasonic wave e. Since the amplitude of the received signal f is roughly proportional to the amplitude of the ultrasonic wave e, the amplitude of the received signal f can be controlled by varying the amplitude of the ultrasonic wave e. The DAC built into the microcontroller has a resolution of about 10 to 14 bits, allowing fine control of the amplitude adjustment voltage p1.

Although the embodiments have been described above, they are presented as examples, and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

The peak hold circuit is not limited to ultrasonic flow meters, but may also be applied to other devices such as ultrasonic level meters that use ultrasonic waves to measure the height level of a fluid, such as a water level, and ultrasonic thickness gauges that use ultrasonic waves to measure the thickness of an object.

REFERENCE SIGNS LIST 10a, 10b ultrasonic probe 11a, 11b ultrasonic transducer 12a, 12b wedge 31 transmitter 32 receiver 33a, 33b switch 35 controller 37, 37A, 37B, 37X peak hold circuit 38 reception timing detection circuit 40 time measurement unit 50 flow rate measurement unit 61 first amplifier 63 first diode 64 bias element 65 second diode 67 capacitor 69 transistor 70 resistor 72 second amplifier 75 reset circuit 91 power supply 92 ground 100 piping 102 fluid 300 ultrasonic flow meter

Claims (11)

a first amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein an input wave is input to the non-inverting input terminal or the inverting input terminal;
a first diode having an anode electrically connected to the inverting input terminal and a cathode electrically connected to the output terminal;
a second diode having a cathode electrically connected to the cathode of the first diode and to the output terminal;
a capacitor having one end electrically connected to the anode of the second diode and configured to hold a voltage corresponding to the peak value of the input wave. The peak hold circuit according to claim 1, further comprising a bias element disposed between a power source and the anode of the first diode to bias the first diode. a first amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein an input wave is input to the non-inverting input terminal or the inverting input terminal;
a first diode having a cathode electrically connected to the inverting input terminal and an anode electrically connected to the output terminal;
a second diode having an anode electrically connected to the anode of the first diode and the output terminal;
a capacitor having one end electrically connected to the cathode of the second diode and configured to hold a voltage corresponding to the peak value of the input wave. The peak hold circuit of claim 3, further comprising a bias element interposed between ground and the cathode of the first diode to bias the first diode. 5. The peak hold circuit according to claim 2, wherein the bias element is a resistive element. The peak hold circuit according to any one of claims 1 to 4, wherein the second diode has the same forward voltage characteristics as the first diode. The peak hold circuit according to any one of claims 1 to 4, further comprising a reset circuit that resets the voltage of the capacitor. The peak hold circuit according to claim 7, wherein the reset circuit has a transistor whose collector or drain is electrically connected to the one end of the capacitor. The peak hold circuit of claim 8, wherein the transistor is a bipolar transistor with a resistor electrically connected between the emitter and the base. The peak hold circuit according to any one of claims 1 to 4, further comprising a second amplifier having an input terminal electrically connected to the one end of the capacitor. The peak hold circuit according to claim 1 , wherein the input wave is an ultrasonic reception signal;
a flow rate measuring unit that calculates a flow rate of a fluid through which the ultrasonic waves propagate by using a measured time from a point in time when the transmission of the ultrasonic waves starts to a point in time when the input wave crosses a reference level after the input wave crosses a threshold voltage;
a control unit that outputs a signal that adjusts a gain of an amplifier circuit that amplifies the received signal, the threshold voltage, or the amplitude of the ultrasonic wave according to the voltage of the capacitor.

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