JP2024043312A - laminated electronic components - Google Patents

Abstract

[Problem] To provide a laminated electronic component capable of suppressing the occurrence of cracks. [Solution] The laminated electronic component has an interior region having an inner dielectric layer and an inner electrode layer, and an exterior region having an outer dielectric layer and positioned on the outside of the interior region in the lamination direction. The inner dielectric layer has AmBO3 and element M, and the outer dielectric layer has Am'BO3 and element M', where element M is at least one of Mg, Ni, Mn, Al, and Cr, and element M' is at least one of Mg, Ni, Mn, Al, and Cr, and the relationship 0.69<m/m'<0.92 is satisfied. [Selected Figure] Figure 1

Description

The present invention relates to a multilayer electronic component such as a multilayer ceramic capacitor.

As dielectric layers become thinner and smaller, the incidence of cracks in multilayer electronic components such as multilayer ceramic capacitors is increasing. Therefore, for example, in Patent Document 1 listed below, a technique has been developed that can prevent the occurrence of cracks by using a specific component as a sintering aid component of a dielectric layer included in an electronic component.

However, due to an increase in the number of laminated layers due to further improvements in the performance of laminated electronic components, there is a need for a method for preventing cracks using an approach different from the conventional one.

Patent No. 4561922

The present invention was made in view of the above circumstances, and an object of the present invention is to provide a laminated electronic component that can suppress the occurrence of cracks.

As a result of intensive studies on laminated electronic components that can prevent cracks using an approach different from conventional approaches, the present inventors have determined that the composition of the exterior and interior regions in the stacking direction of the element body of the laminated electronic component should be By focusing on A/B and specifying the relationship between them, the inventors have discovered that it is possible to suppress the occurrence of cracks, and have completed the present invention.

That is, the laminated electronic component according to one embodiment of the present invention is
an interior region having inner dielectric layers and inner electrode layers alternately stacked;
A laminated electronic component having an outer dielectric layer and an exterior region located outside along the lamination direction of the interior region,
The inner dielectric layer has A _m BO ₃ and element M,
The outer dielectric layer has A _m' BO ₃ and element M',
The element M is at least one of Mg, Ni, Mn, Al, and Cr,
The element M' is at least one of Mg, Ni, Mn, Al, and Cr,
0.69<m/m'<0.92
satisfy the relationship.

In a laminated electronic component that satisfies the above configuration, the incidence of cracks can be reduced regardless of the number of laminated inner dielectric layers, and especially even if the number of laminated inner dielectric layers increases. , the incidence of cracks can be reduced. The reason for this is not necessarily clear, but in a laminated electronic component that satisfies the above configuration, the thermal contraction behavior (thermal contraction rate) in the interior area and the thermal contraction behavior (thermal contraction rate) in the exterior area are different. It is thought that this is because they can be matched.

The concentration of the element M in the inner dielectric layer is Mc atomic %,
When the concentration of the element M' in the outer dielectric layer is M'c atomic %,
Preferably 0.24<Mc/M'c<0.83, more preferably 0.3<Mc/M'c<0.8, particularly preferably 0.4<Mc/M'c<0.6. Satisfied with the relationship.

By setting Mc/M'c within a specific range, it is possible to reduce the incidence of cracking and improve the performance of high temperature load life. It is believed that the high temperature load life performance is improved by making the concentration Mc of the element M in the inner dielectric layer smaller than the concentration M'c of the element M' in the outer dielectric layer.

Preferably, the relationship 0.7<m/m'<0.9, more preferably 0.7<m/m'<0.8 is satisfied. By setting it within such a range, the crack occurrence rate can be further suppressed, and the high temperature load life performance is further improved.

Preferably, the relationship 0.89≦m<1.41 is satisfied, and the relationship 0.89<m'≦1.41 is satisfied. More preferably, the relationship 0.90≦m≦1.27 is satisfied, and the relationship 1.29≦m'≦1.40 is satisfied.

Preferably, the relationship 0.8≦Mc≦5.0, more preferably 1.0≦Mc≦3.0 is satisfied. When such a relationship exists, the crack occurrence rate can be further suppressed, and the high temperature load life performance is further improved.

The type of _AmBO3 in the inner dielectric layer and the type of _Am'BO3 in the outer dielectric layer may be the same or different, but from the viewpoint _of preventing composition deviation due to interdiffusion, it is preferable that they are of the same type. _In addition, the types of the A element and the B element in _ABO3 are not particularly limited, but the following modes are possible, for example.

For example, the A _m BO ₃ of the inner dielectric layer is represented by (Ba _1-xy Sr _x Ca _y ) _m (Ti _1-z Zr _z ) O ₃ ;
For example, the A _{m '} BO ₃ of the outer dielectric layer is expressed as (Ba _1-x'- y'Sr _{x '} Ca _{y '} ) _{m '} (Ti _1- z'Zr _{z '} )O ₃ .

Further, it is also preferable that the following relationship exists. for example,
0≦x≦1.00,
0≦y≦1.00,
0.90≦x+y≦1.00,
0.90≦z≦1.00,
0≦x'≦1.00,
0≦y'≦1.00,
0.90≦x'+y'≦1.00, and 0.90≦z'≦1.00.

When such a relationship exists, the temperature characteristics of the laminated electronic component are also improved.

FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view taken along line II-II shown in FIG. FIG. 3 is an enlarged cross-sectional view of the inner dielectric layer shown in FIG. 2. FIG.

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the multilayer ceramic capacitor 2 according to this embodiment has an element body 4 having a substantially rectangular parallelepiped shape (substantially hexahedron) and external electrodes 6, 6 formed on both end faces 4a, 4a of the element body 4 that are substantially perpendicular to the X-axis.

The dimensions of the element main body 4 are not particularly limited, and appropriate dimensions may be adopted depending on the application. For example, the length in the X-axis direction can be 0.6 mm to 5.7 mm, the width in the Y-axis direction can be 0.3 mm to 5.0 mm, and the height in the Z-axis direction can be 0.3 mm to 3.0 mm. . Note that in the drawings, the X-axis, Y-axis, and Z-axis are perpendicular to each other.

As shown in FIG. 2, the element body 4 has an interior region 41. As shown in FIG. The interior region 41 has inner dielectric layers 12 and inner electrode layers 14 alternately stacked along the Z-axis. The plurality of inner electrode layers 14 are stacked such that one end of each layer is alternately exposed to the two end surfaces 4a of the element body 4.

In this embodiment, the end portion of the inner electrode layer 14 drawn out to the end surface 4a is referred to as a drawn-out portion 14a. The exposed end of this lead-out portion 14a is electrically connected to the external electrode 6 covering the end surface 4a, and the plurality of inner electrode layers 14 have different polarities alternately along the stacking direction. It's layered. With this configuration, the inner electrode layer 14 and the outer electrode 6 form a capacitor circuit.

The inner dielectric layer 12 has a central portion 12a that contributes to the capacitance of the capacitor circuit, and an end portion 12b that does not contribute to the capacitance of the capacitor circuit. The central portion 12a is sandwiched between inner electrode layers 14 of different polarities, and the end portion 12b is sandwiched between lead portions 14a of the inner electrode layers 14 of the same polarity.

The number of layers of the inner dielectric layer 12 along the Z axis is not particularly limited, and may be, for example, 20 or more, 50 or more, 100 or more, or 200 or more. As the number of laminated layers increases, the capacitance of the capacitor circuit increases. Note that the number of laminated inner electrode layers 14 is determined according to the number of laminated inner dielectric layers 12.

The average thickness of the inner dielectric layer 12 is not particularly limited, but can be, for example, 100 μm or less, 10 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less. As the average thickness of the inner dielectric layer 12 is made thinner, the capacitance of the capacitor circuit can be increased and the capacitor 2 can be made smaller. The average thickness of the inner electrode layer 14 is also not particularly limited, and is determined according to the average thickness of the inner dielectric layer 12.

The external electrodes 6 are each formed to cover one end surface 4a and extend from the end surface 4a to a part of the side surface, and the pair of external electrodes 6 are electrically insulated from each other. This external electrode 6 only needs to have electrical conductivity, and its material and thickness are not particularly limited. Furthermore, the external electrode 6 may be composed of a single layer or a plurality of layers. For example, the external electrode 6 may have a three-layer structure including a baked electrode (sintered electrode), a resin electrode, and a plating layer.

As shown in FIG. 2, the element main body 4 further includes an exterior region 43 that is stacked on at least one outside of the interior region 41 along the stacking direction (Z axis) so as to be integrated with the interior region 41. have In this embodiment, the exterior regions 43 are integrated and stacked on both sides of the interior region 41 along the Z axis. In the present embodiment, the exterior region 43 does not have the inner electrode layer 14 and is composed only of the outer dielectric layer 43a, but may include layers other than the outer dielectric layer, such as a glass component layer, a dummy electrode layer, etc. may have.

The thickness of the outer dielectric layer 43a is equal to or greater than the thickness of the inner dielectric layer 12, preferably larger than the thickness of the inner dielectric layer 12, for example, 5 times or more, or 10 times or more, and generally, It is about 15 to 100 times larger.

In this embodiment, the inner dielectric layer 12 has an inner main component consisting of A _m BO ₃ and an inner sub-component containing at least element M. Further, the outer dielectric layer 43a has an outer main component consisting of A _m' BO ₃ and an outer sub-component including at least the element M'.

A _m BO ₃ as the inner main component and A _m' BO ₃ as the outer main component both mean the composition formula of a perovskite dielectric composition, and m and m' in the composition formula are respectively B It means the ratio of the A site element to the site element (A/B). In this embodiment, m and m' in the composition formula have the following relationship.

That is, the relationship 0.69<m/m'<0.92 is satisfied, preferably 0.7<m/m'<0.9, and more preferably 0.7<m/m'<0.8 is satisfied. Also, the relationship 0.89≦m<1.41 is satisfied, and more preferably 0.90≦m≦1.27 is satisfied. Also, the relationship 0.89<m'≦1.41 is satisfied, and more preferably 1.29≦m'≦1.40 is satisfied.

In this embodiment, the crack occurrence rate can be reduced regardless of the number of inner dielectric layers stacked, and in particular, even if the number of inner dielectric layers stacked is large (for example, 200 or more). The incidence of cracks can be reduced. The reason for this is not necessarily clear, but if the above relational expression is satisfied, the thermal contraction behavior (thermal contraction rate) in the interior area 41 and the thermal contraction behavior (thermal contraction rate) in the exterior area 43 This is thought to be due to the fact that it can be combined with

Note that m or m' can be measured, for example, as shown below. For example, by performing component analysis on a cross section of the inner dielectric layer 12 or the outer dielectric layer 43a shown in FIG. , m or m' can be identified. Further, when performing component analysis etc. with EPMA, an EDS (energy dispersive spectrometer) or a WDS (wavelength dispersive spectrometer) can be used as the X-ray spectrometer.

In this embodiment, the inner main component and the outer main component may be the same or different, but it is preferable that they have a similar main component composition to prevent compositional deviation due to interdiffusion. In addition, the element M contained in the inner minor component and the element M' contained in the outer minor component may be the same or different, but it is preferable that they are the same.

Element M is at least one of Mg, Ni, Mn, Al, and Cr, and similarly, element M' is at least one of Mg, Ni, Mn, Al, and Cr.

When the concentration of element M in the inner dielectric layer 12 is Mc atomic % and the concentration of element M' in the outer dielectric layer 12 is M'c atomic %, it is preferable that the following relationship exists. That is, preferably 0.24<Mc/M'c<0.83, more preferably 0.3<Mc/M'c<0.8, particularly preferably 0.4<Mc/M'c< The relationship of 0.6 is satisfied. Further, the relationship preferably satisfies 0.8≦Mc≦5.0, more preferably 1.0≦Mc≦3.0.

By setting Mc/M'c within a specific range, it is possible to reduce the incidence of cracks and improve the performance of high temperature load life. It is considered that the high temperature load life performance is improved by making the concentration Mc of the element M in the inner dielectric layer 12 smaller than the concentration M'c of the element M' in the outer dielectric layer 43a.

Note that the concentration of element M or element M' is measured, for example, as shown below. For example, when a cross section of the inner dielectric layer 12 or the outer dielectric layer 43a shown in FIG. 2 is observed using a scanning transmission electron microscope (STEM), dielectric particles 21, grain boundaries 23, segregation 25, etc. are observed. Therefore, quantitative analysis of each element is performed on the center of the cross section of the 20 dielectric particles 21 excluding the segregation 25 using the EDS attached to the STEM, and for example, the concentration of element M or M' with respect to 100 atomic % of Zr is determined. By calculating the respective values and calculating the average, Mc or Mc' can be obtained.

In this embodiment, A _m BO ₃ of the inner dielectric layer 12 is preferably represented by (Ba _1-xy Sr _x Ca _y ) _m (Ti _1-Z Zr _Z )O ₃ , and A m BO 3 of the inner dielectric layer 12 is A _m' BO ₃ is preferably represented by (Ba _1-x'-y' Sr _x' Ca _y' ) _m' (Ti _1-Z' Zr _Z' ) O ₃ .

In the above composition formula, the amount of oxygen (O) may deviate slightly from the above stoichiometric composition. Furthermore, the symbols m, x, y, m', x', y', z, and z' in the composition formula all represent the composition molar ratio, and preferably satisfy the following conditions.

That is, preferably 0≦x≦1.00,
0≦y≦1.00,
0.90≦x+y≦1.00,
0.90≦z≦1.00,
0≦x'≦1.00,
0≦y'≦1.00,
0.90≦x'+y'≦1.00, and 0.90≦z'≦1.00.

When such a relationship exists, the temperature characteristics (for example, C0G characteristics) of the multilayer ceramic capacitor 2 are also improved.

The dielectric particles 21 shown in FIG. 3 are sintered particles, and their average particle size, calculated as a circle-equivalent diameter, is preferably 0.05 μm to 2.0 μm, and more preferably 0.1 μm to 1.0 μm. The particle size of the dielectric particles 21 can be measured by observing the cross section of the inner dielectric layer 12 or the outer dielectric layer 43a in at least three fields of view using a scanning electron microscope (SEM) or a scanning transmission electron microscope (STEM), and performing image analysis of the cross-sectional photographs obtained.

The dielectric particles 21 are mainly composed of the main components of the inner dielectric layer 12 or the outer dielectric layer 43a, and some of the subcomponents containing the element M or M' may be partially dissolved in the core shell. It may be structured particles or entirely solid solution particles. The subcomponents of the inner dielectric layer 12 or the outer dielectric layer 43a may be present at the grain boundaries 23, or may be partially concentrated and present as segregation 25 at a part of the grain boundaries 23. In this embodiment, the form in which the subcomponent exists is not particularly limited. Regarding segregation 25, it may exist as a composite oxide phase due to the combination of multiple subcomponents mentioned above or the combination of some elements constituting the main component and subcomponents. .

The subcomponent containing the element M or M' may contain other subcomponent elements other than M or M'. Examples of other subcomponent elements include V, Nb, Mo, Ta, W, rare earth elements, Si, and Zn.

The compositions of the inner dielectric layer 12 and the outer dielectric layer 43 are analyzed using an analysis method such as an electron beam microanalyzer (EPMA), X-ray fluorescence analysis (XRF), or inductively coupled plasma emission spectrometry (ICP). This allows identification. Furthermore, in this embodiment, when component analysis or the like is performed using EPMA, an EDS (energy dispersive spectrometer) or a WDS (wavelength dispersive spectrometer) can be used as the X-ray spectrometer.

Next, an example of a method for manufacturing the multilayer ceramic capacitor 2 shown in FIGS. 1 and 2 will be described. The multilayer ceramic capacitor 2 of this embodiment is manufactured by producing a green chip by a printing method or a sheet method using a paste, firing the green chip, and then forming a pair of external electrodes 6 on the obtained element body 4. can.

First, starting materials for the main components constituting the inner dielectric layer 12 and the outer dielectric layer 43 are prepared, and the starting materials are weighed so as to have a desired composition ratio after firing. The starting materials used in this case are oxide powders containing the elements that constitute the main components, or compound powders that become oxides after firing (e.g. carbonates, nitrates, oxalates, hydroxides, organometallic compounds). etc.) can be used.

For example, BaCO ₃ powder, SrCO ₃ powder, CaCO ₃ powder, TiO ₂ powder, and ZrO ₂ powder can be used as starting materials for each element constituting the main component. Further, all of the starting materials as the main components are preferably fine particles, and the average particle size thereof is preferably 0.01 to 1.0 μm.

Next, the starting materials weighed above are wet-mixed using a mixer such as a ball mill, and the resulting mixed powder is dried and then calcined under predetermined conditions. As for the heat treatment conditions for calcination, the holding temperature is preferably 1100° C. to 1300° C., and the holding time is preferably 1 to 4 hours.

The atmosphere during the calcination process is not particularly limited, and may be an air atmosphere, an inert gas atmosphere such as nitrogen, or a reduced pressure or vacuum atmosphere. By performing the heat treatment under the above conditions, a calcined powder of the main component is obtained. It is preferable to appropriately crush, grind, classify, or otherwise process the calcined powder to adjust the average particle size of the calcined powder to about 0.1 μm to 1.0 μm.

Next, a starting material as an auxiliary component is added to the calcined powder obtained above and mixed to obtain a dielectric raw material powder. Note that as the starting material for the subcomponent, an oxide powder or a compound powder that becomes an oxide after firing may be used similarly to the starting material for the main component.

Then, the above dielectric raw material powder is added to an organic vehicle or an aqueous vehicle and kneaded to form a paint, and an inner dielectric paste adjusted to have the composition of the inner dielectric layer 12 after firing; After firing, an outer dielectric paste adjusted to have the composition of the outer dielectric layer 43a is obtained. Here, the organic vehicle is a paint in which a binder is dissolved in an organic solvent.

The binder used in the organic vehicle is not particularly limited, and various binders such as ethyl cellulose and polyvinyl butyral can be used. Further, the organic solvent used in the organic vehicle is not particularly limited, and various organic solvents such as terpineol, butyl carbitol, acetone, and toluene can be used.

On the other hand, an aqueous vehicle is a paint in which a water-soluble binder is dissolved in water. In this case, the water-soluble binder is not particularly limited, and for example, polyvinyl alcohol, cellulose, water-soluble acrylic resin, etc. can be used. Note that the dielectric paste may contain other additives such as a plasticizer and a dispersant in addition to the binder and solvent described above.

In addition to the dielectric paste described above, an inner electrode paste that will constitute the inner electrode layer 14 after firing is also prepared. The paste for the inner electrode is made by kneading the above-mentioned conductive material made of Ni or Ni alloy, or various oxides, organometallic compounds, resinates, etc. that become the above-mentioned Ni or Ni alloy after firing, together with the above-mentioned organic vehicle. It can be prepared by At this time, a ceramic component (preferably having the same composition as the main component) contained in the dielectric paste may be added to the inner electrode paste as a co-material.

In addition, in each of the above-mentioned pastes (dielectric paste and inner electrode paste), the blending ratio of the vehicle to be added is not particularly limited, and a known blending ratio may be adopted. For example, the content of the binder component can be about 1 to 10 parts by weight, and the content of the solvent can be about 10 to 100 parts by weight, relative to 100 parts by weight of the dielectric raw material powder.

Next, the above pastes are used to manufacture green chips that will become the element body 4 after firing. Green chips can be manufactured using various printing methods or various sheet methods.

For example, when manufacturing a green chip using a sheet method, first, an outer dielectric paste is applied onto a carrier film such as a PET film using a doctor blade method or the like to form a sheet, and the outer green sheet is obtained by appropriately drying. Further, the inner dielectric paste is applied onto another carrier film such as a PET film by a doctor blade method or the like to form a sheet, and the inner green sheet is appropriately dried.

An inner electrode paste is applied in a predetermined pattern onto the inner green sheet by various printing methods such as screen printing. A mother laminate is obtained by laminating a plurality of inner green sheets on which patterns of the inner electrode paste are formed and then pressing in the lamination direction. Note that on the upper and lower surfaces of the mother laminate in the stacking direction, outer green sheets on which no inner electrode paste is printed are formed in a single layer or in multiple layers so that outer dielectric layers 43a shown in FIG. 2 are formed respectively. It is laminated in layers. Then, the mother laminate obtained through the above steps is cut by dicing or punching to obtain a plurality of green chips.

Next, the green chip is subjected to a binder removal process. The conditions for the binder removal treatment are such that the temperature increase rate is preferably 5 to 300°C/hour, the holding temperature is preferably 180°C to 900°C, and the temperature holding time is preferably 0.5 to 48 hours. Further, the atmosphere for the binder removal treatment is an atmospheric atmosphere or a reducing atmosphere.

After the binder removal process, the green chips are fired (main firing). Specifically, the atmosphere during firing is preferably a reducing atmosphere, and the atmospheric gas is preferably a humidified mixed gas of nitrogen (N ₂ ) and hydrogen (H ₂ ), for example. The oxygen partial pressure during firing is preferably 1.0 x 10 ^-13 MPa or more, more preferably 1.0 x 10 ^-12 MPa or more, and more preferably 1.0 x 10 ^-11 MPa or more.

Further, the temperature increase rate during firing is preferably set as slow as 100°C/hour or less, and more preferably within the range of 5°C/hour to 50°C/hour. Note that the holding temperature during firing is preferably 1100°C to 1300°C. Further, the holding time during firing is preferably 0.2 hours to 3 hours, more preferably 0.5 hours to 2 hours. Furthermore, in the cooling process after temperature maintenance, the cooling rate is preferably 50°C/hour to 300°C/hour.

The element body 4 is obtained by firing under the above conditions. Note that in this embodiment, it is preferable to perform an annealing treatment (re-oxidation treatment of the dielectric layer) on the element body 4 after firing. In the reoxidation treatment, the holding temperature is preferably 1150°C or lower, more preferably 500°C to 1100°C. The temperature holding time in the reoxidation treatment can be 0 to 20 hours, preferably 6 to 10 hours. Further, the atmosphere during the reoxidation treatment is preferably a nitrogen atmosphere or a humidified nitrogen atmosphere, and the oxygen partial pressure is preferably 1.0×10 ⁻⁹ to 1.0×10 ⁻⁵ MPa.

Note that the binder removal treatment, firing, and reoxidation treatment may be performed continuously or independently. Further, these heat treatment steps (binder removal treatment, firing, and reoxidation treatment) are performed on the mother laminate before cutting, and after the heat treatment step, the mother laminate is cut to obtain a plurality of element bodies 4. You can. Further, the obtained element body 4 may be subjected to end face treatment such as polishing or blasting as appropriate.

Finally, a pair of external electrodes 6 are formed on the ends of the element body 4 obtained by the above manufacturing method. The method for forming the external electrodes 6 is not particularly limited. For example, they may be formed by baking a conductive paste containing glass frit or the like. Alternatively, the external electrodes 6 may be formed as resin electrodes by applying a conductive paste containing a thermosetting resin and curing the resin by heating. The external electrodes 6 can also be formed by other film formation methods such as plating and sputtering.

Note that the external electrode 6 may be a laminated electrode by forming one or more plating layers on the surface of a sintered electrode or a resin electrode. For example, the external electrode 6 can have a laminated structure of a sintered Cu electrode/Ag-Pd resin electrode/Ni plating/Sn plating, and in this case, the base electrode in contact with the element body 4 is a sintered Cu electrode. It is a condensing electrode.

The multilayer ceramic capacitor 2 of this embodiment manufactured by the above method is mounted on a substrate such as a circuit board using solder or a conductive adhesive, and is used in various electronic devices.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. For example, the multilayer electronic component according to the present invention is not limited to a multilayer ceramic capacitor, and may be an LC composite electronic component, etc.

Hereinafter, the present invention will be explained based on more detailed examples, but the present invention is not limited to these examples.

Examples and comparative examples

First, in order to produce calcined powder that is the raw material for the inner dielectric layer 12 shown in FIG. 2, BaCO ₃ powder, SrCO ₃ powder, CaCO ₃ powder, TiO ₂ powder, and ZrO ₂ powder are prepared as starting materials. , and were weighed to obtain the desired composition ratio (composition shown in Table 1A after firing). At this time, the average particle size of the starting materials prepared was 0.03 to 1.0 μm.

Next, the weighed starting materials were wet-mixed in a ball mill for 20 hours and dried appropriately to obtain a mixture of starting materials.

Next, the mixture of starting materials obtained above was calcined at 1250° C. for 2 hours to obtain a calcined powder of starting materials. Note that, after the above-mentioned heat treatment, the calcined powder was wet-pulverized using a ball mill, and then dried.

Next, the starting materials for the sub-components were added to the calcined powder and mixed to obtain the desired composition ratio (the composition after firing shown in Table 1A) to obtain the dielectric raw material powder for the inner dielectric layer 12. The dried dielectric raw material powder was then kneaded with a specified organic vehicle and turned into a paint to obtain the inner dielectric paste.

The outer dielectric paste used to form the outer dielectric layer 43a shown in Figure 2 was also prepared in the same manner as the inner dielectric paste.

On the other hand, the paste for the inner electrode was obtained by kneading 100 parts by weight of Ni powder, 40 parts by weight of a predetermined organic vehicle, and 10 parts by weight of butyl carbitol using three rolls to form a paint.

Next, a green laminate was manufactured by a sheet method using the two types of dielectric pastes and electrode paste prepared above. Specifically, an outer dielectric paste, which will become the outer dielectric layer 43, is applied onto a PET film using a doctor blade method, formed into a sheet, and dried appropriately to obtain an outer green sheet. In addition, an inner dielectric paste, which will become the inner dielectric layer 12, is applied onto another PET film using a doctor blade method, formed into a sheet, and dried as appropriate to obtain an inner green sheet.
An inner electrode paste is applied in a predetermined pattern onto the inner green sheet by screen printing. A mother laminate is obtained by laminating a plurality of inner green sheets on which patterns of the inner electrode paste are formed and then pressing in the lamination direction. Note that on the upper and lower surfaces of the mother laminate in the stacking direction, outer green sheets on which no dielectric paste for inner electrodes is printed are formed in multiple layers so that outer dielectric layers 43a shown in FIG. 2 are formed respectively. Laminate.

Next, the green laminate was cut into a predetermined size to obtain green chips, and the green chips were subjected to binder removal treatment, firing, and reoxidation treatment. The detailed conditions for each of these heat treatment steps were as follows.

The conditions for the binder removal treatment were: temperature increase/decrease rate: 30° C./hour, holding temperature: 260° C., temperature holding time: 8 hours, and atmosphere: air.

The firing conditions were: temperature increase rate: 200°C/hour, holding temperature: 1250°C, temperature holding time: 2 hours, cooling rate: 300°C/hour or more, atmospheric gas: humidified N ₂ + H ₂ mixed gas, oxygen content. Pressure: 1.0×10 ⁻¹² MPa or higher.

The conditions for the annealing treatment are: temperature increase rate: 200°C/hour, holding temperature: 1000°C, holding time: 2 hours, cooling rate: 300°C/hour or more, atmospheric gas: humidified N ₂ gas, oxygen partial pressure: 1 .0×10 ^-8 MPa or higher. Note that in the firing and annealing treatments, a wetter was used to humidify the atmospheric gas.

By carrying out heat treatment under the above conditions, the element body 4 was obtained. Next, the end faces of the obtained element body 4 were polished by sandblasting, and then an In-Ga eutectic alloy was applied as an external electrode, and a capacitor sample having the same shape as the multilayer ceramic capacitor 1 shown in Figure 1 was obtained. The size of the obtained capacitor sample (the size of the element body 4) was 3.2 mm x 1.6 mm x 1.6 mm, the average thickness of the inner dielectric layers 12 was 3.0 μm, the average thickness of the inner electrode layers 14 was 1.0 μm, and the number of inner dielectric layers 12 sandwiched between the inner electrode layers 14 was 200.

The following characteristic evaluations were performed on each of the capacitor samples 1 to 30 obtained above.

Crack Incidence Rate Regarding each of the prepared samples 1 to 30, the appearance of 10,000 samples was observed using a microscope, etc., and the proportion of cracks detected was determined. The crack generation rate was considered good when it was 500 ppm or less, and particularly good when it was 100 ppm or less. The results are shown in Table 1B.

High-temperature load life Capacitor samples 1 to 30 were evaluated for high-temperature load life by maintaining the application of DC voltage under an electric field of 70 V/μm at 200°C and measuring the insulation deterioration time of the capacitor samples. . In this example, the time from the start of voltage application until the insulation resistance drops by one order of magnitude was defined as the life span.

Further, in this example, the above evaluation was performed on 20 capacitor samples, and the mean time to failure (MTTF) calculated by Weibull analysis was defined as the average life of each capacitor sample 1 to 30. Regarding high temperature load life, an average life of 50 hours or more was considered good, and an average life of 100 hours or more was considered particularly good. The results are shown in Table 1B.

Temperature coefficient of capacitance τC
Furthermore, the capacitance temperature coefficient τC (unit: ppm/°C) of capacitor samples 1 to 30 was measured. Specifically, a signal with a frequency of 1 kHz and an input signal level (measurement voltage) of 1 Vrms was input to each capacitor sample at 25°C and 125°C, and the capacitance was measured at each temperature range. The capacitance temperature coefficient was calculated from the capacitance C25 at 25°C and the capacitance C125 at 125°C using the following formula. The results are shown in Table 1B.
τC={(C125-C25)/C25}×(1/(125-25))

The above measurements were performed on 10 samples for each capacitor sample, and the capacitance temperature coefficient of each sample was calculated as the average value. The capacity temperature coefficient was judged to be acceptable if it was within the range of ±40 ppm/°C, good if it was within the range of ±30 ppm/°C, and particularly good if it was within the range of ±20 ppm/°C. The results are shown in Table 1B.

Measurement of principal components (x, y, z, m, x', y', z', m') Laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS) was performed on each of the prepared samples 1 to 30. The inner dielectric layer and the outer dielectric layer were analyzed using , and the molar concentration ratio of the main components constituting each layer was determined. As shown in Table 1A, results similar to the composition ratio at the raw material stage were obtained.

Measurement of Mc and M'c The concentrations of M and M' contained in the inner and outer dielectric layers of the prepared samples 1 to 30 were analyzed using an EDS attached to an STEM. Specifically, the concentrations of M and M' were determined for the cross sections of 20 non-segregated particles when the concentration of Zr was set to 100 at% at the geometric center of each particle cross section, and Mc and M'c were calculated from the arithmetic average of the 20 points. As shown in Table 1A, results similar to the composition ratio at the raw material stage were obtained.

As shown in Samples 13 to 22 of Evaluation Tables 1A and 1B, the composition of the main components in the inner dielectric layer and the outer dielectric layer is 0.69<m/m'<0.92, preferably 0.7. By satisfying the relationship <m/m'<0.9, more preferably 0.7<m/m'<0.8, it is possible to suppress the crack occurrence rate and improve the performance of high temperature load life. It was confirmed that there was further improvement. Furthermore, it was confirmed that the temperature coefficient of capacity was also good within this range.

As shown in samples 1 to 4 and 9 to 12 in Tables 1A and 1B, it has been confirmed that the crack occurrence rate can be suppressed and the high temperature load life performance is further improved when the relationships of 0.89≦m<1.41 and 0.89<m'≦1.41 are satisfied, and more preferably, the relationships of 0.90≦m≦1.27 and 1.29≦m'≦1.40 are satisfied, as shown in Tables 1A and 1B for samples 1 to 4 and 9 to 12. It has also been confirmed that the capacity temperature coefficient is good within these ranges.

As shown in Samples 13 to 22 of Table 1A and Table 1B, preferably 0.24<Mc/M'c<0.83, more preferably 0.3<Mc/M'c<0.8, particularly preferably It was confirmed that by satisfying the relationship of 0.4<Mc/M'c<0.6, the crack occurrence rate could be reduced and the high temperature load life performance would be improved. Furthermore, it was confirmed that the temperature coefficient of capacity was also good within this range.

By increasing the solid solution concentration of element M (Mn, etc.) in the dielectric particles of the outer dielectric layer compared to the dielectric particles of the inner dielectric layer, it is believed that the sinterability of the outer dielectric layer is improved, and it is also easier to match the sintering behavior of the inner and outer dielectric layers, further suppressing cracks. In addition, by making the concentration Mc of element M in the inner dielectric layer smaller than the concentration M' of element M'c in the outer dielectric layer, it is believed that the high temperature load life performance is improved. In other words, it is believed that if a large amount of element M (Mn, etc.) is solid-solved in the inner dielectric layer, the high temperature load life is reduced.

As shown in Samples 23 to 30 of Table 1A and Table 1B, when the relationship preferably satisfies 0.8≦Mc≦5.0, more preferably 1.0≦Mc≦3.0, further cracking occurs. It was confirmed that the occurrence rate could be suppressed and the high temperature load life performance was further improved. Furthermore, it was confirmed that the temperature coefficient of capacity was also good within this range.

As shown in Samples 1 to 12 in Tables 1A and 1B, the following relationships ensure that the temperature coefficient of capacity is good, the crack generation rate can be suppressed, and the high-temperature load life performance is improved. It was confirmed that there was an improvement.
0≦x≦1.00,
0≦y≦1.00,
0.90≦x+y≦1.00,
0.90≦z≦1.00,
0≦x'≦1.00,
0≦y'≦1.00,
0.90≦x'+y'≦1.00, and 0.90≦z'≦1.00.

2... Multilayer ceramic capacitor 4... Element body 4a... End surface 6... External electrode 12... Inner dielectric layer 12a... Center portion 12b... End portion 14... Inner electrode layer 14a... Lead portion 21... Dielectric particle 23... Grain boundary 25... Segregation 41... Interior region 43... Exterior region 43a... Outer dielectric layer

Claims (12)

an interior region having inner dielectric layers and inner electrode layers alternately stacked;
A laminated electronic component having an outer dielectric layer and an exterior region located outside along the lamination direction of the interior region,
The inner dielectric layer has A _{m'BO 3} and an element M,
The outer dielectric layer has A _m' BO ₃ and element M',
The element M is at least one of Mg, Ni, Mn, Al, and Cr,
The element M' is at least one of Mg, Ni, Mn, Al, and Cr,
0.69<m/m'<0.92
Laminated electronic components that satisfy the following relationships. The concentration of the element M in the inner dielectric layer is Mc atomic %,
When the concentration of the element M' in the outer dielectric layer is M'c atomic %,
The laminated electronic component according to claim 1, which satisfies the relationship: 0.24<Mc/M'c<0.83. The laminated electronic component according to claim 1, which satisfies the relationship 0.7<m/m'<0.9. The laminated electronic component according to claim 3, which satisfies the relationship: 0.7<m/m'<0.8. The laminated electronic component according to claim 2, which satisfies the relationship: 0.3<Mc/M'c<0.8. The laminated electronic component according to claim 5, which satisfies the relationship: 0.4<Mc/M'c<0.6. The laminated electronic component according to claim 1, which satisfies the relationship of 0.89≦m<1.41 and the relationship of 0.89<m'≦1.41. The laminated electronic component according to claim 7, which satisfies the relationship of 0.90≦m≦1.27 and the relationship of 1.29≦m'≦1.40. The laminated electronic component according to claim 2, which satisfies the relationship 0.8≦Mc≦5.0. The laminated electronic component according to claim 9, which satisfies the relationship 1.0≦Mc≦3.0. A _m BO ₃ of the inner dielectric layer is represented by (Ba _1-xy Sr _x Ca _y ) _m (Ti _1-Z Zr _Z )O ₃ ,
Claim 1: A _m' BO ₃ of the outer dielectric layer is represented by (Ba _1-x'-y' Sr _x' Ca _y' ) _m' (Ti _1-Z' Zr _Z' ) O ₃ . 10. The laminated electronic component according to any one of 10 to 10. 0≦x≦1.00,
0≦y≦1.00,
0.90≦x+y≦1.00,
0.90≦z≦1.00,
0≦x'≦1.00,
0≦y'≦1.00,
The laminated electronic component according to claim 11, wherein 0.90≦x'+y'≦1.00 and 0.90≦z'≦1.00.

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