[go: up one dir, main page]

JP2024013124A - Semiconductor module and its manufacturing method - Google Patents

Semiconductor module and its manufacturing method Download PDF

Info

Publication number
JP2024013124A
JP2024013124A JP2022115076A JP2022115076A JP2024013124A JP 2024013124 A JP2024013124 A JP 2024013124A JP 2022115076 A JP2022115076 A JP 2022115076A JP 2022115076 A JP2022115076 A JP 2022115076A JP 2024013124 A JP2024013124 A JP 2024013124A
Authority
JP
Japan
Prior art keywords
heat sink
semiconductor
module
sealing material
frame portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022115076A
Other languages
Japanese (ja)
Other versions
JP7694492B2 (en
Inventor
洪波 張
Hongbo Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2022115076A priority Critical patent/JP7694492B2/en
Priority to US18/065,509 priority patent/US20240030085A1/en
Priority to DE102023102229.6A priority patent/DE102023102229B4/en
Priority to CN202310850612.9A priority patent/CN117423667A/en
Publication of JP2024013124A publication Critical patent/JP2024013124A/en
Application granted granted Critical
Publication of JP7694492B2 publication Critical patent/JP7694492B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Figure 2024013124000001

【課題】製造コストを低減する。
【解決手段】フレーム部１の上面に半導体素子５，６が実装されている。フレーム部１の下面にヒートシンク１２が接合されている。ヒートシンク１２の下面に絶縁シート１３が設けられている。封止材１４がフレーム部１、半導体素子５，６、ヒートシンク１２を封止してモジュール本体１５を構成する。ヒートシンク１２の厚みはモジュール本体１５の厚みの５０％以上である。
【選択図】図１

Figure 2024013124000001

[Problem] To reduce manufacturing costs.
Semiconductor elements (5, 6) are mounted on the upper surface of a frame part (1). A heat sink 12 is bonded to the lower surface of the frame portion 1. An insulating sheet 13 is provided on the lower surface of the heat sink 12. The sealing material 14 seals the frame portion 1, the semiconductor elements 5 and 6, and the heat sink 12 to form a module body 15. The thickness of the heat sink 12 is 50% or more of the thickness of the module body 15.
[Selection diagram] Figure 1

Description

本開示は、半導体モジュール及びその製造方法に関する。 The present disclosure relates to a semiconductor module and a method for manufacturing the same.

高放熱性を有する樹脂混合物の絶縁シートを用いたトランスファーモールド型パワーモジュールが家電製品などの幅広い分野で用いられている。フレーム部の上面に半導体素子が実装され、放熱性を向上するためにフレーム部の下面にヒートシンクが設けられる。モジュール内部の電力回路と外部とを絶縁するために絶縁シートが設けられる。 Transfer mold type power modules using insulating sheets made of resin mixtures with high heat dissipation properties are used in a wide range of fields such as home appliances. A semiconductor element is mounted on the upper surface of the frame, and a heat sink is provided on the lower surface of the frame to improve heat dissipation. An insulating sheet is provided to insulate the power circuit inside the module from the outside.

従来、絶縁シートはフレーム部とヒートシンクとの間に配置されていた。しかし、絶縁シートが発熱源である半導体素子に隣接しているため、絶縁シートを高耐熱性にする必要があった。ヒートシンクの下面に絶縁シートを設けた構成も提案されている（例えば、特許文献１参照）が、それだけでは絶縁シートの温度上昇を十分に抑制することはできなかった。 Conventionally, an insulating sheet has been placed between a frame portion and a heat sink. However, since the insulating sheet is adjacent to the semiconductor element, which is a heat source, it was necessary to make the insulating sheet highly heat resistant. A configuration in which an insulating sheet is provided on the lower surface of the heat sink has also been proposed (for example, see Patent Document 1), but this alone has not been able to sufficiently suppress the temperature rise of the insulating sheet.

特開２０１６－０９２１８４号公報Japanese Patent Application Publication No. 2016-092184

絶縁シートを高耐熱性にするためには、フィラーの含有率を調整するか、樹脂材料を変更せざるを得ない。これらの変更により絶縁シートが高価なものになるため、製造コストが上昇するという問題があった。 In order to make an insulating sheet highly heat resistant, it is necessary to adjust the filler content or change the resin material. These changes made the insulating sheet expensive, resulting in an increase in manufacturing costs.

本開示は、上述のような課題を解決するためになされたもので、その目的は製造コストを低減することができる半導体モジュール及びその製造方法を得るものである。 The present disclosure has been made to solve the above-mentioned problems, and its purpose is to obtain a semiconductor module and a method for manufacturing the same that can reduce manufacturing costs.

本開示に係る半導体モジュールは、フレーム部と、前記フレーム部の上面に実装された半導体素子と、前記フレーム部の下面に接合されたヒートシンクと、前記ヒートシンクの下面に設けられた絶縁シートと、前記フレーム部、前記半導体素子、前記ヒートシンクを封止してモジュール本体を構成する封止材とを備え、前記ヒートシンクの厚みは前記モジュール本体の厚みの５０％以上であることを特徴とする。 A semiconductor module according to the present disclosure includes a frame portion, a semiconductor element mounted on an upper surface of the frame portion, a heat sink joined to a lower surface of the frame portion, an insulating sheet provided on a lower surface of the heat sink, and the semiconductor element mounted on the upper surface of the frame portion. The module includes a frame portion, the semiconductor element, and a sealing material that seals the heat sink to form a module body, and the thickness of the heat sink is 50% or more of the thickness of the module body.

本開示に係る半導体モジュールの製造方法は、ヒートシンクの下面に絶縁シートを設ける工程と、前記ヒートシンク及び前記絶縁シートを第１の金型に入れて第１の封止材により封止してモジュール下部を成形する工程と、前記第１の封止材から露出した前記ヒートシンクの上面にフレーム部を載せる工程と、前記フレーム部の上面に半導体素子を実装する工程と、前記モジュール下部、前記フレーム部及び前記半導体素子を第２の金型に入れ、前記フレーム部及び前記半導体素子を第２の封止材により封止してモジュール上部を成形する工程とを備えることを特徴とする。 A method for manufacturing a semiconductor module according to the present disclosure includes a step of providing an insulating sheet on the lower surface of a heat sink, and placing the heat sink and the insulating sheet in a first mold and sealing with a first sealing material to form a lower part of the module. a step of placing a frame portion on the upper surface of the heat sink exposed from the first sealing material; a step of mounting a semiconductor element on the upper surface of the frame portion; a step of molding the module lower part, the frame portion and The method is characterized by including the step of placing the semiconductor element in a second mold, sealing the frame portion and the semiconductor element with a second sealing material, and molding an upper part of the module.

本開示に係る半導体モジュールでは、絶縁シートがヒートシンクの下面に設けられ、ヒートシンクの厚みがモジュール本体の厚みの５０％以上である。絶縁シートを発熱源である半導体素子から十分に離すことで、絶縁シートの熱破壊を抑制することができる。従って、高耐熱性の絶縁シートを必要としないため、製造コストを低減することができる。 In the semiconductor module according to the present disclosure, an insulating sheet is provided on the lower surface of the heat sink, and the thickness of the heat sink is 50% or more of the thickness of the module body. By sufficiently separating the insulating sheet from the semiconductor element, which is a heat source, thermal breakdown of the insulating sheet can be suppressed. Therefore, since a highly heat-resistant insulating sheet is not required, manufacturing costs can be reduced.

本開示に係る半導体モジュールの製造方法では、モジュール下部とモジュール上部を別々にモールド成形する。これにより、両者の樹脂材料とモールド成形条件の個別選択が可能となる。よって、製造プロセスを簡素化できるため、製造コストを低減することができる。 In the method for manufacturing a semiconductor module according to the present disclosure, a lower module portion and an upper module portion are molded separately. This allows individual selection of both resin materials and molding conditions. Therefore, since the manufacturing process can be simplified, manufacturing costs can be reduced.

実施の形態１に係る半導体モジュールを示す断面図である。1 is a cross-sectional view showing a semiconductor module according to Embodiment 1. FIG. 比較例に係る半導体モジュールを示す断面図である。FIG. 3 is a cross-sectional view showing a semiconductor module according to a comparative example. モジュール本体の厚みに対するヒートシンクの厚みの割合と絶縁シートの温度との関係を示す図である。FIG. 6 is a diagram showing the relationship between the ratio of the thickness of the heat sink to the thickness of the module body and the temperature of the insulating sheet. 実施の形態２に係る半導体モジュールを示す断面図である。FIG. 3 is a cross-sectional view showing a semiconductor module according to a second embodiment. 実施の形態２に係る半導体モジュールの製造方法を示す断面図である。7 is a cross-sectional view showing a method for manufacturing a semiconductor module according to a second embodiment. FIG. 実施の形態２に係る半導体モジュールの製造方法を示す断面図である。7 is a cross-sectional view showing a method for manufacturing a semiconductor module according to a second embodiment. FIG. 実施の形態２に係る半導体モジュールの製造方法を示す断面図である。7 is a cross-sectional view showing a method for manufacturing a semiconductor module according to a second embodiment. FIG. 実施の形態２に係る半導体モジュールの製造方法を示す断面図である。7 is a cross-sectional view showing a method for manufacturing a semiconductor module according to a second embodiment. FIG. 実施の形態２に係る半導体モジュールの製造方法を示す断面図である。7 is a cross-sectional view showing a method for manufacturing a semiconductor module according to a second embodiment. FIG.

実施の形態に係る半導体モジュール及びその製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。 A semiconductor module and a method for manufacturing the same according to an embodiment will be described with reference to the drawings. Identical or corresponding components may be given the same reference numerals and repeated descriptions may be omitted.

実施の形態１．
図１は、実施の形態１に係る半導体モジュールを示す断面図である。フレーム部１，２と端子３，４が同じ高さに設けられ、互いに分離している。フレーム部１の上面に半導体素子５，６が実装されている。例えば、半導体素子５はＩＧＢＴであり、半導体素子６はダイオードである。フレーム部２の上に制御素子７が実装されている。半導体素子５，６の上面電極が互いにワイヤ８により接続されている。半導体素子６の上面電極がワイヤ９により端子３の一端に接続されている。半導体素子５の制御電極が制御素子７にワイヤ１０により接続されている。制御素子７と端子４の一端がワイヤ１１により接続されている。制御素子７は端子４から入力した信号に応じて半導体素子５を駆動し、半導体素子５，６からの出力信号が端子３から出力される。 Embodiment 1.
FIG. 1 is a cross-sectional view showing a semiconductor module according to a first embodiment. Frame parts 1, 2 and terminals 3, 4 are provided at the same height and are separated from each other. Semiconductor elements 5 and 6 are mounted on the upper surface of the frame portion 1. For example, the semiconductor element 5 is an IGBT, and the semiconductor element 6 is a diode. A control element 7 is mounted on the frame part 2. The upper surface electrodes of the semiconductor elements 5 and 6 are connected to each other by a wire 8. An upper surface electrode of the semiconductor element 6 is connected to one end of the terminal 3 by a wire 9. A control electrode of the semiconductor element 5 is connected to the control element 7 by a wire 10. The control element 7 and one end of the terminal 4 are connected by a wire 11. Control element 7 drives semiconductor element 5 according to a signal input from terminal 4, and output signals from semiconductor elements 5 and 6 are output from terminal 3.

フレーム部１の下面にヒートシンク１２が接合されている。ヒートシンク１２の下面に絶縁シート１３が設けられている。絶縁シート１３はエポキシ樹脂とフィラーの混合物である。フィラーは粒子状のセラミック系添加剤である。 A heat sink 12 is bonded to the lower surface of the frame portion 1. An insulating sheet 13 is provided on the lower surface of the heat sink 12. The insulating sheet 13 is a mixture of epoxy resin and filler. Fillers are particulate ceramic additives.

封止材１４がフレーム部１、半導体素子５，６、ヒートシンク１２を封止してモジュール本体１５を構成する。封止材１４はエポキシ樹脂などである。端子３，４の他端がそれぞれモジュール本体１５の側面から突出している。絶縁シート１３の下面はモジュール本体１５の下面で封止材１４から露出している。絶縁シート１３の下面に銅箔などを設けてもよい。モジュール本体１５の下面が放熱面となる。放熱面は外部の放熱フィンとグリス材によって接着される。 The sealing material 14 seals the frame portion 1, the semiconductor elements 5 and 6, and the heat sink 12 to form a module body 15. The sealing material 14 is epoxy resin or the like. The other ends of the terminals 3 and 4 each protrude from the side surface of the module body 15. The lower surface of the insulating sheet 13 is exposed from the sealing material 14 at the lower surface of the module body 15. A copper foil or the like may be provided on the lower surface of the insulating sheet 13. The lower surface of the module body 15 serves as a heat radiation surface. The heat dissipation surface is bonded to external heat dissipation fins using a grease material.

続いて、本実施の形態の効果を比較例と比較して説明する。図２は、比較例に係る半導体モジュールを示す断面図である。比較例では、絶縁シート１６がフレーム部１とヒートシンク１２との間に配置されている。絶縁シート１６が発熱源である半導体素子に隣接しているため、絶縁シート１６が半導体素子５，６の最高温度とほぼ同じレベルの高温に晒される。従って、絶縁シート１６を高耐熱性にする必要があるため、製造コストが上昇する。近年、ＳｉＣデバイスの実用化に伴い、比較例の構造では高い耐熱性を有する絶縁シートが必要となる。しかし、絶縁シート１６の樹脂混合物のガラス転移温度が一般的に１６０～１７０℃であるため、大幅な耐熱性の向上は技術とコスト面で困難である。これに対して、本実施の形態では、絶縁シート１３がヒートシンク１２の下面に設けられているため、絶縁シート１３を発熱源である半導体素子５，６から離すことができる。 Next, the effects of this embodiment will be explained in comparison with a comparative example. FIG. 2 is a cross-sectional view showing a semiconductor module according to a comparative example. In the comparative example, an insulating sheet 16 is placed between the frame portion 1 and the heat sink 12. Since the insulating sheet 16 is adjacent to the semiconductor element, which is a heat source, the insulating sheet 16 is exposed to a high temperature that is approximately the same level as the maximum temperature of the semiconductor elements 5 and 6. Therefore, it is necessary to make the insulating sheet 16 highly heat resistant, which increases manufacturing costs. In recent years, with the practical use of SiC devices, the structure of the comparative example requires an insulating sheet with high heat resistance. However, since the glass transition temperature of the resin mixture of the insulating sheet 16 is generally 160 to 170° C., it is difficult to significantly improve heat resistance in terms of technology and cost. In contrast, in this embodiment, the insulating sheet 13 is provided on the lower surface of the heat sink 12, so that the insulating sheet 13 can be separated from the semiconductor elements 5 and 6, which are heat sources.

比較例では、モジュール下面側の主な放熱経路の熱抵抗の１割がフレーム部１であり、９割が絶縁シート１６である。一方、本実施の形態では、主な放熱経路の熱抵抗の１割がフレーム部１であり、３割がヒートシンク１２であり、６割が絶縁シート１３である。従って、本実施の形態では、主な放熱経路の熱抵抗における絶縁シート１３の占める割合を減らすことができる。 In the comparative example, the frame portion 1 accounts for 10% of the thermal resistance of the main heat dissipation path on the lower surface side of the module, and the insulating sheet 16 accounts for 90%. On the other hand, in this embodiment, 10% of the thermal resistance of the main heat dissipation path is the frame portion 1, 30% is the heat sink 12, and 60% is the insulating sheet 13. Therefore, in this embodiment, the proportion of the insulating sheet 13 in the thermal resistance of the main heat dissipation path can be reduced.

図３は、モジュール本体の厚みに対するヒートシンクの厚みの割合と絶縁シートの温度との関係を示す図である。発熱源である半導体素子５，６と絶縁シート１３の間に存在する各層の材料の熱伝導率と縦方向の厚みにより熱抵抗を試算し、絶縁シート１３の温度を計算した。モジュール本体１５の厚みＢに対するヒートシンク１２の厚みＡの割合Ａ／Ｂが５０％より小さい領域では、ヒートシンク１２の厚みＡが増加するほど絶縁シート１３の温度が顕著に低下する。Ａ／Ｂが５０％以上になると絶縁シート１３の温度低下がだんだん鈍ってくる。Ａ／Ｂが７５％に達すると絶縁シート１３の温度低下が飽和する。 FIG. 3 is a diagram showing the relationship between the ratio of the thickness of the heat sink to the thickness of the module body and the temperature of the insulating sheet. The temperature of the insulating sheet 13 was calculated by calculating the thermal resistance based on the thermal conductivity and longitudinal thickness of the material of each layer existing between the semiconductor elements 5 and 6, which are heat generating sources, and the insulating sheet 13. In a region where the ratio A/B of the thickness A of the heat sink 12 to the thickness B of the module body 15 is smaller than 50%, the temperature of the insulating sheet 13 decreases more markedly as the thickness A of the heat sink 12 increases. When A/B becomes 50% or more, the temperature drop of the insulating sheet 13 gradually slows down. When A/B reaches 75%, the temperature drop of the insulating sheet 13 is saturated.

そこで、本実施の形態では、ヒートシンク１２の厚みＡをモジュール本体１５の厚みＢの５０％以上とし（Ａ／Ｂ≧０．５０）、更に好ましくは７５％以上とする（Ａ／Ｂ≧０．７５）。即ち、絶縁シート１３を発熱源である半導体素子５，６から十分に離すことで、両者の間の伝熱経路の熱抵抗を敢えて高くしている。これにより、絶縁シート１３の周囲温度が低下するため、絶縁シート１３の熱破壊を抑制することができる。従って、高耐熱性の絶縁シートを必要としないため、製造コストを低減することができる。また、より高い動作温度のパワーデバイスを半導体素子５，６として搭載することができる。 Therefore, in this embodiment, the thickness A of the heat sink 12 is set to be 50% or more of the thickness B of the module body 15 (A/B≧0.50), and more preferably 75% or more (A/B≧0. 75). That is, by separating the insulating sheet 13 sufficiently from the semiconductor elements 5 and 6, which are heat sources, the thermal resistance of the heat transfer path between the two is purposely increased. Thereby, the ambient temperature of the insulating sheet 13 decreases, so that thermal breakdown of the insulating sheet 13 can be suppressed. Therefore, since a highly heat-resistant insulating sheet is not required, manufacturing costs can be reduced. Furthermore, power devices with higher operating temperatures can be mounted as the semiconductor elements 5 and 6.

半導体素子５，６からの熱流が熱容量の大きなヒートシンク１２で熱拡散される。この際に過渡的な熱は平坦化されて放熱面から放出される。このように厚いヒートシンク１２が熱流を外部へ放出する前に一旦溜め込むため、ヒートシンク１２の下面に設けられた本実施の形態の絶縁シート１３の周囲温度は、半導体素子５，６の直下に設けられた比較例の絶縁シート１６に比べて２０℃～３０℃程度低くなる。ただし、両者の温度差は動作条件等により異なる。 The heat flow from the semiconductor elements 5 and 6 is thermally diffused by the heat sink 12 having a large heat capacity. At this time, transient heat is flattened and released from the heat radiation surface. Since the thick heat sink 12 temporarily accumulates the heat flow before discharging it to the outside, the ambient temperature of the insulating sheet 13 of this embodiment provided on the lower surface of the heat sink 12 is lower than that of the insulating sheet 13 provided directly below the semiconductor elements 5 and 6. The temperature is about 20° C. to 30° C. lower than that of the insulating sheet 16 of the comparative example. However, the temperature difference between the two varies depending on operating conditions and the like.

また、比較例では、フレーム部１の高さがフレーム部２及び端子３，４よりも低いため、フレーム部１の上方の封止材１４が厚くなる。従って、フレーム部１に実装された半導体素子５，６からモジュール上面までの熱抵抗がモジュール下面側の放熱経路の１０倍以上になるため、モジュール上面側はほとんど放熱経路にならない。 Furthermore, in the comparative example, since the height of the frame portion 1 is lower than the frame portion 2 and the terminals 3 and 4, the sealing material 14 above the frame portion 1 is thick. Therefore, the thermal resistance from the semiconductor elements 5 and 6 mounted on the frame portion 1 to the top surface of the module is ten times or more that of the heat radiation path on the bottom side of the module, so that the top surface of the module hardly becomes a heat radiation path.

一方、本実施の形態では、端子３，４とフレーム部１，２が同じ高さである。このため、フレーム部１の上方の封止材１４を薄くして、半導体素子５，６からモジュール上面までの熱抵抗を下げることができる。よって、モジュール全体での放熱性を向上することができる。また、フレーム部１の高さが高くなるため、絶縁シート１３を発熱源である半導体素子５，６から離すことにも有効である。 On the other hand, in this embodiment, the terminals 3 and 4 and the frame parts 1 and 2 are at the same height. Therefore, the sealing material 14 above the frame portion 1 can be made thinner, and the thermal resistance from the semiconductor elements 5 and 6 to the top surface of the module can be lowered. Therefore, the heat dissipation of the entire module can be improved. Furthermore, since the height of the frame portion 1 is increased, it is also effective in separating the insulating sheet 13 from the semiconductor elements 5 and 6, which are heat sources.

また、ヒートシンク１２の材料として、コストと加工性の観点からアルミが用いられる。一方、フレーム部１の材料は銅等である。従って、ヒートシンク１２の熱伝導率はフレーム部１の熱伝導率よりも低い。熱抵抗Ｒ［ｍ２・Ｋ／Ｗ］は断熱材の厚さｄ［ｍ］と熱伝導率λ［Ｗ／（ｍ・Ｋ）］からＲ＝ｄ／λにより求められる。従って、発熱源である半導体素子５，６と絶縁シート１３との間の熱抵抗が大きくなるため、絶縁シート１３の周囲温度を下げることができる。なお、ヒートシンク１２の材料がアルミより低熱伝導率の合金材であることが好ましい。 Furthermore, aluminum is used as the material for the heat sink 12 from the viewpoint of cost and workability. On the other hand, the material of the frame portion 1 is copper or the like. Therefore, the thermal conductivity of the heat sink 12 is lower than that of the frame portion 1. The thermal resistance R [m 2 ·K/W] is determined from the thickness d [m] of the heat insulating material and the thermal conductivity λ [W/(m ·K)] by R=d/λ. Therefore, the thermal resistance between the semiconductor elements 5 and 6, which are heat sources, and the insulating sheet 13 increases, so that the ambient temperature of the insulating sheet 13 can be lowered. Note that it is preferable that the material of the heat sink 12 is an alloy material having a lower thermal conductivity than aluminum.

実施の形態２．
図４は、実施の形態２に係る半導体モジュールを示す断面図である。封止材１４は、フレーム部１の下面側に設けられた第１の封止材１４ａと、フレーム部１の上面側に設けられた第２の封止材１４ｂとを有する。第１の封止材１４ａと第２の封止材１４ｂとの間に接合界面１７が存在する。接合界面１７を介して第１の封止材１４ａと第２の封止材１４ｂは直接的に接合されている。接合界面１７は目視又は分析により確認できる。第１の封止材１４ａと第２の封止材１４ｂは同じ材料でもよいし、異なる材料でもよい。 Embodiment 2.
FIG. 4 is a cross-sectional view showing a semiconductor module according to the second embodiment. The sealing material 14 includes a first sealing material 14 a provided on the lower surface side of the frame portion 1 and a second sealing material 14 b provided on the upper surface side of the frame portion 1 . A bonding interface 17 exists between the first sealing material 14a and the second sealing material 14b. The first sealing material 14a and the second sealing material 14b are directly bonded via the bonding interface 17. The bonding interface 17 can be confirmed visually or by analysis. The first sealing material 14a and the second sealing material 14b may be made of the same material or different materials.

第１の封止材１４ａはヒートシンク１２及び絶縁シート１３の側面を覆っている。ヒートシンク１２の上面は第１の封止材１４ａから露出し、第１の封止材１４ａの上面と面一である。第２の封止材１４ｂは、フレーム部１，２及び端子３，４の上面及び側面、半導体素子５，６、制御素子７、ワイヤ８～１１を覆っている。第２の封止材１４ｂの下面はフレーム部１，２及び端子３，４の下面と面一である。フレーム部１の下面は第２の封止材１４ｂから露出してヒートシンク１２の上面に接している。 The first sealing material 14a covers the sides of the heat sink 12 and the insulating sheet 13. The upper surface of the heat sink 12 is exposed from the first sealing material 14a and is flush with the upper surface of the first sealing material 14a. The second sealing material 14b covers the upper and side surfaces of the frame parts 1 and 2, the terminals 3 and 4, the semiconductor elements 5 and 6, the control element 7, and the wires 8 to 11. The lower surface of the second sealing material 14b is flush with the lower surfaces of the frame parts 1 and 2 and the terminals 3 and 4. The lower surface of the frame portion 1 is exposed from the second sealing material 14b and is in contact with the upper surface of the heat sink 12.

また、ヒートシンク１２の断面は、絶縁シート１３の側の下辺がフレーム部１の側の上辺よりも長い台形である。従って、熱源である半導体素子５，６から熱を受けるヒートシンク１２の上面の面積が、外部の放熱フィンに熱を放出するヒートシンク１２の下面の面積よりも小さい。これにより、半導体素子５，６と絶縁シート１３との間の熱抵抗を更に大きくすることができ、絶縁シート１３の周囲温度の上昇を更に抑制することができる。また、ヒートシンク１２の全体に熱拡散ができるため、ヒートシンク１２を小型化できる。その他の構成は実施の形態１と同様である。 Further, the cross section of the heat sink 12 is a trapezoid in which the lower side on the insulating sheet 13 side is longer than the upper side on the frame portion 1 side. Therefore, the area of the upper surface of the heat sink 12 that receives heat from the semiconductor elements 5 and 6, which are heat sources, is smaller than the area of the lower surface of the heat sink 12 that radiates heat to the external radiation fins. Thereby, the thermal resistance between the semiconductor elements 5 and 6 and the insulating sheet 13 can be further increased, and the rise in the ambient temperature of the insulating sheet 13 can be further suppressed. Furthermore, since heat can be diffused throughout the heat sink 12, the heat sink 12 can be made smaller. The other configurations are the same as in the first embodiment.

図５から図９は、実施の形態２に係る半導体モジュールの製造方法を示す断面図である。まず、図５に示すように、ヒートシンク１２の下面に絶縁シート１３を設ける。ヒートシンク１２及び絶縁シート１３を第１の金型１８に入れる。次に、図６に示すように、第１の金型１８に第１の封止材１４ａを注入して、ヒートシンク１２及び絶縁シート１３を第１の封止材１４ａにより封止してモジュール下部１５ａを成形する。図７に示すように、モジュール下部１５ａの上面は平坦であり、第１の封止材１４ａの上面とヒートシンク１２の上面が面一になっている。 5 to 9 are cross-sectional views showing a method for manufacturing a semiconductor module according to the second embodiment. First, as shown in FIG. 5, an insulating sheet 13 is provided on the lower surface of the heat sink 12. The heat sink 12 and the insulating sheet 13 are placed in the first mold 18. Next, as shown in FIG. 6, the first sealing material 14a is injected into the first mold 18, and the heat sink 12 and the insulating sheet 13 are sealed with the first sealing material 14a, and the lower part of the module is formed. 15a is formed. As shown in FIG. 7, the upper surface of the module lower part 15a is flat, and the upper surface of the first sealing material 14a and the upper surface of the heat sink 12 are flush with each other.

次に、図８に示すように、モジュール下部１５ａの上面にフレーム部１，２と端子３，４を同じ高さで載せる。特に、第１の封止材１４ａから露出したヒートシンク１２の上面にフレーム部１を載せる。フレーム部１の上面に半導体素子５，６を実装する。半導体素子５，６を端子３，４にワイヤ接続する。モジュール下部１５ａ、フレーム部１，２、端子３，４の一部及び半導体素子５，６を第２の金型１９に入れる。 Next, as shown in FIG. 8, the frame parts 1 and 2 and the terminals 3 and 4 are placed on the upper surface of the module lower part 15a at the same height. In particular, the frame portion 1 is placed on the upper surface of the heat sink 12 exposed from the first sealing material 14a. Semiconductor elements 5 and 6 are mounted on the upper surface of the frame portion 1. Semiconductor elements 5 and 6 are connected to terminals 3 and 4 by wires. The module lower part 15a, the frame parts 1 and 2, parts of the terminals 3 and 4, and the semiconductor elements 5 and 6 are placed in a second mold 19.

次に、図９に示すように、第２の金型１９に第２の封止材１４ｂを注入して、フレーム部１，２及び半導体素子５，６を第２の封止材１４ｂにより封止してモジュール上部１５ｂを成形する。以上の工程により本実施の形態に係る半導体モジュールが製造される。 Next, as shown in FIG. 9, the second sealing material 14b is injected into the second mold 19, and the frame parts 1 and 2 and the semiconductor elements 5 and 6 are sealed with the second sealing material 14b. Then, the module upper part 15b is formed. Through the above steps, the semiconductor module according to this embodiment is manufactured.

従来は、フレーム部にチップを実装し、ワイヤをボンディングした後に一括してモールド成形を行っていた。モールド成形時の樹脂硬化の温度と圧力により、絶縁シートをフレーム部と接着していた。 Conventionally, chips were mounted on the frame, wires were bonded, and then molding was performed all at once. The insulating sheet was bonded to the frame part by the temperature and pressure of the resin curing during molding.

これに対して、本実施の形態では、モジュール下部１５ａとモジュール上部１５ｂを別々にモールド成形する。従って、第１の封止材１４ａと第２の封止材１４ｂの樹脂材料又はモールド成形条件が互いに異なっていてもよい。これにより、両者の樹脂材料とモールド成形条件の個別選択が可能となる。よって、製造プロセスを簡素化できるため、製造コストを低減することができる。また、それぞれの成形工程に最適化したプロセス設計が可能となり、製造品質が向上する。 In contrast, in this embodiment, the module lower part 15a and the module upper part 15b are molded separately. Therefore, the resin materials or molding conditions of the first sealing material 14a and the second sealing material 14b may be different from each other. This allows individual selection of both resin materials and molding conditions. Therefore, since the manufacturing process can be simplified, manufacturing costs can be reduced. In addition, it becomes possible to design a process that is optimized for each molding process, improving manufacturing quality.

また、モジュール下部１５ａの上面が平坦であることが好ましい。これにより、モジュール下部１５ａの上面にフレーム部１，２と端子３，４を同じ高さで載せることができる。また、実施の形態１と同様に、ヒートシンク１２の厚みはモジュール下部１５ａとモジュール上部１５ｂの合計厚みの５０％以上であるが、７５％以上であることが好ましい。これにより実施の形態１と同様の効果を得ることができる。また、本実施の形態の製造方法は、実施の形態１のようにヒートシンク１２の断面が長方形の場合にも同様に適用できる。 Further, it is preferable that the upper surface of the module lower part 15a is flat. Thereby, the frame parts 1 and 2 and the terminals 3 and 4 can be placed at the same height on the upper surface of the module lower part 15a. Further, as in the first embodiment, the thickness of the heat sink 12 is 50% or more of the total thickness of the module lower part 15a and module upper part 15b, but preferably 75% or more. As a result, the same effects as in the first embodiment can be obtained. Further, the manufacturing method of this embodiment can be similarly applied to a case where the heat sink 12 has a rectangular cross section as in the first embodiment.

なお、半導体素子５，６は、珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成された半導体チップは、耐電圧性及び許容電流密度が高いため、小型化できる。この小型化された半導体チップを用いることで、この半導体チップを組み込んだ半導体装置も小型化・高集積化できる。また、半導体チップの耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体装置を更に小型化できる。また、半導体チップの電力損失が低く高効率であるため、半導体装置を高効率化できる。 Note that the semiconductor elements 5 and 6 are not limited to those formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon. The wide bandgap semiconductor is, for example, silicon carbide, gallium nitride based material, or diamond. A semiconductor chip formed using such a wide bandgap semiconductor has high voltage resistance and allowable current density, so it can be miniaturized. By using this miniaturized semiconductor chip, a semiconductor device incorporating this semiconductor chip can also be miniaturized and highly integrated. Furthermore, since the semiconductor chip has high heat resistance, the radiation fins of the heat sink can be miniaturized, and the water cooling section can be air-cooled, so the semiconductor device can be further miniaturized. Furthermore, since the semiconductor chip has low power loss and high efficiency, the semiconductor device can be made highly efficient.

以上、好ましい実施の形態等について詳説したが、上述した実施の形態等に制限されることはなく、特許請求の範囲に記載された範囲を逸脱することなく、上述した実施の形態等に種々の変形及び置換を加えることができる。以下、本開示の諸態様を付記としてまとめて記載する。 Although the preferred embodiments have been described in detail above, they are not limited to the embodiments described above, and various modifications may be made to the embodiments described above without departing from the scope of the claims. Variations and substitutions can be made. Hereinafter, various aspects of the present disclosure will be collectively described as supplementary notes.

（付記１）
フレーム部と、
前記フレーム部の上面に実装された半導体素子と、
前記フレーム部の下面に接合されたヒートシンクと、
前記ヒートシンクの下面に設けられた絶縁シートと、
前記フレーム部、前記半導体素子、前記ヒートシンクを封止してモジュール本体を構成する封止材とを備え、
前記ヒートシンクの厚みは前記モジュール本体の厚みの５０％以上であることを特徴とする半導体モジュール。
（付記２）
前記ヒートシンクの厚みは前記モジュール本体の厚みの７５％以上であることを特徴とする付記１に記載の半導体モジュール。
（付記３）
前記封止材は、前記フレーム部の下面側に設けられた第１の封止材と、前記フレーム部の上面側に設けられた第２の封止材とを有し、
前記第１の封止材と前記第２の封止材との間に接合界面が存在することを特徴とする付記１又は２に記載の半導体モジュール。
（付記４）
一端が前記半導体素子に接続され、他端が前記封止材の側面から突出した端子を更に備え、
前記端子と前記フレーム部は同じ高さであることを特徴とする付記１～３の何れかに記載の半導体モジュール。
（付記５）
前記ヒートシンクの断面は、前記絶縁シートの側の下辺が前記フレーム部の側の上辺よりも長い台形であることを特徴とする付記１～４の何れかに記載の半導体モジュール。
（付記６）
前記ヒートシンクの熱伝導率は前記フレーム部の熱伝導率よりも低いことを特徴とする付記１～５の何れかに記載の半導体モジュール。
（付記７）
前記絶縁シートは樹脂とフィラーの混合物であることを特徴とする付記１～６の何れかに記載の半導体モジュール。
（付記８）
前記半導体素子はワイドバンドギャップ半導体によって形成されていることを特徴とする付記１～７の何れかに記載の半導体モジュール。
（付記９）
ヒートシンクの下面に絶縁シートを設ける工程と、
前記ヒートシンク及び前記絶縁シートを第１の金型に入れて第１の封止材により封止してモジュール下部を成形する工程と、
前記第１の封止材から露出した前記ヒートシンクの上面にフレーム部を載せる工程と、
前記フレーム部の上面に半導体素子を実装する工程と、
前記モジュール下部、前記フレーム部及び前記半導体素子を第２の金型に入れ、前記フレーム部及び前記半導体素子を第２の封止材により封止してモジュール上部を成形する工程とを備えることを特徴とする半導体モジュールの製造方法。
（付記１０）
前記第１の封止材と前記第２の封止材の樹脂材料又はモールド成形条件が互いに異なることを特徴とする付記９に記載の半導体モジュールの製造方法。
（付記１１）
前記モジュール下部の上面が平坦であり、
前記モジュール下部の上面に前記フレーム部と端子を載せ、
前記端子を前記半導体素子にワイヤ接続し、前記第２の封止材により封止することを特徴とする付記９又は１０に記載の半導体モジュールの製造方法。
（付記１２）
前記ヒートシンクの厚みは前記モジュール下部と前記モジュール上部の合計厚みの５０％以上であることを特徴とする付記９～１１の何れかに記載の半導体モジュールの製造方法。
（付記１３）
前記ヒートシンクの厚みは前記モジュール下部と前記モジュール上部の合計厚みの７５％以上であることを特徴とする付記９～１１の何れかに記載の半導体モジュールの製造方法。 (Additional note 1)
A frame part,
a semiconductor element mounted on the upper surface of the frame portion;
a heat sink joined to the lower surface of the frame portion;
an insulating sheet provided on the lower surface of the heat sink;
a sealing material that seals the frame portion, the semiconductor element, and the heat sink to form a module body;
A semiconductor module, wherein the thickness of the heat sink is 50% or more of the thickness of the module main body.
(Additional note 2)
The semiconductor module according to appendix 1, wherein the thickness of the heat sink is 75% or more of the thickness of the module main body.
(Additional note 3)
The sealing material includes a first sealing material provided on the lower surface side of the frame portion, and a second sealing material provided on the upper surface side of the frame portion,
The semiconductor module according to appendix 1 or 2, wherein a bonding interface exists between the first encapsulant and the second encapsulant.
(Additional note 4)
further comprising a terminal having one end connected to the semiconductor element and the other end protruding from a side surface of the sealing material,
4. The semiconductor module according to any one of appendices 1 to 3, wherein the terminal and the frame portion have the same height.
(Appendix 5)
5. The semiconductor module according to any one of appendices 1 to 4, wherein the heat sink has a trapezoidal cross section in which a lower side on the insulating sheet side is longer than an upper side on the frame portion side.
(Appendix 6)
6. The semiconductor module according to any one of appendices 1 to 5, wherein the heat sink has a thermal conductivity lower than that of the frame portion.
(Appendix 7)
7. The semiconductor module according to any one of appendices 1 to 6, wherein the insulating sheet is a mixture of resin and filler.
(Appendix 8)
8. The semiconductor module according to any one of appendices 1 to 7, wherein the semiconductor element is formed of a wide bandgap semiconductor.
(Appendix 9)
A step of providing an insulating sheet on the bottom surface of the heat sink,
placing the heat sink and the insulating sheet in a first mold and sealing with a first sealing material to mold a lower part of the module;
placing a frame portion on the upper surface of the heat sink exposed from the first sealing material;
a step of mounting a semiconductor element on the upper surface of the frame portion;
the step of placing the module lower part, the frame part, and the semiconductor element in a second mold, sealing the frame part and the semiconductor element with a second sealing material, and molding the module upper part. Features: A method for manufacturing semiconductor modules.
(Appendix 10)
9. The method of manufacturing a semiconductor module according to appendix 9, wherein the first encapsulant and the second encapsulant are different in resin material or molding conditions.
(Appendix 11)
the upper surface of the lower part of the module is flat;
Place the frame part and the terminal on the upper surface of the lower part of the module,
11. The method of manufacturing a semiconductor module according to appendix 9 or 10, characterized in that the terminal is connected to the semiconductor element by wire and sealed with the second sealing material.
(Appendix 12)
The method for manufacturing a semiconductor module according to any one of appendices 9 to 11, wherein the thickness of the heat sink is 50% or more of the total thickness of the module lower part and the module upper part.
(Appendix 13)
The method for manufacturing a semiconductor module according to any one of appendices 9 to 11, wherein the thickness of the heat sink is 75% or more of the total thickness of the lower part of the module and the upper part of the module.

１ フレーム部、３，４ 端子、５，６ 半導体素子、１２ ヒートシンク、１３ 絶縁シート、１４ 封止材、１４ａ 第１の封止材、１４ｂ 第２の封止材、１５ モジュール本体、１５ａ モジュール下部、１５ｂ モジュール上部、１７ 接合界面、１８第１の金型、１９第２の金型 1 frame part, 3, 4 terminal, 5, 6 semiconductor element, 12 heat sink, 13 insulating sheet, 14 sealing material, 14a first sealing material, 14b second sealing material, 15 module main body, 15a module lower part , 15b module upper part, 17 joint interface, 18 first mold, 19 second mold

Claims (13)

フレーム部と、
前記フレーム部の上面に実装された半導体素子と、
前記フレーム部の下面に接合されたヒートシンクと、
前記ヒートシンクの下面に設けられた絶縁シートと、
前記フレーム部、前記半導体素子、前記ヒートシンクを封止してモジュール本体を構成する封止材とを備え、
前記ヒートシンクの厚みは前記モジュール本体の厚みの５０％以上であることを特徴とする半導体モジュール。 A frame part,
a semiconductor element mounted on the upper surface of the frame portion;
a heat sink joined to the lower surface of the frame portion;
an insulating sheet provided on the lower surface of the heat sink;
a sealing material that seals the frame portion, the semiconductor element, and the heat sink to form a module body;
A semiconductor module, wherein the thickness of the heat sink is 50% or more of the thickness of the module main body. 前記ヒートシンクの厚みは前記モジュール本体の厚みの７５％以上であることを特徴とする請求項１に記載の半導体モジュール。 2. The semiconductor module according to claim 1, wherein the thickness of the heat sink is 75% or more of the thickness of the module body. 前記封止材は、前記フレーム部の下面側に設けられた第１の封止材と、前記フレーム部の上面側に設けられた第２の封止材とを有し、
前記第１の封止材と前記第２の封止材との間に接合界面が存在することを特徴とする請求項１又は２に記載の半導体モジュール。 The sealing material includes a first sealing material provided on the lower surface side of the frame portion, and a second sealing material provided on the upper surface side of the frame portion,
3. The semiconductor module according to claim 1, wherein a bonding interface exists between the first encapsulant and the second encapsulant. 一端が前記半導体素子に接続され、他端が前記封止材の側面から突出した端子を更に備え、
前記端子と前記フレーム部は同じ高さであることを特徴とする請求項１又は２に記載の半導体モジュール。 further comprising a terminal having one end connected to the semiconductor element and the other end protruding from a side surface of the sealing material,
3. The semiconductor module according to claim 1, wherein the terminal and the frame portion have the same height. 前記ヒートシンクの断面は、前記絶縁シートの側の下辺が前記フレーム部の側の上辺よりも長い台形であることを特徴とする請求項１又は２に記載の半導体モジュール。 3. The semiconductor module according to claim 1, wherein the cross section of the heat sink has a trapezoidal shape in which a lower side on the side of the insulating sheet is longer than an upper side on the side of the frame part. 前記ヒートシンクの熱伝導率は前記フレーム部の熱伝導率よりも低いことを特徴とする請求項１又は２に記載の半導体モジュール。 3. The semiconductor module according to claim 1, wherein the heat sink has a lower thermal conductivity than the frame portion. 前記絶縁シートは樹脂とフィラーの混合物であることを特徴とする請求項１又は２に記載の半導体モジュール。 3. The semiconductor module according to claim 1, wherein the insulating sheet is a mixture of resin and filler. 前記半導体素子はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項１又は２に記載の半導体モジュール。 3. The semiconductor module according to claim 1, wherein the semiconductor element is formed of a wide bandgap semiconductor. ヒートシンクの下面に絶縁シートを設ける工程と、
前記ヒートシンク及び前記絶縁シートを第１の金型に入れて第１の封止材により封止してモジュール下部を成形する工程と、
前記第１の封止材から露出した前記ヒートシンクの上面にフレーム部を載せる工程と、
前記フレーム部の上面に半導体素子を実装する工程と、
前記モジュール下部、前記フレーム部及び前記半導体素子を第２の金型に入れ、前記フレーム部及び前記半導体素子を第２の封止材により封止してモジュール上部を成形する工程とを備えることを特徴とする半導体モジュールの製造方法。 A step of providing an insulating sheet on the bottom surface of the heat sink,
placing the heat sink and the insulating sheet in a first mold and sealing with a first sealing material to mold a lower part of the module;
placing a frame portion on the upper surface of the heat sink exposed from the first sealing material;
a step of mounting a semiconductor element on the upper surface of the frame portion;
the step of placing the module lower part, the frame part, and the semiconductor element in a second mold, sealing the frame part and the semiconductor element with a second sealing material, and molding the module upper part. Features: A method for manufacturing semiconductor modules. 前記第１の封止材と前記第２の封止材の樹脂材料又はモールド成形条件が互いに異なることを特徴とする請求項９に記載の半導体モジュールの製造方法。 10. The method of manufacturing a semiconductor module according to claim 9, wherein the first encapsulant and the second encapsulant have different resin materials or molding conditions. 前記モジュール下部の上面が平坦であり、
前記モジュール下部の上面に前記フレーム部と端子を載せ、
前記端子を前記半導体素子にワイヤ接続し、前記第２の封止材により封止することを特徴とする請求項９又は１０に記載の半導体モジュールの製造方法。 the upper surface of the lower part of the module is flat;
Place the frame part and the terminal on the upper surface of the lower part of the module,
11. The method of manufacturing a semiconductor module according to claim 9, wherein the terminal is connected to the semiconductor element by wire and sealed with the second sealing material. 前記ヒートシンクの厚みは前記モジュール下部と前記モジュール上部の合計厚みの５０％以上であることを特徴とする請求項９又は１０に記載の半導体モジュールの製造方法。 11. The method of manufacturing a semiconductor module according to claim 9, wherein the thickness of the heat sink is 50% or more of the total thickness of the lower part of the module and the upper part of the module. 前記ヒートシンクの厚みは前記モジュール下部と前記モジュール上部の合計厚みの７５％以上であることを特徴とする請求項９又は１０に記載の半導体モジュールの製造方法。 11. The method of manufacturing a semiconductor module according to claim 9, wherein the thickness of the heat sink is 75% or more of the total thickness of the module lower part and the module upper part.
JP2022115076A 2022-07-19 2022-07-19 Semiconductor module and manufacturing method thereof Active JP7694492B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2022115076A JP7694492B2 (en) 2022-07-19 2022-07-19 Semiconductor module and manufacturing method thereof
US18/065,509 US20240030085A1 (en) 2022-07-19 2022-12-13 Semiconductor module and method of manufacturing the same
DE102023102229.6A DE102023102229B4 (en) 2022-07-19 2023-01-31 semiconductor module
CN202310850612.9A CN117423667A (en) 2022-07-19 2023-07-12 Semiconductor module and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2022115076A JP7694492B2 (en) 2022-07-19 2022-07-19 Semiconductor module and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2024013124A true JP2024013124A (en) 2024-01-31
JP7694492B2 JP7694492B2 (en) 2025-06-18

Family

ID=89429555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022115076A Active JP7694492B2 (en) 2022-07-19 2022-07-19 Semiconductor module and manufacturing method thereof

Country Status (4)

Country Link
US (1) US20240030085A1 (en)
JP (1) JP7694492B2 (en)
CN (1) CN117423667A (en)
DE (1) DE102023102229B4 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495197B1 (en) * 1969-04-28 1974-02-05
US5216283A (en) * 1990-05-03 1993-06-01 Motorola, Inc. Semiconductor device having an insertable heat sink and method for mounting the same
JPH0870069A (en) * 1994-08-30 1996-03-12 Hitachi Ltd Semiconductor device
JPH10163383A (en) * 1996-11-29 1998-06-19 Oki Electric Ind Co Ltd Resin sealed type semiconductor device and its manufacture
JP2013135161A (en) * 2011-12-27 2013-07-08 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
JP2014236028A (en) * 2013-05-31 2014-12-15 三菱電機株式会社 Semiconductor device and semiconductor device manufacturing method
JP2015211178A (en) * 2014-04-29 2015-11-24 三菱電機株式会社 Semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4540884B2 (en) 2001-06-19 2010-09-08 三菱電機株式会社 Semiconductor device
JP6421549B2 (en) 2014-11-04 2018-11-14 トヨタ自動車株式会社 Power module
CN112688461B (en) 2021-01-27 2025-05-23 Abb瑞士股份有限公司 Stator of motor and motor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495197B1 (en) * 1969-04-28 1974-02-05
US5216283A (en) * 1990-05-03 1993-06-01 Motorola, Inc. Semiconductor device having an insertable heat sink and method for mounting the same
JPH0870069A (en) * 1994-08-30 1996-03-12 Hitachi Ltd Semiconductor device
JPH10163383A (en) * 1996-11-29 1998-06-19 Oki Electric Ind Co Ltd Resin sealed type semiconductor device and its manufacture
JP2013135161A (en) * 2011-12-27 2013-07-08 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
JP2014236028A (en) * 2013-05-31 2014-12-15 三菱電機株式会社 Semiconductor device and semiconductor device manufacturing method
JP2015211178A (en) * 2014-04-29 2015-11-24 三菱電機株式会社 Semiconductor device

Also Published As

Publication number Publication date
DE102023102229B4 (en) 2025-01-09
US20240030085A1 (en) 2024-01-25
DE102023102229A1 (en) 2024-01-25
CN117423667A (en) 2024-01-19
JP7694492B2 (en) 2025-06-18

Similar Documents

Publication Publication Date Title
US9171773B2 (en) Semiconductor device
JP5656907B2 (en) Power module
Hinata et al. Full SiC power module with advanced structure and its solar inverter application
JP6139330B2 (en) Power semiconductor device
US11201121B2 (en) Semiconductor device
US20220102249A1 (en) Dual side cooling power module and manufacturing method of the same
WO2016152258A1 (en) Semiconductor device
CN104620373A (en) Semiconductor device
JP5085972B2 (en) Insulating sheet and semiconductor device
WO2020241472A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP5665572B2 (en) Semiconductor device and manufacturing method of semiconductor device
US20220051960A1 (en) Power Semiconductor Module Arrangement and Method for Producing the Same
JP5369163B2 (en) Insulating sheet and semiconductor device
US10566295B2 (en) Semiconductor device
CN113363231B (en) Semiconductor devices
JP7561677B2 (en) Power semiconductor device, method for manufacturing the power semiconductor device, and power conversion device
JP2012209470A (en) Semiconductor device, semiconductor device module, and manufacturing method of the semiconductor device
JP2024013124A (en) Semiconductor module and its manufacturing method
JP2007288044A (en) Semiconductor device
JP2019067976A (en) Semiconductor device
JP2017079217A (en) Power semiconductor device and manufacturing method therefor
JP7570298B2 (en) Semiconductor Device
JP2015167171A (en) semiconductor device
US20230223317A1 (en) Resin-sealed semiconductor device
CN119452556A (en) Power conversion device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20240801

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20250328

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20250408

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250423

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250507

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250520

R150 Certificate of patent or registration of utility model

Ref document number: 7694492

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150