JP2023046669A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device in which electrical characteristics can be improved, and a manufacturing method thereof.SOLUTION: A semiconductor device 1A comprises: a chip 2 that has a first principal surface 3; an n-type first semiconductor region 6 that is formed in the chip 2 to be exposed from the first principal surface 3; a trench 10 that is formed on the first principal surface 3 and has a side wall and a bottom wall; a p-type impurity region 12 that is formed only in a region existing along the bottom wall of the trench 10 in the first semiconductor region 6; and a first polarity electrode 25 (principal surface electrode) that covers the first principal surface 3 and forms a Schottky junction with the first semiconductor region 6.SELECTED DRAWING: Figure 7

Description

The present invention relates to a semiconductor device and its manufacturing method.

US Pat. No. 5,300,000 discloses a semiconductor device including a drift layer, trenches, p-type regions and an anode electrode. A trench is formed in the surface of the drift layer. A p-type region is formed in the drift layer to cover the bottom and sidewalls of the trench. The anode electrode covers the drift layer.

U.S. Patent Application Publication No. 2013/105820

One embodiment provides a semiconductor device capable of improving electrical characteristics and a method of manufacturing the same.

One embodiment comprises a chip having a main surface, a semiconductor region of a first conductivity type formed in the chip so as to be exposed from the main surface, and a trench formed in the main surface and having sidewalls and bottom walls. an impurity region of the second conductivity type formed only in a region along the bottom wall of the trench in the semiconductor region; and a main surface electrode covering the main surface and forming a Schottky junction with the semiconductor region. A semiconductor device comprising:

In one embodiment, a trench having sidewalls and bottom walls is formed by preparing a wafer having a main surface in which a semiconductor region of a first conductivity type is exposed, and removing unnecessary portions of the wafer from the main surface side. on the main surface, and by introducing the second conductivity type impurity only into the bottom wall of the trench, an impurity region of the second conductivity type along only the bottom wall of the trench is formed in the semiconductor region. and forming, on the main surface, a main surface electrode forming a Schottky junction with the semiconductor region.

The above and further objects, features and advantages are made apparent by the embodiments described with reference to the accompanying drawings.

FIG. 1 is a perspective view showing the semiconductor device according to the first embodiment. 2 is a plan view showing the semiconductor device shown in FIG. 1. FIG. 3 is a plan view showing a layout example of the first main surface of the chip shown in FIG. 1. FIG. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. FIG. 6 is an enlarged view of area VI shown in FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 6. FIG. FIG. 8 is a graph showing the sufficiency of the target value of the reverse current IR and the target value of the forward voltage VF by the relationship between the first value a and the second value b. FIG. 9 is a graph showing the sufficiency of the target value of the reverse current IR and the target value of the forward voltage VF by the relationship between the third value c and the fourth value d. 10A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. 1. FIG. FIG. 10B is a cross-sectional view showing a step after the step shown in FIG. 10A. FIG. 10C is a cross-sectional view showing a step after the step shown in FIG. 10B. FIG. 10D is a cross-sectional view showing a step after the step shown in FIG. 10C. FIG. 10E is a cross-sectional view showing a step after the step shown in FIG. 10D. FIG. 10F is a cross-sectional view showing a step after the step shown in FIG. 10E. FIG. 10G is a cross-sectional view showing a step after the step shown in FIG. 10F. FIG. 10H is a cross-sectional view showing a step after the step shown in FIG. 10G. FIG. 10I is a cross-sectional view showing a step after the step shown in FIG. 10H. FIG. 10J is a cross-sectional view showing a step after the step shown in FIG. 10I. FIG. 11 is an internal see-through perspective view showing a package in which the semiconductor device shown in FIG. 1 is mounted. FIG. 12 is a perspective view showing the semiconductor device according to the second embodiment. 13 is a plan view showing the semiconductor device shown in FIG. 12. FIG. 14 is a plan view showing a layout example of the first main surface of the chip shown in FIG. 12. FIG. FIG. 15 is a plan view showing a layout example of the first polarity electrodes and the second polarity electrodes. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 13. FIG. FIG. 17 is a plan view showing a layout example of outer trenches according to a modification. FIG. 18 is a plan view showing a layout example of trenches according to the first modification. FIG. 19 is a plan view showing a layout example of trenches according to the second modification.

Embodiments are described in detail below with reference to the accompanying drawings. The attached drawings are schematic diagrams and are not strictly illustrated, and the scales and the like do not necessarily match. Corresponding structures among the accompanying drawings are given the same reference numerals, and overlapping descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omissions or simplifications apply.

FIG. 1 is a perspective view showing a semiconductor device 1A according to the first embodiment. FIG. 2 is a plan view showing semiconductor device 1A shown in FIG. 3 is a plan view showing a layout example of the first main surface 3 of the chip 2 shown in FIG. 1. FIG. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. FIG. 6 is an enlarged view of area VI shown in FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 6. FIG.

1 to 7, semiconductor device 1A is a semiconductor rectifying device having an SBD (Schottky Barrier Diode). A semiconductor device 1A includes a hexahedral (specifically rectangular parallelepiped) chip 2 . The chip 2 is made of a single crystal of Si (silicon) or a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a higher bandgap than Si. SiC (silicon carbide), GaN (gallium nitride) and C (diamond) are exemplified as wide bandgap semiconductors. Chip 2 consists of a Si chip in this embodiment.

The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. ing. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from above in the normal direction Z (hereinafter simply referred to as "plan view"). The first main surface 3 is a device forming surface. The second main surface 4 is a non-device formation surface. The second main surface 4 may be a ground surface having grinding marks.

The first side surface 5A and the second side surface 5B extend in the first direction X along the first main surface 3 and face the second direction Y intersecting (specifically, perpendicular to) the first direction X. As shown in FIG. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. As shown in FIG. The length of the first to fourth side surfaces 5A to 5D may be 0.5 mm or more and 2 mm or less.

The semiconductor device 1A includes an n-type (first conductivity type) first semiconductor region 6 formed in a surface layer portion of the chip 2 on the first main surface 3 side. The first semiconductor region 6 is formed in a layer extending along the first main surface 3 and exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. That is, the first semiconductor region 6 forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 may have an n-type impurity concentration of 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less. The first semiconductor region 6 may have a thickness of 2 μm or more and 20 μm or less. The first semiconductor region 6 is formed of an n-type epitaxial layer (Si epitaxial layer) in this embodiment.

The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a surface layer portion of the chip 2 on the second main surface 4 side. The second semiconductor region 7 is formed in a layer extending along the second main surface 4 and exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. That is, the second semiconductor region 7 forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 is electrically connected to the first semiconductor region 6 inside the chip 2 .

The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 . The second semiconductor region 7 may have an n-type impurity concentration of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. The second semiconductor region 7 has a thickness exceeding the thickness of the first semiconductor region 6 . The thickness of the second semiconductor region 7 may be 50 μm or more and 800 μm or less. The second semiconductor region 7 is formed of an n-type semiconductor substrate (Si substrate) in this embodiment.

Semiconductor device 1A includes an active region 8 set in first main surface 3 . The active region 8 is the region where the SBD is formed. The active region 8 is set in the inner part (the central part in this embodiment) of the first main surface 3 with a gap from the peripheral edge of the first main surface 3 in plan view. In this form, the active region 8 is set in a square shape having four sides extending along the peripheral edges (first to fourth side surfaces 5A to 5D) of the first main surface 3 in plan view.

Semiconductor device 1</b>A includes an outer region 9 set on first main surface 3 . The outer region 9 is a region where no SBD is formed. The outer region 9 is set at the peripheral portion of the first main surface 3 . In this embodiment, the outer region 9 extends in a strip shape along the periphery of the first main surface 3 in plan view, and is set in a ring shape (specifically, a square ring shape) surrounding the active region 8 .

The semiconductor device 1A includes at least one (a plurality in this embodiment) trenches 10 formed in the first main surface 3 in the active region 8 . The number of trenches 10 is arbitrary, and is adjusted according to the planar area of first main surface 3 (active region 8). The plurality of trenches 10 are arranged in the first direction X at intervals in a plan view, and are each formed in a strip shape extending in the second direction Y. As shown in FIG. That is, the plurality of trenches 10 are arranged in stripes extending in the second direction Y in plan view. The multiple trenches 10 each have one end portion on one side (first side surface 5A side) and the other end portion on the other side (second side surface 5B side) with respect to the second direction Y. As shown in FIG.

The plurality of trenches 10 are formed at intervals from the bottom (second semiconductor region 7) of the first semiconductor region 6 to the first main surface 3 side in a cross-sectional view, and are partitioned in the first semiconductor region 6. Each has a bottom wall. Each of the plurality of trenches 10 may be formed in a tapered shape having an opening width that gradually decreases toward the bottom wall in a cross-sectional view. The plurality of trenches 10 may each be formed in a vertical shape having a substantially constant opening width when viewed in cross section. Bottom wall corners of the plurality of trenches 10 are preferably formed in a curved shape. Moreover, it is preferable that the opening corners of the plurality of trenches 10 are formed in a curved shape.

6 and 7, a plurality of trenches 10 are formed at intervals of a first value a in the first direction X when viewed in cross section. The first value a may be 0.4 μm or more and 1.4 μm or less. Each of the plurality of trenches 10 has a width of a second value b (b≦a) less than or equal to the first value a in the first direction X. As shown in FIG. The second value b may be 0.4 μm or more and 1.2 μm or less. Preferred numerical values for the first value a and the second value b will be described later.

A plurality of trenches 10 each have a predetermined depth D. As shown in FIG. The depth D may be 0.2 μm or more and 0.4 μm or less. The depth D is preferably 0.25 μm or more and 0.35 μm or less. The plurality of trenches 10 may each have an aspect ratio b/D of 1 or more and 5 or less. Aspect ratio b/D is defined by the ratio of said second value b to said depth D. The aspect ratio b/D is preferably greater than one. That is, it is preferable that the plurality of trenches 10 are formed in a laterally long shape extending along the first main surface 3 in a cross-sectional view perpendicular to the extending direction (stripe direction).

The semiconductor device 1A includes at least one (in this embodiment, a plurality of) outer trenches 11 formed in the first main surface 3 so as to partition the active regions 8 in the outer regions 9 . The plurality of outer trenches 11 sandwich the group of the plurality of trenches 10 from both sides in the first direction X. As shown in FIG. The plurality of outer trenches 11 are arranged in the first direction X from the group of the plurality of trenches 10 at intervals in plan view, and are each formed in a strip shape extending in the second direction Y. As shown in FIG.

That is, the plurality of outer trenches 11 are arranged in stripes extending in the second direction Y together with the plurality of trenches 10 in plan view. The multiple outer trenches 11 each have a length in the second direction Y substantially equal to the multiple trenches 10 . The plurality of outer trenches 11 can be regarded as forming the outermost trenches 10 of the plurality of trenches 10 in this form. The plurality of outer trenches 11 have one end portion on one side (first side surface 5A side) and the other end portion on the other side (second side surface 5B side) in the second direction Y, respectively.

The plurality of outer trenches 11 are formed at intervals from the bottom of the first semiconductor region 6 (the second semiconductor region 7 ) to the first main surface 3 side in a cross-sectional view, and the inner walls partitioned in the first semiconductor region 6 . , an outer wall and a bottom wall, respectively. The inner wall of the outer trench 11 is positioned on the active region 8 side. The outer wall of the outer trench 11 is positioned on the outer region 9 side. A bottom wall of the outer trench 11 connects the inner and outer walls.

Each of the plurality of outer trenches 11 may be formed in a tapered shape having an opening width that gradually decreases toward the bottom wall in a cross-sectional view. The plurality of outer trenches 11 may each be formed in a vertical shape having a substantially constant opening width when viewed in cross section. Bottom wall corners of the plurality of outer trenches 11 are preferably formed in a curved shape. Moreover, it is preferable that the opening corners of the plurality of outer trenches 11 are formed in a curved shape.

6 and 7, like the plurality of trenches 10, the plurality of outer trenches 11 are formed at intervals of the first value a in the first direction X from adjacent trenches 10 in cross-sectional view. . Similarly to the plurality of trenches 10, the plurality of outer trenches 11 each have a width of a second value b (b≤a) equal to or less than the first value a. The plurality of outer trenches 11 each have a predetermined depth D, like the plurality of trenches 10 . That is, the plurality of outer trenches 11 each have an aspect ratio b/D.

The semiconductor device 1</b>A includes a plurality of p-type (second conductivity type) impurity regions 12 formed in regions along the bottom walls of the plurality of trenches 10 in the first semiconductor region 6 . The plurality of impurity regions 12 may have a p-type impurity concentration of 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less. The plurality of impurity regions 12 are arranged at intervals in the first direction X in a plan view, following the layout of the plurality of trenches 10, and are formed in strips extending in the second direction Y, respectively. That is, the plurality of impurity regions 12 are arranged in stripes extending in the second direction Y in plan view. The plurality of impurity regions 12 each extend in a strip shape in the second direction Y from one end portion to the other end portion of the corresponding trench 10 .

A plurality of impurity regions 12 are respectively formed only on the bottom walls of the corresponding trenches 10 and not formed on the sidewalls of the trenches 10 . Thereby, the plurality of impurity regions 12 are formed so as to expose the first semiconductor region 6 from the entire side wall of the corresponding trench 10 . Specifically, the plurality of impurity regions 12 are formed at intervals inward from the sidewalls of the corresponding trenches 10 so as to expose the first semiconductor region 6 at least from the bottom wall corners of the corresponding trenches 10 . It is

In this embodiment, the plurality of impurity regions 12 are formed so as to expose the first semiconductor regions 6 respectively from the bottom wall corners and the bottom wall peripheral portions of the corresponding trenches 10 . The plurality of impurity regions 12 are formed spaced apart from the bottom (second semiconductor region 7 ) of the first semiconductor region 6 toward the first main surface 3 in cross-sectional view. As a result, the plurality of impurity regions 12 form pn junctions with the first semiconductor regions 6 .

The form in which the first semiconductor region 6 is exposed from the wall surface of the trench 10 includes the form in which the first semiconductor region 6 is not replaced with a p-type semiconductor region by the p-type impurity introduced to form the impurity region 12. . Therefore, when the first semiconductor region 6 is exposed from the sidewalls, bottom wall corners, and bottom wall peripheral portions of the trench 10, a very small amount (extremely low concentration) of p-type impurity is present on the sidewalls, bottom wall corners, and bottom wall peripheral portions of the trench 10. Including features that diffuse into at least one of the bottom wall perimeters. That is, the first semiconductor region 6 includes an n-type impurity region and a p impurity concentration lower than the n-type impurity concentration of the n-type impurity region in a portion along at least one of the side wall, bottom wall corner and bottom wall peripheral portion of the trench 10 . A p-type impurity region having a type impurity concentration may be included.

Referring to FIG. 7, impurity regions 12 each have a concentration gradient in which the p-type impurity concentration gradually decreases from the inner portion toward the peripheral portion. The plurality of impurity regions 12 specifically include a high-concentration region 13 on the inner side and a low-concentration region 14 on the peripheral side. In FIG. 7, the high concentration regions 13 are indicated by dashed lines. High-concentration region 13 is exposed from the central portion of the bottom wall of trench 10 . Lightly doped region 14 is exposed from the bottom wall periphery of trench 10 at a distance from the sidewalls of trench 10 .

The plurality of impurity regions 12 are formed in regions along the bottom walls of the plurality of trenches 10 at intervals of a third value c (a≦c) equal to or greater than the first value a in the first direction X when viewed in cross section. there is The third value c may be 0.4 μm or more and 1.6 μm or less. A first difference value c−a between the third value c and the first value a is preferably 0 μm or more and 0.6 μm or less. The first difference ca is preferably 0.2 μm or more.

The plurality of impurity regions 12 each have a width of a fourth value d (b≦d) that is equal to or smaller than the second value b in the first direction X. As shown in FIG. The fourth value d may be 0.35 μm or more and 1.2 μm or less. A second difference b−d between the second value b and the fourth value d is preferably 0 μm or more and 0.6 μm or less. The second difference value bd is preferably 0.2 μm or more. The second difference value bd is approximately equal to the first difference value ca.

Semiconductor device 1</b>A includes outer impurity region 15 formed in first semiconductor region 6 so as to partition active region 8 in outer region 9 . The plurality of outer impurity regions 15 may have a p-type impurity concentration of 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less. The outer impurity region 15 preferably has a p-type impurity concentration substantially equal to that of the plurality of impurity regions 12 . The outer impurity region 15 is formed in an annular shape surrounding the active region 8 (the plurality of trenches 10 and the plurality of outer trenches 11) in plan view.

Outer impurity regions 15 specifically include a plurality of first outer impurity regions 16 and a plurality of second outer impurity regions 17 . The plurality of first outer impurity regions 16 are each formed in a strip shape extending along the corresponding outer trench 11 in plan view. The plurality of first outer impurity regions 16 extend along the second direction Y in a strip shape over the entire area between one end and the other end of the corresponding outer trench 11 .

A plurality of first outer impurity regions 16 are formed in regions along the outer wall and the bottom wall of outer trench 11 so as to expose the entire inner wall of corresponding outer trench 11 . More specifically, the plurality of first outer impurity regions 16 extend outward from the inner wall of the outer trench 11 so as to expose the first semiconductor region 6 from the inner wall-side corners of the inner wall and the bottom wall of the corresponding outer trench 11 . They are formed spaced apart from each other on the region 9 side.

In this embodiment, the plurality of first outer impurity regions 16 expose the first semiconductor regions 6 from the inner wall side corners and bottom wall peripheral portions of the bottom walls of the corresponding outer trenches 11 . A plurality of first outer impurity regions 16 are extracted from the outer wall of the corresponding outer trench 11 toward the peripheral portion of the first main surface 3 and exposed from the first main surface 3 . A plurality of first outer impurity regions 16 are formed spaced inwardly from the peripheral edge of first main surface 3 . The plurality of first outer impurity regions 16 are formed spaced apart from the bottom (second semiconductor region 7 ) of the first semiconductor region 6 toward the first main surface 3 in cross-sectional view. As a result, the plurality of first outer impurity regions 16 form pn junctions with the first semiconductor regions 6 .

The plurality of first outer impurity regions 16 are regions along the bottom walls of the outer trenches 11 corresponding to the impurity regions 12 adjacent to each other in a cross-sectional view at intervals of a third value c (a≦c) equal to or greater than the first value a. are formed respectively. Each of the plurality of first outer impurity regions 16 has a width of a fifth value e (d<e) in the first direction X exceeding the fourth value d of the impurity region 12 . The fifth value e exceeds the second value b of the trench 10 (b<e). The fifth value e may be 5 μm or more and 25 μm or less.

The plurality of second outer impurity regions 17 are formed in the first semiconductor region 6 so as to sandwich the group of trenches 10 from both sides in the second direction Y in regions between the plurality of first outer impurity regions 16 . ing. The plurality of second outer impurity regions 17 are formed in strips extending in the first direction X, respectively.

Specifically, one second outer impurity region 17 extends in a strip shape in the first direction X so as to connect one end portions of the plurality of first outer impurity regions 16, cover one end of the outer trench 11 of each. The other second outer impurity region 17 extends in a strip shape in the first direction X so as to connect the other end portions of the plurality of first outer impurity regions 16, and the other end portions of the plurality of trenches 10 and the plurality of outer trenches. 11 are covered, respectively.

The plurality of second outer impurity regions 17 cover the side walls and bottom walls of the plurality of trenches 10 at both end portions of the plurality of trenches 10 and are connected to the plurality of impurity regions 12 . A plurality of second outer impurity regions 17 cover inner walls, outer walls and bottom walls of the plurality of outer trenches 11 at both end portions of the plurality of outer trenches 11 and are connected to the plurality of first outer impurity regions 16 . The plurality of second outer impurity regions 17 form one annular outer impurity region 15 together with the plurality of first outer impurity regions 16 .

The plurality of second outer impurity regions 17 are formed spaced apart from the bottom (second semiconductor region 7 ) of the first semiconductor region 6 toward the first main surface 3 in cross-sectional view. As a result, the outer impurity region 15 forms a pn junction with the first semiconductor region 6 . Each of the plurality of second outer impurity regions 17 has a width of a fifth value e (d<e) exceeding the fourth value d of the impurity region 12 in a cross-sectional view, similarly to the first outer impurity regions 16 .

Semiconductor device 1A includes an insulating film 20 selectively covering first main surface 3 . The insulating film 20 has walls 22 defining contact openings 21 exposing the first main surface 3 on the active region 8 side, and covers the first main surface 3 on the outer region 9 side. Wall portion 22 is formed spaced apart from the plurality of trenches 10 and the plurality of outer trenches 11 on the peripheral edge side of first main surface 3 so as to expose at least a portion of outer impurity region 15 .

The wall portion 22 is positioned directly above the outer impurity region 15 in this embodiment. The wall portion 22 exposes a portion of the outer impurity region 15 (the plurality of second outer impurity regions 17 ) from between the sidewalls of the plurality of trenches 10 , and exposes portions of the outer impurity region from between the outer walls of the plurality of outer trenches 11 . 15 (plurality of first outer impurity regions 16) are partially exposed. Thereby, the contact opening 21 covers a part (outer edge) of the outer impurity region 15 and covers the entire area of the plurality of trenches 10, the entire area of the plurality of outer trenches 11, and a part (inner edge) of the outer impurity region 15. exposing.

In this embodiment, the insulating film 20 has a laminated structure including a first insulating film 23 and a second insulating film 24 laminated in this order from the first main surface 3 side. The insulating film 20 does not necessarily have a laminated structure including the first insulating film 23 and the second insulating film 24 . Insulating film 20 may have, for example, a single-layer structure composed of either one of first insulating film 23 and second insulating film 24 .

The first insulating film 23 is preferably made of the insulating film 20 having a relatively high density. The first insulating film 23 may contain a silicon oxide film. The first insulating film 23 preferably includes an oxide film made of oxide of the chip 2 . The first insulating film 23 may have a thickness of 10 nm or more and 1000 nm or less. The first insulating film 23 preferably has a thickness of 50 nm or more and 500 nm or less.

The second insulating film 24 is preferably made of the insulating film 20 having a density lower than that of the first insulating film 23 . The second insulating film 24 may contain a silicon oxide film having properties different from those of the first insulating film 23 . The second insulating film 24 may include at least one of a PSG (Phosphorus Silicate Glass) film, a BPSG (Boron and Phosphorus Silicate Glass) film, a USG (Undoped Silicate Glass) film, and a TEOS (Tetraethyl orthosilicate) film. good. The second insulating film 24 is made of a PSG film in this embodiment. The second insulating film 24 is thicker than the first insulating film 23 . The second insulating film 24 may have a thickness of 100 nm or more and 1500 nm or less. The second insulating film 24 preferably has a thickness of 500 nm or more and 1000 nm or less.

Semiconductor device 1</b>A includes first polarity electrode 25 (first main surface electrode) formed on first main surface 3 . The first polarity electrode 25 is the anode electrode (Schottky electrode) of the SBD. A first polar electrode 25 covers the first main surface 3 in the active region 8 and forms a Schottky junction with the first semiconductor region 6 . The first polar electrodes 25 extend into the plurality of trenches 10 from the first major surface 3 .

The first polar electrode 25 is electrically connected to the impurity region 12 on the bottom wall of each trench 10 and forms a Schottky junction with the first semiconductor region 6 on the side wall of each trench 10 . The first polar electrode 25 includes in this embodiment a portion forming a Schottky junction with the first semiconductor region 6 at the bottom wall of each trench 10 .

Specifically, the first polar electrode 25 forms a Schottky junction with the first semiconductor region 6 at the bottom wall corner portion and the bottom wall peripheral portion of each trench 10 . That is, even if the first semiconductor region 6 contains a very small amount of p-type impurity in a portion along at least one of the side wall, bottom wall corner, and bottom wall peripheral portion of each trench 10, the first polarity electrode 25 is A Schottky junction is formed with the first semiconductor region 6 at the side wall, bottom wall corner and bottom wall peripheral edge of each trench 10 .

The first polar electrodes 25 are electrically connected to the outer impurity regions 15 at both ends of each trench 10 . The first polar electrodes 25 also extend into the plurality of outer trenches 11 from the first major surface 3 . First polarity electrode 25 is electrically connected to outer impurity region 15 on the outer wall and bottom wall of each outer trench 11 and forms a Schottky junction with first semiconductor region 6 on the inner wall of each outer trench 11 . The first polar electrode 25 comprises in this embodiment a portion forming a Schottky junction with the first semiconductor region 6 at the bottom wall of each outer trench 11 . Specifically, the first polar electrode 25 forms a Schottky junction with the first semiconductor region 6 at the inner corner portion of the bottom wall of each outer trench 11 and the peripheral portion of the bottom wall.

The first polar electrode 25 includes a lead portion 26 that extends from the first main surface 3 through the wall portion 22 and onto the insulating film 20 . The lead portion 26 faces the outer impurity region 15 with the insulating film 20 interposed therebetween. The lead portion 26 may be led out to a region outside the outer impurity region 15 in plan view. The lead-out portion 26 is formed spaced apart from the peripheral edge (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the active region 8 side.

In this embodiment, the first polar electrode 25 has a laminated structure including a first electrode film 27, a second electrode film 28 and a third electrode film 29 laminated in this order from the chip 2 side. The first electrode film 27 is formed in a film shape along the first main surface 3 , the wall surfaces of the plurality of trenches 10 , the wall surfaces of the plurality of outer trenches 11 and the outer surface of the insulating film 20 . The first electrode film 27 defines a recess space in each trench 10 and defines a recess space in each outer trench 11 .

The first electrode film 27 is made of a Schottky barrier electrode film. The first electrode film 27 includes magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu ), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt ) and gold (Au).

The electrode material of the first electrode film 27 is arbitrary as long as a Schottky junction is formed. The first electrode film 27 may be made of an alloy film containing at least one of the metal species. The first electrode film 27 has a single-layer structure made of a Ti film in this embodiment. The first electrode film 27 may have a thickness of 10 nm or more and 100 nm or less. The first electrode film 27 preferably has a thickness of 50 nm or more and 500 nm or less.

The second electrode film 28 is formed in a film shape along the first electrode film 27 . The second electrode film 28 covers the wall surface of each trench 10 in each trench 10 with the first electrode film 27 interposed therebetween, and covers the wall surface of each outer trench 11 in each outer trench 11 with the first electrode film 27 interposed therebetween. covered. The second electrode film 28 defines recess spaces in each trench 10 and defines recess spaces in each outer trench 11 .

The second electrode film 28 is made of a barrier film. The second electrode film 28 is made of a TiN film in this embodiment. The second electrode film 28 is thicker than the first electrode film 27 . The second electrode film 28 may have a thickness of 10 nm or more and 1000 nm or less. The second electrode film 28 may have a thickness of 50 nm or more and 750 nm or less.

The third electrode film 29 is formed in a film shape along the second electrode film 28 . The third electrode film 29 fills back a plurality of recessed spaces partitioned by the second electrode film 28 in each trench 10 and each outer trench 11 . The third electrode film 29 covers the wall surface of each trench 10 with the first electrode film 27 and the second electrode film 28 interposed in each trench 10 , and covers the first electrode film 27 and the second electrode film 27 in each outer trench 11 . The wall surface of each outer trench 11 is covered with a film 28 interposed therebetween.

The third electrode film 29 is made of a Cu-based metal film or an Al-based metal film. The third electrode film 29 is a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, or an AlSiCu alloy film. may include at least one of The third electrode film 29 is made of an AlCu alloy film in this embodiment. The third electrode film 29 is thicker than the second electrode film 28 . The third electrode film 29 may have a thickness of 0.5 μm or more and 10 μm or less. The thickness of the third electrode film 29 is preferably 3 μm or more and 5 μm or less.

Thus, in the active region 8, an SBD structure 30 (Schottky junction) having a first polar electrode 25 as an anode and a first semiconductor region 6 (second semiconductor region 7) as a cathode is formed.

The semiconductor device 1</b>A includes a silicide layer 31 formed in a connection portion with the first polarity electrode 25 in the chip 2 . Specifically, the silicide layer 31 is formed at the connecting portion between the chip 2 and the first electrode film 27 . That is, the silicide layer 31 contains Ti silicide in this form. The silicide layer 31 is formed in a film shape along the first main surface 3 , the wall surfaces of the plurality of trenches 10 and the wall surfaces of the plurality of outer trenches 11 .

Semiconductor device 1</b>A includes upper insulating film 35 covering the peripheral portion of first polarity electrode 25 . The upper insulating film 35 has a single-layer structure made of an inorganic insulating film in this embodiment. The upper insulating film 35 is preferably made of an insulator different from that of the insulating film 20 . Upper insulating film 35 preferably includes at least one of a silicon nitride film and a silicon oxynitride film. The upper insulating film 35 has a single-layer structure made of a silicon nitride film in this embodiment.

The upper insulating film 35 is formed in a film shape along the insulating film 20 and the first polarity electrode 25 and has a pad opening 36 that exposes the central portion of the first polarity electrode 25 . The pad opening 36 is formed in a square shape having four sides parallel to the periphery of the first main surface 3 in this embodiment. The upper insulating film 35 is preferably thicker than the insulating film 20 . The upper insulating film 35 is preferably thinner than the first polar electrode 25 . The upper insulating film 35 may have a thickness of 0.5 μm or more and 5 μm or less. The thickness of the upper insulating film 35 is preferably 1 μm or more and 3 μm or less.

The upper insulating film 35 may have a laminated structure including an organic insulating film laminated on the inorganic insulating film. In this case, the organic insulating film may include at least one of a polyimide film, a polyamide film and a polybenzoxazole film. The thickness of the organic insulating film may be 1 μm or more and 20 μm or less.

Semiconductor device 1</b>A includes second polarity electrode 37 (second main surface electrode) covering second main surface 4 of chip 2 . The second polar electrode 37 is the cathode electrode of the SBD. That is, the semiconductor device 1A includes a vertical type SBD. The second polar electrode 37 covers the entire second main surface 4 and forms an ohmic contact with the second main surface 4 (second semiconductor region 7).

In this embodiment, the second polar electrode 37 has a laminated structure including a Ti film 37a, a Ni film 37b and an Ag film 37c laminated in this order from the second main surface 4 side. The Ti film 37a may have a thickness of 10 nm or more and 500 nm or less. The Ni film 37b may have a thickness of 100 nm or more and 500 nm or less. The Ag film 37c is thicker than the Ni film 37b. The Ag film 37c may have a thickness of 500 nm or more and 1500 nm or less.

As described above, semiconductor device 1A includes chip 2, first semiconductor region 6, trench 10, impurity region 12, and first polar electrode 25 (main surface electrode). Chip 2 has a first main surface 3 . The first semiconductor region 6 is formed within the chip 2 so as to be exposed from the first main surface 3 . Trench 10 is formed in first main surface 3 and has sidewalls and a bottom wall. The impurity region 12 is formed along the bottom wall of the trench 10 within the first semiconductor region 6 so as to expose the entire side wall of the trench 10 . The first polar electrode 25 covers the first main surface 3 and forms a Schottky junction with the first semiconductor region 6 .

According to this structure, it is possible to provide the semiconductor device 1A capable of improving electrical characteristics. Specifically, by adjusting the layout of the trenches 10 and the layout of the impurity regions 12, it is possible to provide the semiconductor device 1A capable of improving the characteristics of the forward voltage VF and the characteristics of the reverse current IR, which are examples of electrical characteristics. . As an example, the characteristics of the forward voltage VF and the characteristics of the reverse current IR can be adjusted by adjusting the first value a, the second value b, the third value c and the fourth value d as shown in FIGS. adjusted.

FIG. 8 is a graph showing the sufficiency of the target value of the reverse current IR and the target value of the forward voltage VF by the relationship between the first value a and the second value b (see FIGS. 6 and 7). The target value of the reverse current IR is defined by the reverse current IR generated in the Schottky junction when a reverse voltage VR of 3V is applied to the Schottky junction in a temperature environment of 125°C. The target value of the reverse current IR is 10 mA or less. The target value of the forward voltage VF is defined by the forward voltage VF generated at the Schottky junction when a forward current IF of 7.5 mA is applied to the Schottky junction under a temperature environment of -40°C. The target value of the forward voltage VF is 300 mV or less.

FIG. 8 shows a plurality of black plotted points and a plurality of white plotted points. A plurality of black plotted points indicate conditions in which the target value of the reverse current IR is satisfied, but the target value of the forward voltage VF is not satisfied. A plurality of white plotted points indicate conditions in which both the target value of the reverse current IR and the target value of the forward voltage VF are satisfied.

Referring to FIG. 8, the characteristics of the forward voltage VF and the characteristics of the reverse current IR tend to improve as the first value a increases and the second value b decreases. Further, the characteristics of the forward voltage VF and the characteristics of the reverse current IR tend to improve as the first value a decreases and the second value b increases.

The first value a is preferably 0.4 μm or more. Also, the second value b is preferably 0.6 μm or more. When these conditions are satisfied, at least the target value of the reverse current IR can be satisfied. It is particularly preferable that the first value a is 0.6 μm or more. In this case, both the target value of the reverse current IR and the target value of the forward voltage VF can be satisfied by adjusting the second value b. The first value a may be 1.4 μm or less. The first value a may be 1.2 μm or less. The second value b may be 1.2 μm or less. The second value b may be 1.0 μm or less.

A relational expression of "a>-b+1.4" is preferably established between the first value a and the second value b. In this case, the second value b preferably belongs to the range of 0.6 μm to 1.0 μm (0.6≦b≦1.0). When these conditions are satisfied, it is possible to increase the possibility that both the target value of the reverse current IR and the target value of the forward voltage VF are satisfied. In this case, it is particularly preferable that the relational expression "a≧−b+1.6" holds between the first value a and the second value b. When this condition is satisfied, both the target value of the reverse current IR and the target value of the forward voltage VF can be satisfied.

A relational expression “a≦−b+1.8” may be established between the first value a and the second value b. That is, both the relational expression "a>-b+1.4" and the relational expression "a≦-b+1.8" may hold between the first value a and the second value b. . It is preferable that both the relational expression “a≧−b+1.6” and the relational expression “a≦−b+1.8” hold between the first value a and the second value b.

FIG. 9 is a graph showing the sufficiency of the target value of the reverse current IR and the target value of the forward voltage VF by the relationship between the third value c and the fourth value d (see FIGS. 6 and 7). The target value of the forward voltage VF is 300 mV or less as described above. The target value of the reverse current IR is 10 mA or less as described above.

FIG. 9 shows a plurality of black plotted points and a plurality of white plotted points. A plurality of black plotted points indicate conditions in which the target value of the reverse current IR is satisfied, but the target value of the forward voltage VF is not satisfied. A plurality of white plotted points indicate conditions in which both the target value of the reverse current IR and the target value of the forward voltage VF are satisfied.

Referring to FIG. 9, the characteristics of forward voltage VF and the characteristics of reverse current IR tend to improve as third value c increases and fourth value d increases. The third value c is preferably 0.6 μm or more. Also, the fourth value d is preferably 0.35 μm or more. When these conditions are satisfied, at least the target value of the reverse current IR can be satisfied. It is particularly preferred that the third value c is 1.2 μm or more.

When this condition is satisfied, both the target value of the reverse current IR and the target value of the forward voltage VF can be satisfied. The third value c may be 1.6 μm or less. The third value c may be 1.4 μm or less. The fourth value d may be 0.6 μm or less. The fourth value d may be 0.5 μm or less.

Preferred numerical range examples of the first to third values a, b, and c extracted from the graphs of FIGS. 8 and 9 are shown below. The first value a is preferably 0.6 μm or more and 1.2 μm or less. The second value b is preferably 0.6 μm or more and 1.0 μm or less. The third value c is preferably 1.2 μm or more and 1.4 μm or less. The fourth value d is preferably 0.35 μm or more and 0.5 μm or less.

Under these conditions, the characteristics of the reverse current IR and the characteristics of the forward voltage VF can be appropriately improved. As an example, when a reverse voltage VR of 3 V is applied to the Schottky junction in a temperature environment of 125° C., a reverse current IR of 10 mA or less can be achieved. Further, when a forward current IF of 7.5 mA is applied to the Schottky junction in a temperature environment of -40°C, a forward voltage VF of 300 mV or less can be achieved.

In these cases, it is preferable that a relational expression of "a>-b+1.4" holds between the first value a and the second value b. In this case, the second value b preferably belongs to the range of 0.6 μm to 1.0 μm (0.6≦b≦1.0). It is particularly preferable that the relational expression "a≧−b+1.6" holds between the first value a and the second value b. Under these conditions, the characteristics of the reverse current IR and the characteristics of the forward voltage VF can be improved more appropriately.

10A to 10J are cross-sectional views showing an example of a method of manufacturing the semiconductor device 1A shown in FIG. 10A-10J are cross-sectional views of the region corresponding to FIG. Referring to FIG. 10A, disk-shaped wafer 40 is prepared. The wafer 40 has a wafer main surface 41 . Wafer 40 includes first semiconductor region 6 and second semiconductor region 7 . The second semiconductor region 7 consists in this embodiment of an n-type base wafer forming the body of the wafer 40 .

In this embodiment, the first semiconductor region 6 consists of an n-type epitaxial layer laminated on the second semiconductor region 7 (base wafer) by an epitaxial growth method, and is exposed from the main surface 41 of the wafer. Next, a hard mask 42 is formed to cover the main surface 41 of the wafer in the form of a film. The hard mask 42 may be formed by an oxidation treatment method (for example, a thermal oxidation treatment method) or a CVD (Chemical Vapor Deposition) method.

Next, referring to FIG. 10B, a first resist mask 43 having a predetermined pattern is formed on hard mask 42 . The first resist mask 43 exposes regions where the plurality of trenches 10 and the plurality of outer trenches 11 are to be formed, and covers regions other than these. Next, unnecessary portions of the hard mask 42 are removed by an etching method through the first resist mask 43 . The etching method may be a wet etching method and/or a dry etching method. Thereby, a plurality of openings are formed in the hard mask 42 to expose regions where the plurality of trenches 10 and the plurality of outer trenches 11 are to be formed. The first resist mask 43 is then removed.

Next, referring to FIG. 10C, unnecessary portions of the wafer 40 are removed from the wafer main surface 41 side by etching through the hard mask 42 . The etching method may be a wet etching method and/or a dry etching method. An unnecessary portion of the wafer 40 is removed up to the middle portion of the first semiconductor region 6 in the depth direction. Thereby, a plurality of trenches 10 exposing the first semiconductor regions 6 and a plurality of outer trenches 11 exposing the first semiconductor regions 6 are formed in the wafer main surface 41 .

Next, referring to FIG. 10D, a first insulating film 23 is formed on the main surface 41 of the wafer. The first insulating film 23 may be formed by an oxidation treatment method (for example, a thermal oxidation treatment method). The first insulating film 23 is formed in a film shape along the main surface 41 of the wafer, the wall surfaces of the plurality of trenches 10 and the wall surfaces of the plurality of outer trenches 11 .

Next, referring to FIG. 10E, a second resist mask 44 (shielding mask) having a predetermined pattern is formed on first insulating film 23 . The second resist mask 44 exposes regions where the plurality of impurity regions 12 are to be formed and regions where the outer impurity regions 15 (the first outer impurity region 16 and the second outer impurity region 17) are to be formed. area. Specifically, the second resist mask 44 covers the sidewalls of the multiple trenches 10 and exposes the bottom walls of the multiple trenches 10 . The second resist mask 44 preferably covers bottom wall corners and bottom wall peripheral portions of the plurality of trenches 10 .

The second resist mask 44 also covers the inner walls of the plurality of outer trenches 11 , exposing the outer walls and bottom walls of the plurality of outer trenches 11 together with a portion of the wafer main surface 41 . The second resist mask 44 preferably covers inner wall side corner portions and inner wall side peripheral portions of the bottom walls of the plurality of outer trenches 11 . The second resist mask 44 exposes the sidewalls and bottom walls of the plurality of trenches 10 at both end portions of the plurality of trenches 10 . Also, the second resist mask 44 exposes the inner walls, outer walls and bottom walls of the plurality of outer trenches 11 at both end portions of the plurality of outer trenches 11 .

Next, a p-type impurity (for example, boron as an example of a trivalent element) is introduced into first semiconductor region 6 by ion implantation through second resist mask 44 . The p-type impurity is introduced into the first semiconductor region 6 through the first insulating film 23 in this form. As a result, a plurality of first impurity diffusion starting points 45 serving as the bases of the plurality of impurity regions 12 and a second impurity diffusion serving as the bases of the outer impurity regions 15 (the first outer impurity regions 16 and the second outer impurity regions 17) are formed. A starting point 46 is formed. The second resist mask 44 is then removed.

Next, referring to FIG. 10F, a heat treatment method (drive-in treatment method) is performed on wafer 40 to cause p-type impurities to enter first semiconductor region 6 from first impurity diffusion starting point 45 and second impurity diffusion starting point 46, respectively. spread to This step includes heating the wafer 40 under heating conditions (that is, heating temperature and heating time) in which the plurality of impurity regions 12 do not reach the sidewalls of the plurality of trenches 10 . The heating conditions include a condition that outer impurity region 15 does not reach the inner wall of outer trench 11 . Thereby, a plurality of impurity regions 12 having a prescribed layout and outer impurity regions 15 having a prescribed layout are formed (see also FIGS. 6 to 9).

Next, referring to FIG. 10G, second insulating film 24 is formed on first insulating film 23 . The second insulating film 24 may be formed by the CVD method. The second insulating film 24 fills the plurality of trenches 10 and the plurality of outer trenches 11 and covers the entire wafer main surface 41 . Thereby, the insulating film 20 including the first insulating film 23 and the second insulating film 24 is formed. Before the step of forming the second insulating film 24, a step of thickening the first insulating film 23 by an oxidation treatment method (for example, a thermal oxidation treatment method) may be performed.

Next, referring to FIG. 10H, a third resist mask 47 having a predetermined pattern is formed on insulating film 20. Referring to FIG. The third resist mask 47 exposes the regions where the contact openings 21 are to be formed and covers the other regions. Next, unnecessary portions of the insulating film 20 are removed by etching using the third resist mask 47 . The etching method may be a wet etching method and/or a dry etching method. Thereby, a contact opening 21 is formed in the insulating film 20 . The third resist mask 47 is then removed.

Next, referring to FIG. 10I, a first electrode film 27 is formed on the main surface 41 of the wafer. The first electrode film 27 is made of a Ti film in this embodiment. The first electrode film 27 may be formed by sputtering or vapor deposition. Next, a silicide layer 31 is formed at the connecting portion between the wafer 40 and the first electrode film 27 by a heat treatment method (for example, RTA (Rapid Thermal Annealing) method) on the wafer 40 .

Next, referring to FIG. 10J, a second electrode film 28 is formed on the first electrode film 27. As shown in FIG. The second electrode film 28 is made of a TiN film in this embodiment. The second electrode film 28 may be formed by sputtering or vapor deposition. A third electrode film 29 is then formed on the second electrode film 28 . The third electrode film 29 is made of an AlCu film in this embodiment. The third electrode film 29 may be formed by sputtering or vapor deposition. Next, unnecessary portions of the first to third electrode films 27 to 29 are removed to form the first polarity electrode 25. Next, as shown in FIG. After that, the upper insulating film 35 and the second polar electrode 37 are formed, and the wafer 40 is cut. The semiconductor device 1A is manufactured through the steps including the above.

FIG. 11 is an internal see-through perspective view showing a package 50 in which the semiconductor device 1A shown in FIG. 1 is mounted. Referring to FIG. 11, package 50 includes package body 51, pad portion 52, first terminal portion 53, second terminal portion 54, semiconductor device 1A, conductive bonding material 55, and at least one (in this embodiment, one ) of conductors 56 .

The package main body 51 contains molding resin and is molded in a substantially hexahedral shape (substantially rectangular parallelepiped shape). The package body 51 has a first surface 57 on one side, a second surface 58 on the other side, and first to fourth side walls 59A to 59D connecting the first surface 57 and the second surface 58. As shown in FIG.

The first surface 57 and the second surface 58 are rectangular in plan view. The first side wall 59A and the second side wall 59B extend in one direction (the first direction X in this embodiment) and face each other in the cross direction (the second direction Y in this embodiment) that intersects (specifically, is perpendicular to) the one direction. are doing. The first side wall 59A and the second side wall 59B form short sides of the package body 51 . The third side wall 59C and the fourth side wall 59D extend in the cross direction (second direction Y) and face one direction (first direction X). The third side wall 59C and the fourth side wall 59D form the long sides of the package body 51. As shown in FIG.

The pad portion 52 is made of a plate-like member made of metal. The pad portion 52 is formed in a square shape in plan view. In this embodiment, the pad section 52 is arranged inside the package body 51 so as to be exposed from the second surface 58 .

The 1st terminal part 53 consists of metal plate-shaped members. The first terminal portion 53 is composed of an anode terminal. The first terminal portion 53 extends out of the package body 51 through the first side wall 59A from inside the package body 51 . The first terminal portion 53 has a first inner end portion 60 inside the package body 51 and a first outer end portion 61 outside the package body 51 . The first inner end portion 60 is spaced apart from the pad portion 52 . The first terminal portion 53 has a plurality (a pair in this embodiment) of recesses 62 recessed in the first direction X in a pair of side wall portions extending along the second direction Y in the first inner end portion 60 . The plurality of recesses 62 are engaged with the package body 51 (that is, mold resin) inside the package body 51 .

The 2nd terminal part 54 consists of metal plate-shaped members. The second terminal portion 54 consists of a cathode terminal. The second terminal portion 54 extends from the inside of the package body 51 through the second side wall 59B to the outside of the package body 51 . The second terminal portion 54 has a second inner end portion 63 inside the package body 51 and a second outer end portion 64 outside the package body 51 . The second inner end portion 63 is connected to the pad portion 52 in this embodiment. Specifically, the second inner end portion 63 is formed integrally with the pad portion 52 .

The semiconductor device 1</b>A is arranged on the pad section 52 in the package body 51 with the second polarity electrode 37 facing the pad section 52 . That is, the second polarity electrode 37 is electrically connected to the second terminal portion 54 via the pad portion 52 . The conductive bonding material 55 is interposed between the second polarity electrode 37 and the pad section 52 to mechanically and electrically bond the second polarity electrode 37 and the pad section 52 together. The conductive bonding material 55 may be solder or metal paste.

The conducting wire 56 is connected to the first polarity electrode 25 of the semiconductor device 1A and the first inner end portion 60 of the first terminal portion 53 in the package body 51 . That is, the first polarity electrode 25 is electrically connected to the first terminal portion 53 via the lead wire 56 . Conductor 56 consists of a bonding wire in this form. Conductor 56 may include at least one of Au wire, Cu wire, Ag wire and Al wire. The conducting wire 56 may be made of a metal clip (a plate-like member made of metal) instead of the bonding wire.

FIG. 12 is a perspective view showing a semiconductor device 1B according to the second embodiment. FIG. 13 is a plan view showing semiconductor device 1B shown in FIG. 14 is a plan view showing a layout example of the first main surface 3 of the chip 2 shown in FIG. 12. FIG. FIG. 15 is a plan view showing a layout example of the first polarity electrode 25 and the second polarity electrode 37. FIG. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 13. FIG.

12 to 16, semiconductor device 1B includes chip 2, first semiconductor region 6 and second semiconductor region 7, like semiconductor device 1A. Description of the first semiconductor region 6 and the second semiconductor region 7 is omitted. The chip 2 has a first principal surface 3, a second principal surface 4 and first to fourth side surfaces 5A to 5D. The 1st main surface 3 and the 2nd main surface 4 are formed in rectangular shape in planar view in this form. The first side surface 5A and the second side surface 5B form long sides of the chip 2 . The third side surface 5</b>C and the fourth side surface 5</b>D form short sides of the chip 2 .

The length of the first side surface 5A and the second side surface 5B may be 0.2 mm or more and 4 mm or less. The length of the third side surface 5C and the fourth side surface 5D may be 0.1 mm or more and 2 mm or less. The semiconductor device 1B has 1608 (1.6 mm×0.8 mm) chips and 1006 (1.0 mm×0.6 mm) chips depending on the size of the chip 2 (the length of the first to fourth side surfaces 5A to 5D). , 0603 (0.6 mm×0.3 mm) chip, 0402 (0.4 mm×0.2 mm) chip, 03015 (0.3 mm×0.15 mm) chip, and the like. In other words, the semiconductor device 1B is a chip component made up of a wafer level chip size package having the size of the chip 2 cut out from the wafer 40 as the size of the package.

Semiconductor device 1B includes an active region 8 set in first main surface 3, similar to semiconductor device 1A. The active area 8 in this form includes a first active area 8A and a second active area 8B. The first active region 8A is set in a region on the third side surface 5C side of the first main surface 3 with a gap from the peripheral edge of the first main surface 3 . In this form, the first active region 8A is set in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view. there is

The second active region 8B is set in the inner portion (specifically, the central portion) of the first main surface 3 with a gap from the peripheral edge of the first main surface 3, and extends in the first direction X so as to extend from the first active region 8A. facing. In this form, the second active region 8B is set in a rectangular shape having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view. The second active area 8B has a length in the second direction Y which is less than the length of the first active area 8A.

The semiconductor device 1B includes an outer region 9 set on the first main surface 3 as in the case of the semiconductor device 1A. The outer region 9 is set at the peripheral portion of the first main surface 3 . In this form, the outer region 9 extends along the periphery of the first main surface 3 in plan view and is set in a ring shape surrounding the first active region 8A and the second active region 8B.

Semiconductor device 1B includes an n-type diode region 70 formed in the surface layer portion of first main surface 3 in first active region 8A. The diode region 70 is formed using part of the first semiconductor region 6 in this embodiment. That is, the diode region 70 has the same n-type impurity concentration as the first semiconductor region 6 and is exposed from the first main surface 3 . Of course, diode region 70 may be adjusted to have a higher n-type impurity concentration than first semiconductor region 6 by selectively introducing n-type impurities. In this case, the diode region 70 may be formed in the surface layer portion of the first semiconductor region 6 .

Semiconductor device 1B includes a plurality of trenches 10 and a plurality of impurity regions 12 formed in second active region 8B. The plurality of trenches 10 and the plurality of impurity regions 12 according to the semiconductor device 1B are similar to the plurality of trenches 10 and the plurality of impurity regions 12 according to the semiconductor device 1A, except that they are formed in the second active region 8B. Each has a layout (see also FIGS. 6 to 9). Description of the plurality of trenches 10 and the plurality of impurity regions 12 is omitted.

Semiconductor device 1B includes outer impurity region 15 formed in first semiconductor region 6 of outer region 9 so as to partition active region 8, as in semiconductor device 1A. In this form, the outer impurity region 15 is formed spaced apart from the plurality of trenches 10 in plan view, and extends in a strip shape along the first active region 8A and the second active region 8B. Specifically, the outer impurity region 15 is formed in an annular shape collectively surrounding the first active region 8A and the second active region 8B in plan view.

The semiconductor device 1</b>B includes an n-type low resistance region 71 formed within the first semiconductor region 6 in the outer region 9 . The low resistance region 71 has a higher n-type impurity concentration than the first semiconductor region 6 . The low resistance region 71 may have an n-type impurity concentration of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. The low resistance region 71 penetrates through the first semiconductor region 6 and is connected to the second semiconductor region 7 . The low-resistance region 71 forms a current path with a lower resistance than the first semiconductor region 6 together with the second semiconductor region 7 .

The low resistance region 71 includes a first region 72 , at least one (a pair in this embodiment) second region 73 and at least one (one in this embodiment) third region 74 . The first region 72 is formed in a region of the first semiconductor region 6 on the side of the fourth side surface 5D. The first region 72 is formed in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) spaced inwardly from the peripheral edge of the first main surface 3 in plan view. The first region 72 faces the first active region 8A (diode region 70) across the second active region 8B (group of trenches 10).

A pair of second regions 73 are drawn out from the first region 72 toward the third side surface 5C side (first active region 8A side). In this embodiment, the pair of second regions 73 are drawn out from the first region 72 in a band shape in the first direction X so as to sandwich the second active region 8B from both sides in the second direction Y in plan view. The pair of second regions 73 faces the second active region 8B (group of trenches 10) in the second direction Y and faces the first active region 8A in the first direction X in plan view. The pair of second regions 73 are formed spaced inwardly from the peripheral edge of the first main surface 3 in plan view.

The third region 74 is pulled out from one or both of the pair of second regions 73 toward the third side surface 5C, and extends in a strip shape along the first active region 8A. In this form, the third region 74 is drawn out from both of the pair of second regions 73 and surrounds the first active region 8A. The third region 74 is formed spaced inwardly from the peripheral edge of the first main surface 3 in plan view. The third region 74 has a width smaller than that of the second region 73 in plan view. Of course, the third region 74 may have a width substantially equal to the width of the second region 73 in plan view.

Thus, the low resistance region 71 faces the first active region 8A from multiple directions and faces the second active region 8B from multiple directions. Specifically, the low resistance region 71 collectively surrounds the first active region 8A and the second active region 8B. The low-resistance region 71 reduces the resistance value of the current path from the first active region 8A to the region on the side of the fourth side surface 5D, and reduces the resistance value of the current path from the second active region 8B to the region on the side of the fourth side surface 5D. to reduce Of course, the low resistance region 71 only needs to include at least one of the first to third regions 72-74, and does not necessarily include all of the first to third regions 72-74 at the same time.

Semiconductor device 1B includes an insulating film 20 formed on first main surface 3 as in semiconductor device 1A. The insulating film 20 has a laminated structure including a first insulating film 23 and a second insulating film 24, as in the case of the semiconductor device 1A. The insulating film 20 includes a first contact opening 75 and a second contact opening 76 in this form. The first contact opening 75 exposes the first active area 8A and the second active area 8B. A wall portion defining the first contact opening 75 is located directly above the outer impurity region 15 . A second contact opening 76 is formed along the first to third regions 72 to 74 so as to expose the first to third regions 72 to 74 of the low resistance region 71 .

Semiconductor device 1B includes first polar electrode 25 formed on first main surface 3, as in semiconductor device 1A. As in the case of the semiconductor device 1A, the first polar electrode 25 has a laminated structure including a first electrode film 27, a second electrode film 28 and a third electrode film 29 laminated in this order from the chip 2 side. .

The first polar electrode 25 includes a first pad portion 80 and a first lead portion 81 in this embodiment. The first pad portion 80 enters the first contact opening 75 from above the insulating film 20 so as to cover the first active region 8A (the region on the third side surface 5C side of the first main surface 3). The first pad portion 80 is formed in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) spaced inwardly from the peripheral edge of the first main surface 3 in plan view. The first pad portion 80 is electrically connected to the outer impurity region 15 in the first active region 8A and forms a Schottky junction with the diode region 70 (first semiconductor region 6).

The first lead-out portion 81 extends from the first pad portion 80 toward the second active region 8B so as to cover the second active region 8B, and enters the first contact opening 75 from above the insulating film 20 . The first drawn-out portion 81 is formed to be spaced inwardly from the peripheral edge of the first main surface 3 in plan view. First lead-out portion 81 is electrically connected to impurity region 12 and outer impurity region 15 in first contact opening 75 and forms a Schottky junction with first semiconductor region 6 .

Specifically, the first lead-out portion 81 covers the first main surface 3 in the second active region 8B and enters the plurality of trenches 10 from the first main surface 3 . The first lead-out portion 81 is electrically connected to the impurity region 12 at the bottom wall of each trench 10 and forms a Schottky junction with the first semiconductor region 6 at the side wall of each trench 10 . The first lead-out portion 81 includes a portion forming a Schottky junction with the first semiconductor region 6 on the bottom wall of each trench 10 . Specifically, the first lead-out portion 81 forms a Schottky junction with the first semiconductor region 6 at the bottom wall corner portion and the bottom wall peripheral edge portion of each trench 10 .

Thus, in the first active region 8A, the first SBD structure 82 ( Schottky junction) is formed. Also, in the second active region 8B, a second SBD structure 83 (Schottky junction) having a first polar electrode 25 (first lead-out portion 81) as an anode and a first semiconductor region 6 as a cathode is formed. there is A second SBD structure 83 is connected in parallel with the first SBD structure 82 .

Semiconductor device 1B includes a second polarity electrode 37 formed on first main surface 3 instead of second main surface 4, unlike semiconductor device 1A. A second polar electrode 37 is disposed on the first major surface 3 laterally spaced along the first major surface 3 from the first polar electrode 25 . That is, the semiconductor device 1B includes a lateral type SBD. In this embodiment, the second polarity electrode 37 is a laminate including a first electrode film 27, a second electrode film 28 and a third electrode film 29 which are laminated in this order from the chip 2 side, as in the case of the first polarity electrode 25. have a structure.

The second polarity electrode 37 enters the second contact opening 76 from above the insulating film 20 . The second polarity electrode 37 is electrically connected to the low resistance region 71 within the second contact opening 76 . Specifically, the second polar electrode 37 forms an ohmic contact with the low resistance region 71 . In this embodiment, the second polarity electrode 37 includes a second pad section 84, at least one (a pair in this embodiment) second lead section 85, and at least one (one in this embodiment) third lead section. Including 86.

The second pad portion 84 enters the second contact opening 76 from above the insulating film 20 so as to cover the first region 72 of the low resistance region 71 (the region on the side of the fourth side surface 5D of the first main surface 3). there is The second pad portion 84 is electrically connected to the first region 72 within the second contact opening 76 . The second pad portion 84 is formed in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) spaced inwardly from the peripheral edge of the first main surface 3 in plan view. The second pad portion 84 faces the first pad portion 80 with the first lead-out portion 81 interposed therebetween.

A pair of second lead portions 85 are led out from the first pad portion 80 toward the third side surface 5C side (second active region 8B side) so as to cover the second region 73 of the low resistance region 71, and are formed by an insulating film. 20 enters the second contact opening 76 from above. In this embodiment, the pair of second lead portions 85 extend from the first pad portion 80 in the first direction X so as to sandwich the first lead portions 81 (second active regions 8B) from both sides in the second direction Y in plan view. is pulled out in a strip shape.

The pair of second lead-out portions 85 faces the first pad portion 80 in the first direction X and faces the first lead-out portion 81 in the second direction Y in plan view. The pair of second lead-out portions 85 are formed to be spaced inwardly from the peripheral edge of the first main surface 3 in plan view. The pair of second lead portions 85 are electrically connected to the second region 73 of the low resistance region 71 within the second contact opening 76 .

The third lead-out portion 86 is led out from one or both of the pair of second lead-out portions 85 toward the third side surface 5</b>C so as to cover the third region 74 of the low resistance region 71 . It enters the second contact opening 76 . The third lead-out portion 86 is spaced inwardly from the peripheral edge of the first main surface 3 in plan view, and extends in a strip shape along the first pad portion 80 (first active region 8A).

In this embodiment, the third lead-out portion 86 is led out from both of the pair of second lead-out portions 85 and surrounds the first pad portion 80 (first active region 8A). The third lead portion 86 is electrically connected to the third region 74 of the low resistance region 71 within the second contact opening 76 . The third lead-out portion 86 has a width smaller than that of the second lead-out portion 85 in plan view. Of course, the third lead-out portion 86 may have a width substantially equal to the width of the second lead-out portion 85 in plan view.

Although not shown in detail, the semiconductor device 1B includes a connection portion between the chip 2 and the first polarity electrode 25 and a silicide layer 31 formed at a connection portion between the chip 2 and the second polarity electrode 37 ( See also FIG. 7). Specifically, the silicide layer 31 is formed at the connecting portion between the chip 2 and the first electrode film 27 .

The semiconductor device 1B includes an insulating layer 90 selectively covering the first polar electrode 25 (the first polar electrode 25 and the second polar electrode 37). The insulating layer 90 includes a first pad opening 91 exposing the first polarity electrode 25 . Specifically, the first pad opening 91 exposes the first pad portion 80 of the first polarity electrode 25 . The first pad opening 91 is formed in a square shape (specifically, a rectangular shape extending in the second direction Y) spaced inward from the peripheral edge of the first pad portion 80 in plan view.

The insulating layer 90 includes a second pad opening 92 spaced from the first pad opening 91 to expose the second polarity electrode 37 . Specifically, the second pad opening 92 exposes the second pad portion 84 of the second polarity electrode 37 . In this embodiment, the second pad opening 92 is formed in a square shape (specifically, a rectangular shape extending in the second direction Y) spaced inwardly from the periphery of the second pad portion 84 in plan view. .

In this embodiment, the insulating layer 90 has a laminated structure including an inorganic insulating film 93 and an organic insulating film 94 laminated in this order from the first polarity electrode 25 side. Inorganic insulating film 93 may include at least one of a silicon oxide film and a silicon nitride film. Inorganic insulating film 93 includes a silicon nitride film in this embodiment. Organic insulating film 94 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. The organic insulating film 94 includes a polyimide film in this form. Of course, the insulating layer 90 may have a single layer structure consisting of the inorganic insulating film 93 or the organic insulating film 94 .

Semiconductor device 1B includes a first terminal electrode 95 electrically connected to first polarity electrode 25 . The first terminal electrode 95 is arranged inside the first pad opening 91 and electrically connected to the first pad portion 80 inside the first pad opening 91 . Semiconductor device 1B includes a second terminal electrode 96 electrically connected to second polarity electrode 37 . The second terminal electrode 96 is arranged inside the second pad opening 92 and electrically connected to the second pad portion 84 inside the second pad opening 92 .

The first and second terminal electrodes 95 and 96 each have a laminated structure including a Ni film 97, a Pd film 98 and an Au film 99 laminated in this order from the chip 2 side. The Ni film 97 may have a portion that fills back the first and second pad openings 91 and 92 and covers the main surface of the insulating layer 90 . The Pd film 98 covers the main surface of the Ni film 97 in the form of a film. The Pd film 98 may have a portion covering the outer surface of the insulating layer 90 . The Au film 99 coats the outer surface of the Pd film 98 like a film. The Au film 99 may have a portion covering the main surface of the insulating layer 90 .

Semiconductor device 1B includes sidewall insulating films 100 covering first to fourth side surfaces 5A to 5D of chip 2 . The sidewall insulating film 100 covers the entire circumference of the first to fourth side surfaces 5A to 5D and exposes the second main surface 4. As shown in FIG. In this embodiment, sidewall insulating film 100 may cover part or all of the sidewalls of insulating layer 90 so that the main surface of insulating layer 90 is exposed. Sidewall insulating film 100 may include at least one of a silicon oxide film and a silicon nitride film.

As described above, semiconductor device 1B includes chip 2, first semiconductor region 6, trench 10, impurity region 12, and first polar electrode 25 (main surface electrode). Chip 2 has a first main surface 3 . The first semiconductor region 6 is formed within the chip 2 so as to be exposed from the first main surface 3 . Trench 10 is formed in first main surface 3 and has sidewalls and a bottom wall. The impurity region 12 is formed along the bottom wall of the trench 10 within the first semiconductor region 6 so as to expose the entire side wall of the trench 10 . The first polar electrode 25 covers the first main surface 3 and forms a Schottky junction with the first semiconductor region 6 .

According to this structure, it is possible to provide the semiconductor device 1B capable of improving electrical characteristics. Specifically, by adjusting the layout of the trenches 10 and the layout of the impurity regions 12, it is possible to provide the semiconductor device 1B capable of improving the characteristics of the forward voltage VF and the characteristics of the reverse current IR, which are examples of electrical characteristics. .

This form shows an example in which a plurality of trenches 10 and a plurality of impurity regions 12 are formed in the second active region 8B. However, the plurality of trenches 10 and the plurality of impurity regions 12 may be formed in the first active region 8A instead of the second active region 8B. That is, the arrangement of the first SBD structure 82 and the second SBD structure 83 may be interchanged.

In this case, the plurality of trenches 10 and the plurality of impurity regions 12 are connected to the first polarity electrode 25 (first pad portion 80) in the first active region 8A. Of course, multiple trenches 10 and multiple impurity regions 12 may be formed in both the first active region 8A and the second active region 8B. That is, the second SBD structure 83 may be formed in both the first active region 8A and the second active region 8B.

Although the embodiments have been described above, the above-described embodiments can be embodied in other forms. For example, outer trench 11 may have the layout shown in FIG. FIG. 17 is a plan view showing a layout example of the outer trench 11 according to the modification. Referring to FIG. 17 , outer trench 11 may be formed in an annular shape surrounding multiple trenches 10 . The layout of the outer impurity regions 15 with respect to the layout of the outer trenches 11 is the same as in the first embodiment (see also FIGS. 6 and 7).

The multiple trenches 10 may have the layout shown in FIG. FIG. 18 is a plan view showing a layout example of trenches 10 according to the first modification. Referring to FIG. 18, a plurality of trenches 10 may be arranged in a matrix form (dot form) at intervals in the first direction X and the second direction Y in plan view. In this case, the outer trenches 11 may also be arranged in dots at intervals in the second direction Y according to the layout of the plurality of trenches 10 .

Of course, the plurality of trenches 10 may be arranged in a zigzag pattern (dot pattern) at intervals in the first direction X and the second direction Y in plan view. In this case, for example, the plurality of trenches 10 positioned in even-numbered rows (or odd-numbered rows) may be arranged shifted in the second direction Y from the plurality of trenches 10 positioned in odd-numbered rows (or even-numbered rows). Of course, the plurality of trenches 10 located in even-numbered rows (or odd-numbered rows) may be arranged shifted in the first direction X from the plurality of trenches 10 located in odd-numbered rows (or even-numbered rows).

A plurality of trenches 10 may have the layout shown in FIG. FIG. 19 is a plan view showing a layout example of trenches 10 according to the second modification. Referring to FIG. 19, multiple trenches 10 include multiple first trenches 10A extending in the first direction X and multiple second trenches 10B extending in the second direction Y in this embodiment. The plurality of second trenches 10B intersect with the plurality of first trenches 10A to form one grid-shaped trench 10 together with the plurality of first trenches 10A.

In this case, the plurality of impurity regions 12 include a plurality of first impurity regions 12A covering the bottom walls of the plurality of first trenches 10A, respectively, and a plurality of second impurity regions 12A covering the bottom walls of the plurality of second trenches 10B, respectively. An impurity region 12B may be included. The layout of the first impurity regions 12A with respect to the layout of the first trenches 10A is the same as in the first embodiment (see also FIGS. 6 and 7).

Also, the layout of the second impurity regions 12B with respect to the layout of the second trenches 10B is the same as in the case of the first embodiment (see also FIGS. 6 and 7). Of course, the plurality of impurity regions 12 may include either one of the plurality of first impurity regions 12A or the plurality of second impurity regions 12B, and the plurality of first impurity regions 12A and the plurality of second impurity regions are not necessarily required. 12B need not be included at the same time.

Of course, the plurality of trenches 10 may be formed in a concentric layout or a spiral layout in a plan view by combining the plurality of first trenches 10A and the plurality of second trenches 10B. good too. In these cases, the plurality of impurity regions 12 may be formed in a concentric layout in plan view or a spiral layout by combining the plurality of first impurity regions 12A and the plurality of second impurity regions 12B. may be formed of

In each of the above-described embodiments, when the chip 2 made of SiC single crystal is adopted, the chip 2 preferably contains the SiC single crystal made of hexagonal crystal. The SiC single crystal may be 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, or the like. The chip 2 is preferably made of 4H--SiC single crystal of the polytype.

The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of SiC single crystal. In this case, the first main surface 3 is formed by the silicon surface ((0001) plane) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) plane) of the SiC single crystal. is preferred. Of course, the first main surface 3 may be formed by a carbon surface and the second main surface 4 may be formed by a silicon surface.

The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane of the SiC single crystal. The off-direction may be the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be 0° or more and 5° or less. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

In each of the embodiments described above, the first direction X and the second direction Y were defined by the extending directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be arbitrary directions as long as they maintain a relationship of crossing each other (specifically, orthogonally).

Below are examples of features that can be extracted from the specification and drawings. Hereinafter, alphanumeric characters in parentheses represent components corresponding to the above-described embodiments, but the scope of each item is not limited to the embodiments. "Semiconductor device" in the following items may be changed to "semiconductor rectifier device" or "chip part".

[A1] A chip (2) having a main surface (3) and a semiconductor region (6) of a first conductivity type (n-type) formed in the chip (2) so as to be exposed from the main surface (3) ), a trench (10) formed in said main surface (3) and having sidewalls and a bottom wall, and said an impurity region (12) of a second conductivity type (p-type) formed only in a region along the bottom wall of the trench (10); A semiconductor device (1A, 1B) comprising: a main surface electrode (25) forming a junction.

[A2] The main surface electrode (25) is electrically connected to the impurity region (12) on the bottom wall of the trench (10), and the semiconductor region (6) on the sidewall of the trench (10). and the semiconductor device (1A, 1B) according to A1, forming the Schottky junction.

[A3] The semiconductor device (1A, 1B).

[A4] Any one of A1 to A3, wherein the impurity region (12) is formed only in a region along the bottom wall of the trench (10) spaced apart from the side wall of the trench (10). 1. The semiconductor device (1A, 1B) according to 1.

[A5] The semiconductor device according to any one of A1 to A4, wherein a reverse current IR is 10 mA or less when a reverse voltage VR of 3 V is applied to the Schottky junction in a temperature environment of 125° C. ( 1A, 1B).

[A6] According to any one of A1 to A5, the forward voltage VF is 300 mV or less when a forward current IF of 7.5 mA is applied to the Schottky junction in a temperature environment of -40°C. A semiconductor device (1A, 1B).

[A7] In a cross-sectional view, a plurality of trenches (10) are formed at intervals in the main surface (3), and in a cross-sectional view, the plurality of impurity regions (12) are formed in the plurality of trenches (10). The semiconductor device (1A, 1B ).

[A8] The plurality of trenches (10) are formed in the main surface (3) at intervals of a first value a in a cross-sectional view, and have a second value b (b≦ The semiconductor device (1A, 1B) of A7, each having a width of a).

[A9] The semiconductor device (1A, 1B) according to A8, wherein the first value a is 0.4 μm or more and 1.4 μm or less.

[A10] The semiconductor device (1A, 1B) according to A8 or A9, wherein the second value b is 0.4 μm or more and 1.2 μm or less.

[A11] A8 to A10, wherein the plurality of trenches (10) are formed to have a relational expression of "a>-b+1.4" between the first value a and the second value b A semiconductor device (1A, 1B) according to any one of the above.

[A12] The plurality of impurity regions (12) extend along the bottom walls of the plurality of trenches (10) at intervals of a third value c (a≤c) equal to or greater than the first value a in a cross-sectional view. The semiconductor device according to any one of A8 to A11 (1A, 1B ).

[A13] The semiconductor device (1A, 1B) according to A12, wherein the third value c is 0.4 μm or more and 1.6 μm or less.

[A14] The semiconductor device (1A, 1B) according to A12 or A13, wherein the fourth value d is 0.35 μm or more and 1.2 μm or less.

[A15] An active region (8) set on the main surface (3), an outer region (9) set outside the active region (8) on the main surface (3), and the active region (8) ) formed in the main surface (3) of the outer region (9) so as to partition the trench (10) formed in the main surface (3) and the active region (8), and the active region An outer trench (11) having an inner wall on the (8) side, an outer wall on the outer region (9) side, and a bottom wall connecting the inner wall and the outer wall, and the semiconductor region (6) in the outer region (9) ), an outer impurity region (15) of a second conductivity type (p-type) formed in a region along the outer wall of the outer trench (11) within the trench (11). semiconductor device (1A, 1B).

[A16] The outer impurity region (15) is formed in a region along the outer wall and the bottom wall of the outer trench (11) so as to expose the inner wall of the outer trench (11), A semiconductor device (1A, 1B) as described.

[A17] The semiconductor device (1A, 1B) according to A15 or A16, wherein the outer impurity region (15) exposes a part of the bottom wall of the outer trench (11).

[A18] A step of preparing a wafer (40) having a main surface (41) in which a semiconductor region (6) of a first conductivity type (n-type) is exposed; forming a trench (10) having sidewalls and a bottom wall in said main surface (41) by removing unnecessary portions of said trench (10); forming a second conductivity type (p-type) impurity region (12) in the semiconductor region (6) along only the bottom wall of the trench (10) by introducing; ) and forming a main surface electrode (25) forming a Schottky junction on the main surface (41).

[A19] further comprising the step of exposing the bottom wall of the trench (10) and forming a shielding mask (44) on the main surface (41) covering the sidewalls of the trench (10); The semiconductor device according to A18 ( 1A, 1B) manufacturing method.

[A20] In the step of forming the main surface electrode (25), the bottom wall of the trench (10) is electrically connected to the impurity region (12), and the side wall of the trench (10) is electrically connected to the semiconductor region (12). (6) and the step of forming the main surface electrode (25) forming the Schottky junction.

Although the embodiments have been described in detail, these are merely specific examples used to clarify the technical content, and the present invention should not be construed as being limited to these specific examples. is limited by the scope of the appended claims.

1A semiconductor device 1B semiconductor device 2 chip 3 first main surface 6 semiconductor region 8 active region 9 outer region 10 trench 11 outer trench 12 impurity region 15 outer impurity region 25 first polarity electrode (main surface electrode)
40 Wafer 41 Main surface of wafer 44 Second resist mask (shielding mask)
a first value b second value c third value d fourth value

Claims (20)

a chip having a major surface;
a semiconductor region of a first conductivity type formed in the chip so as to be exposed from the main surface;
a trench formed in the main surface and having sidewalls and a bottom wall;
an impurity region of a second conductivity type formed only in a region along the bottom wall of the trench in the semiconductor region;
a main surface electrode covering the main surface and forming a Schottky junction with the semiconductor region. 2. The semiconductor device according to claim 1, wherein said main surface electrode is electrically connected to said impurity region at said bottom wall of said trench, and forms said Schottky junction with said semiconductor region at said sidewall of said trench. . 3. The semiconductor device according to claim 1, wherein said main surface electrode includes a portion forming said Schottky junction with said semiconductor region on said bottom wall of said trench. 4. The semiconductor device according to claim 1, wherein said impurity region is formed only in a region along said bottom wall of said trench at a distance from said side wall of said trench. 5. The semiconductor device according to claim 1, wherein a reverse current IR is 10 mA or less when a reverse voltage VR of 3 V is applied to said Schottky junction in a temperature environment of 125.degree. The semiconductor according to any one of claims 1 to 5, wherein a forward voltage VF is 300 mV or less when a forward current IF of 7.5 mA is applied to the Schottky junction in a temperature environment of -40°C. Device. In a cross-sectional view, a plurality of trenches are formed on the main surface at intervals,
7. The plurality of impurity regions are respectively formed only in regions along the bottom walls of the plurality of trenches so as to expose the entire sidewalls of the plurality of trenches in a cross-sectional view. The semiconductor device according to any one of 1. The plurality of trenches are formed on the principal surface at intervals of a first value a in a cross-sectional view, and each have a width of a second value b (b≦a) equal to or less than the first value a. 8. The semiconductor device according to claim 7, wherein 9. The semiconductor device according to claim 8, wherein said first value a is 0.4 [mu]m or more and 1.4 [mu]m or less. 10. The semiconductor device according to claim 8, wherein said second value b is 0.4 [mu]m or more and 1.2 [mu]m or less. 11. The trenches according to any one of claims 8 to 10, wherein the plurality of trenches are formed to have a relational expression of "a>-b+1.4" between the first value a and the second value b. The semiconductor device according to . The plurality of impurity regions are formed in regions along the bottom walls of the plurality of trenches at intervals of a third value c (a≦c) equal to or greater than the first value a in a cross-sectional view, and 12. The semiconductor device according to claim 8, each having a width of a fourth value d (d≦b) equal to or smaller than the second value b. 13. The semiconductor device according to claim 12, wherein said third value c is 0.4 [mu]m or more and 1.6 [mu]m or less. 14. The semiconductor device according to claim 12, wherein said fourth value d is 0.35 [mu]m or more and 1.2 [mu]m or less. an active area set on the main surface;
an outer region set outside the active region on the main surface;
the trench formed in the main surface in the active region;
an outer trench formed in the main surface of the outer region so as to partition the active region and having an inner wall on the active region side, an outer wall on the outer region side, and a bottom wall connecting the inner wall and the outer wall; ,
15. The semiconductor according to claim 1, further comprising an outer impurity region of a second conductivity type formed in a region along said outer wall of said outer trench within said semiconductor region of said outer region. Device. 16. The semiconductor device according to claim 15, wherein said outer impurity region is formed in a region along said outer wall and said bottom wall of said outer trench so as to expose said inner wall of said outer trench. 17. The semiconductor device according to claim 15, wherein said outer impurity region exposes a portion of said bottom wall of said outer trench. preparing a wafer having a principal surface on which a semiconductor region of the first conductivity type is exposed;
forming trenches having sidewalls and bottom walls in the main surface by removing unnecessary portions of the wafer from the main surface;
forming a second conductivity type impurity region in the semiconductor region along only the bottom wall of the trench by introducing a second conductivity type impurity only into the bottom wall of the trench;
and forming, on the main surface, a main surface electrode forming a Schottky junction with the semiconductor region. forming a shielding mask over the major surface exposing the bottom wall of the trench and covering the sidewalls of the trench;
19. The method of manufacturing a semiconductor device according to claim 18, wherein said step of forming said impurity region includes a step of introducing said second conductivity type impurity only into said bottom wall of said trench through said shielding mask. The step of forming the main surface electrode is a step of forming the main surface electrode electrically connected to the impurity region on the bottom wall of the trench and forming the Schottky junction with the semiconductor region on the sidewall of the trench. 20. The method of manufacturing a semiconductor device according to claim 18, comprising:

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