JP2022067916A - Controller and control method for controller - Google Patents

Abstract

To provide a mirroring system capable of executing necessary instructions for each storage device without generating unnecessary read processing as a mirroring system, thus not causing performance degradation because application to a bridge device of one-input and two-outputs like the mirroring system causes execution of the same instructions for two storage devices.SOLUTION: In an information processing system, host controller control means, upon receiving a reading request of a command group from a first semiconductor storage device, makes the first semiconductor storage device read a first command group and upon receiving a reading request of a command group from a second semiconductor storage device, makes the second semiconductor storage device read commands of a second type without making the second semiconductor storage device read commands of a first type of the first command group.SELECTED DRAWING: Figure 8

Description

The present invention relates to a control device and a control method for the control device.

In recent years, in information processing devices such as PCs, solid state drives (SSDs) using non-volatile memories have replaced hard disk drives (HDDs), and higher-speed data transfer has become possible. On the other hand, Serial ATA (SATA), which is an interface used for these storage devices, cannot exhibit the original transfer performance of SSD because the physical overhead required for data encoding at the time of transfer is large and the latency is large. Therefore, in recent years, SSDs compatible with the Non-volatile Memory Express (NVMe) protocol, which is a new protocol that can be directly connected to the general-purpose bus PCI-Express (PCIe) and take advantage of the high speed of SSDs, have begun to appear.

Further, as a mechanism for protecting data against a failure of a storage device such as an HDD or SSD, there is a mirroring technique for duplicating and storing data using two storage devices. Since mirroring uses a bridge device to record data from the host in two storage devices at the same time, even if the data or the storage device itself is damaged, it can be recovered by copying the data from the other.

The bridge device of Patent Document 1 receives a first instruction group from an application executed by a host computer on the first interface using an NVMe-Of (or NVMe) protocol. The bridge device then generates a second instruction group based on the first instruction group and transmits the second instruction group generated on the second interface using the second NVMe protocol.

Japanese Unexamined Patent Publication No. 2019-75104

The bridge device described in Patent Document 1 receives an instruction group from a host computer and generates an instruction group to be transmitted to a storage device from the received contents.

However, since this bridge device is configured to generate one instruction group to be transmitted from one received instruction group, if it corresponds to a one-input two-output bridge device such as a mirroring system, two storage devices are used. The same instruction will be executed for.

Therefore, it is not possible to perform different processing for each storage device. As a result, a command that needs to be executed by only one storage device, for example, a read command to the storage device is generated in the two storage devices. As a result, unnecessary read processing occurs as a mirroring system, which may reduce performance.

An object of the present invention is to provide a mirroring system capable of executing necessary instructions for each storage device.

The present invention is a control device that communicates with a host device and communicates with a non-volatile first semiconductor storage device and a non-volatile second semiconductor storage device, and is a first type of command received from the host device. It has a holding means for holding a first command group including a second type of command, and a control means for mirror-controlling the first semiconductor storage device and the second semiconductor storage device, and the control means is the first. 1 When a read request for a command group is received from a semiconductor storage device, the first command group is read by the first semiconductor storage device, and when a read request for a command group is received from the second semiconductor storage device, the first command is read. It is characterized in that the first type of command in the group is not read by the second semiconductor storage device, and the second type of command is read by the second semiconductor storage device.

According to the present invention, it is possible to provide a mirroring system capable of executing necessary instructions for each storage device.

It is a block diagram which shows the system configuration of an information processing apparatus. It is a block diagram of HC of an information processing apparatus. It is a block diagram of the bridge device of an information processing apparatus. It is a block diagram of the storage device of an information processing apparatus. It is a detailed memory diagram of a bridge device. It is a block diagram of the bridge apparatus for demonstrating the memory map conversion means. It is a format diagram of a command. It is a flowchart of the sequencer of the memory map conversion means. It is a table explaining the function of the memory map conversion means. It is a flowchart of a bridge device.

Each embodiment of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the following examples do not limit the invention according to the claims, and not all combinations of features described in the examples are essential for the means for solving the present invention. In this embodiment, an image processing device will be described as an example of the information processing device.

(Example 1)
FIG. 1 is a block diagram showing a configuration of an information processing system (mirroring system) according to the present embodiment.

The information processing system 1 includes a host controller 101, a bridge device (control device) 102, a first storage device 103, and a second storage device 104.

The host controller (hereinafter referred to as HC) 101 is connected to the bridge device 102 and functions as a main controller that controls the entire device. In this embodiment, for example, it is possible to control an image forming function such as a printing function and a scanning function.

The bridge device 102 is connected to the HC 101, the first storage device 103, and the second storage device 104, and mirroring in which the data stored in the first storage device 103 from the HC 101 is duplicated and stored in the second storage device 104. Has the function of.

The first storage device 103 is connected to the bridge device 102 and is an SSD (semiconductor storage device), and stores system software, user data, application data, and the like handled by the HC 101. Further, the image data read from the scanner 207, which will be described later, and the image data received from the information processing apparatus (not shown) via the network are stored. The second storage device 104 is connected to the bridge device 102 and is an SSD, and stores backup data in which the data of the first storage device 103 is duplicated.

<Explanation of block configuration of HC101>
FIG. 2 is a detailed block diagram of the HC101.

The HC 101 has a CPU 201, a PCIe-IF202, a ROM 203, and a RAM 204, and is connected to the bridge device 102 via the PCIe-IF202.

The CPU 201 controls access to various devices connected based on a control program or the like stored in the ROM 203, and also controls various processes executed by the HC 101.

The PCIe-IF202 is an interface of the PCI-Express standard, and the bridge device 102 is used as an Endpoint to communicate data to be transmitted / received with the bridge device 102.

The scanner I / F 205 is an interface for communicating with the scanner 207. The printer I / F 206 is an interface for communicating with the printer 208. The scanner 207 optically reads an image from the original and generates image data. The printer unit 208 forms an image on a recording medium (paper) according to an electrophotographic method.

The ROM 203 is a non-volatile memory, and stores a boot program, a control program, and the like of the bridge device 102.

The RAM 204 is a memory such as a DRAM, in which data is temporarily stored and works as a work memory. An example of the memory map of the RAM 204 is shown in FIG. 5 (A). In the memory space of the RAM 204, a Submission Queue (referred to as SQ) 501 and a Completion Queue (referred to as CQ) 502 used in the NVMe protocol are configured.

The SQ501 is a queue of the ring buffer generated on the RAM 204, and the NVMe commands generated by the CPU 201 in order to communicate the NVMe commands are sequentially stored. The first element of the command stored in SQ501 is managed by the Head pointer 503, and the last element of the command stored in SQ501 is managed by the Tail pointer 504. The command format will be described later.

The CQ502 is a queue of the ring buffer generated on the RAM 204, and the command processing completion notification from the bridge device 102, which is an Endpoint, is sequentially stored. The first element of the completion notification stored in the CQ502 is managed by the Head pointer 505, and the last element of the completion notification stored in the CQ502 is managed by the Tail pointer 506.

In SQ501 and CQ502, a command or a command processing completion notification is stored at the position of the queue sandwiched between the Head pointers 503 and 505 and the Tail pointers 504 and 506, respectively. If the Head and Tail pointers are in the same position, it indicates that the queue is empty. In the example of FIG. 5A, it is shown that the command or the command processing completion notification is stored in the shaded area.

It is assumed that the memory space allocated to these SQs and CQs is statically determined. When the system is started, the CPU 201 secures the memory space of the SQ and the CQ, and shares the information of the memory space of the SQ and the CQ with the bridge device 102 by the admin command. However, the present invention is not limited to this.

<Explanation of block configuration of bridge device 102>
FIG. 3 is a detailed block diagram of the bridge device 102.

The bridge device 102 includes a sub CPU 301, a PCIe-IF302, a PCIe-IF303, a PCIe-IF304, a ROM 305, and a memory map conversion means 309. Each module is connected by an AIC (AXI Interconnect) 321. Further, the RAM 306 is connected via, for example, an APB (AMBA Peripheral Bus) 322 via the memory map conversion means 309.

The bridge device 102 is connected to the HC 101 via the PCIe-IF 302 and is connected to the first storage device 103 and the second storage device 104 via the PCIe-IF 303 and 304.

The sub CPU 301 controls access between the HC 101 and the first storage device 103 and the second storage device 104, which are connected based on the control program or the like stored in the ROM 305. Further, the sub CPU 301 generates a command group for each storage device based on the command group received from the HC 101.

The PCIe-IF302 uses the HC101 as a RootComplex and communicates data to be transmitted / received with the HC101. The PCIe-IF302 is internally provided with a Submission Queue Tail Doorbell (SQTD) 307 and a Completion Queue Head Doorbell (CQHD) 308 register. These registers are registers for storing the information of the Tail pointer 504 of the SQ501 of the HC101 and the information of the Head pointer 505 of the CQ502.

SQDT307 indicates the position of the next NVMe command. For example, when Current Tail 503, which is the start address of SQ501 in FIG. 5A, is stored in SQDT307, the next NVMe command indicates that it exists from the beginning of SQ501.

Then, the CPU 201 stores five NVMe commands as shown in FIG. 5A, and then rewrites the SQTD 307 with the New Tail pointer 504. As a result, the five NVMe commands from the beginning to the New Tail pointer 504 are transmitted to the bridge device 102 as execution targets. This is called a Doorbell notification.

The CQHD 308 indicates a pointer to which the CPU 201 notifies the bridge device 102 of the NVMe command execution result. For example, in the case of FIG. 5A, the CPU 102 performs a Doorbell notification in the CQHD 308 with the value of the Head pointer 505 stored in the CQHD 308.

The sub CPU 301 controls access between the HC 101 and the first storage device 103 and the second storage device 104, which are connected based on the control program or the like stored in the ROM 305. Further, an NVMe command group for each storage device is generated based on the NVMe command group received from the HC101.

The PCIe-IF302 uses the HC101 as a RootComplex to exchange data to be transmitted and received to and from the HC101.

The PCIe-IF303 and the PCIe-IF304 use the first storage device 103 and the second storage device 104 as Endpoints, respectively, and exchange data with and from the storage device.

The ROM 305 is a non-volatile memory, and stores a boot program, a control program, and the like of the bridge device 102.

The RAM 306 is a memory such as a DRAM, in which data is temporarily stored and works as a work memory.

Further, an example of using the RAM 306 is shown in FIG. 5 (B). One SQ507 and two CQ508s and CQ510s used in the NVMe protocol are configured in RAM 306. FIG. 5B is a memory map that can be seen when the RAM 306 is read (notification request of a command group) from the SSD controller 401 of the first storage device 103.

The SQ507 is a queue of the ring buffer generated on the RAM 306, and stores the NVMe command generated by the bridge device 102 for exchanging NVMe commands. The head position and size of the SQ507 are notified and shared to the first storage device 103 and the second storage device 104 by the admin command issued by the sub CPU 301 at the time of initializing the SQ507.

The CQ508 is a queue of the ring buffer generated on the RAM 306, and the first storage device 103, which is an Endpoint, sequentially stores the NVMe command execution results. The head position and size of the CQ508 are notified to the first storage device 103 by the admin command issued by the sub CPU 301 at the time of initialization of the CQ508 and shared.

The CQ 510 is a queue of a ring buffer generated on the RAM 306, and the second storage device 104, which is an Endpoint, sequentially stores NVMe command execution result notifications. The head position and size of the CQ 510 are notified and shared to the second storage device 104 by the admin command issued by the sub CPU 301 at the time of initializing the CQ 510.

The memory map conversion means 309 is a memory map conversion means that makes it appear that the area of the read command in the SQ507 is virtually omitted when the SSD controller 408 in the second storage device 104 refers to the SQ507. ..

FIG. 5C is a memory map that can be seen when the RAM 306 is read from the SSD controller 408 of the second storage device 104 (notification request of the command group). SQ517 is a virtual memory map that can be seen only when SQ507 is read from SSD controller 408 (notification request of command group).

FIG. 4 is a detailed block diagram of the first storage device 103 and the second storage device 104.

The first storage device 103 includes an SSD controller 401, a PCIe-IF402, a DRAM 403, and a NAND FLASH 404. Further, the first storage device 103 is connected to the bridge circuit 102 via the PCIe-IF402. Further, the second storage device also has the same configuration as the first storage device.

The SSD controller 401 is equipped with a processor that processes firmware executed in the first storage device, a DRAM controller that controls DRAM 403, and a NAND FLASH controller that controls NAND FLASH 404.

The PCIe-IF402 uses the bridge device 102 as a RootComplex to exchange data to be transmitted and received to and from the bridge device 102. The SQTD 405 and CQHD 406 are registers configured to be accessible from the sub CPU 301, and are configured in the PCIe IF 402 in this example.

The SQTD 405 is used when the sub CPU 301 of the bridge device 102 notifies the first storage device 103 of the Doorbell. The CQHD 406 is referred to when the SSD controller 408 of the first storage device 103 stores the execution result of the NVMe command.

The DRAM 403 is a memory for caching, and temporarily holds the data before writing the data to the NAND FLASH (registered trademark) 404.

The NAND FLASH 404 is a device that actually records data, and data is read and written.

The SSD controller 408 is equipped with a processor that processes firmware executed in the second storage device, a DRAM controller that controls DRAM 409, and a NAND FLASH controller that controls NAND FLASH 410.

The PCIe-IF407 uses the bridge device 102 as a RootComplex to exchange data to be transmitted and received to and from the bridge device 102. The SQTD411 and the CQHD412 are registers configured to be accessible from the sub CPU 301, and in this example, they are configured in the PCIe IF 402.

The SQTD 411 is used when the sub CPU 301 of the bridge device 102 notifies the second storage device 104 of the Doorbell. The CQHD412 is referred to when the SSD controller 408 of the second storage device 104 stores the execution result of the NVMe command.

The DRAM 409 is a memory for caching, and temporarily holds the data before writing the data to the NAND FLASH 410.

The NAND FLASH 410 is a device that actually records data, and data is read and written.

FIG. 6 is a detailed view of the bridge device 102 for explaining the function of the memory map conversion means 309. Since the operation in which the SQ507 is read (command group notification request) is described in the figure, the ROM 305 is omitted.

The PCIe-IF304 starts the read address phase of the AXI protocol in response to the notification request of the command group from the SSD controller 408.

Here, as an example, only the ARADDR signal indicating the ARID and the address that identifies the AXI master is shown. The AIC outputs the ARID and ARADDR from the PCIe-IF304 to the memory map conversion means 309.

The processing performed by the sequencer is shown in the flowchart of FIG. Here, as an example, a sequencer relating to a notification request of a command group from the second storage device 104 to the SQ517 will be described.

The switch 604 selects ARADDR as it is at the time of access such as when the sub CPU 301 stores the NVMe command in the SQ507 and when the sub CPU 301 reads the NVMe command of the SQ507 from the SSD controller 401. That is, the address map conversion means functions only when the SSD controller 408 of the second storage device 104 requests the notification of the command group to the SQ507.

Therefore, only the operation when the sequencer 601 detects the notification request of the command group from the SSD controller 408 to the SQ507 will be described with the flowchart of FIG. The sequencer 601 that has received the ARID and ARADDR detects that the command group is a notification request from the ARID and ARADDR to the SQ507 by the SSD controller 408, and pushes the switch 604 to the output side of the adder 603.

In step S801, the switch 604 outputs the output of the adder 603 to the RAM 306 as the address signal addr of the APB bus, and the sequencer 601 instructs the APB read access (notification request of a certain command). In S802, the RAM 306 returns the data stored in the addr as the read data signal rdata of the APB bus (indicated in lowercase to distinguish it from AXI).

In S803, the sequencer 601 receives the returned rdata and detects the Opcode 702 (code data).

In S804, the type of NVMe command is determined. If the type of NVMe command is read, the process proceeds to S806, and the offset register 602 is added by the size of one NVMe command. Then, it returns to S801 and instructs RAM306 of APB read access (notification request of the next command).

Here, the Opcode 702 is arranged at a predetermined position in the NVMe command as shown in the format 700 of the NVMe command in FIG. The NVMe command 700 shown in FIG. 7 has fields for Command Indicator (hereinafter referred to as CID) 701, Opcode 702 (hereinafter referred to as OPC), and PRP Entry 703. CID701 is a unique number added to the NVMe command.

OPC702 is an identifier indicating the type of NVMe command, and is an identifier such as Write or Read. The RPR Entry 703 stores information indicating a transfer source address or a transfer destination address.

Returning to the description of FIG. In step S805, when the type of NVMe command is write, the read data is returned to AIC321 and the AXI read is terminated.

The function of the memory map conversion means will be described with reference to FIG. Here, as an example, when the SQ507 is read from the SSD controller 408 (notification request of the command group), the appearance of the SQ517 virtually will be described.

Each line from S901 to S905 in FIG. 9 shows the value of the signal or the register in each step. ARDR is a read address output by AIC321, but for simplicity, it indicates a value in which the beginning of SQ507 is 0 and the size of the NVMe command is a unit. Further, in FIG. 9, the switch 604 always falls to the output side of the adder 603.

As S901, the SSD controller 408 of the second storage device 104 leads the head of the SQ507 (ARADDR = 0). Here, since the offset register value is initialized to 0 as described later, the head of SQ507 is actually read (addr = 0). The returned data includes Opcode702, and since the NVMe command with addr = 0 is a write, rdata returns the contents of the first write command (W0). In the case of write, the sequencer 601 returns rdata as RDATA to AIC321 and ends the read transfer of AXI.

Next, as S902, the SSD controller 408 of the second storage device 104 reads the next NVMe command of SQ507 (ARADDR = 1). Since the offset register value is 0 here, the second NVMe command of SQ507 is read (addr = 1 + 0 = 1).

Since the second NVMe command is R0, rdata returns the contents of R0. In the case of reading, the sequencer 601 adds the value of the offset register 602 to 1, and instructs the RAM 306 as S902 for a notification request. At this time, since addr = 1 + 1 = 2, RAM 306 returns the third NVMe command of SQ507 as rdata. Since the third NVMe command is W1, rdata returns the contents of W1. In the case of write, the sequencer 601 returns rdata as RDATA to AIC321 and ends the read transfer of AXI.

Next, as S904, the SSD controller 408 of the second storage device 104 reads the next NVMe command of SQ507 (ARADDR = 2). Since the offset register value is 1, the fourth NVMe command of SQ507 is read (addr = 2 + 1 = 3). Since the fourth NVMe command is R1, rdata returns the contents of R1. In the case of read, the sequencer 601 adds the value of the offset register 602 to 2.

Instruct RAM 306 to request notification as S905. At this time, since addr = 2 + 2 = 4, the RAM 306 returns the fifth NVMe command of SQ507 as rdata. Since the fifth NVMe command is W2, rdata returns the contents of W2. In the case of write, the sequencer 601 returns rdata as RDATA to AIC321 and ends the read transfer of AXI.

Summarizing S901 to S904, the SSD controller 408 of the second storage device 104 read three NVMe commands from the beginning of SQ507, and could read NVMe commands corresponding to W0, W1, and W2. That is, the sequence of NVMe commands shown in SQ517 of FIG. 5 can be seen.

Next, the operation in the mirroring system of the embodiment will be described. FIG. 10 is a flowchart illustrating a flow executed by the sub CPU 301 of the bridge device 102 while the mirroring system is operating.

In S1000, HC101 initializes SQ501 and CQ502 by issuing an admin command to the bridge device 102. Further, the sub CPU 301 of the bridge device 102 receives an admin command and issues an admin command to both the first storage device 103 and the second storage device 104 to initialize the SQ501, CQ508, and CQ510. Here, the SQ507 is initialized as a common SQ area for both the first storage device 103 and the second storage device 104. CQ508 is initialized as an NVMe command execution result notification area for the first storage device 103, and CQ510 is initialized as an NVMe command execution result notification area for the second storage device 104. Further, the sub CPU 301 initializes the offset register 602 to 0 as S1000.

Next, the HC101 stores the NVMe command group to be executed by the storage device in the SQ501. Then, in order to notify the bridge device 102 that the NVMe command has been stored, the value of the New Tail point 504 of the SQ 205 is written in the SQTD 307 in the bridge device 102.

In S1001, the sub CPU 301 waits for the update of SQDT307 in S1001. When the sub CPU 301 receives the Doorbell notification, it transitions to S1002.

In S1002, the SQ501 of the RAM 204 is read out and stored in the SQ507 of the RAM 306. Next, in S1003, the sub CPU 301 calculates a value to be written to SQTD405 and SQTD411. Since all NVMe commands are executed for the first storage device 103, the value obtained by adding the sizes of five NVMe commands to the beginning of SQ507 is the New Tail 514. Further, the value obtained by adding the sizes of three NVMe commands to the beginning of SQ507 or SQ517 is the New Tail 522.

Next, in S1004, the sub CPU 301 overwrites the SQTD 405 with the value of New Tail 512 to perform the Doorbell notification. As a result, the SSD controller 401 of the first storage device 103 starts processing the NVMe command group of the SQ507.

Next, in S1005, the sub CPU 301 overwrites the SQTD411 with the value of New Tail 522 and performs a Doorbell notification. As a result, the SSD controller 408 of the second storage device 104 starts processing the NVMe command group of the SQ517.

After that, the sub CPU 301 waits for an NVMe command processing completion interrupt from the first storage device 104 and the second storage device 104 in S1006 and S1007.

When a completion interrupt is received from both storage devices via the PCIe-IF, the predetermined areas of CQ508 and CQ510 in the RAM 306 are inspected, and the NVMe command execution result is written in the CQ 308.

Next, S1009 issues a PCIe-IF302NVMe command execution completion notification interrupt.

In this embodiment, the NVMe command group on the HC 101 is used as a new NVMe command group used in the first storage device 103 and the second storage device 104 via the bridge device 102 by the method shown in FIGS. 1 to 10. Generate and notify each storage device. This enables a mirroring system that can execute necessary instructions for each storage device.

Note that the mirroring referred to in this embodiment indicates a mirror control in which the same data is stored in a plurality of storage devices. Specifically, by implementing the memory map conversion means 309, it is possible to make the read command performed only by the first storage device 103 of the mirroring system.

Further, in this embodiment, the case where the command type is read and the case where the command type is write are shown, but the present invention is not limited to this. For example, a command that performs the same processing in a plurality of storage devices may be processed in the same manner as a write in the embodiment, and a command that may be processed in only one storage device may be processed in the same manner as the read in the embodiment. good.

(Other embodiments)
Although various examples and embodiments of the present invention have been described above, the gist and scope of the present invention are not limited to the specific description in the present specification.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

101 HC
103 1st storage device 104 2nd storage device 301 Sub CPU
306 RAM
306 Memory map conversion means

Claims (12)

A control device that communicates with the host device and communicates with the non-volatile first semiconductor storage device and the non-volatile second semiconductor storage device.
A holding means for holding a first type command group including a first type command and a second type command received from the host device, and a holding means.
It has a first semiconductor storage device and a control means for mirror-controlling the second semiconductor storage device.
When the control means receives a command group read request from the first semiconductor storage device, the control means causes the first semiconductor storage device to read the first command group, and the command group read request from the second semiconductor storage device. Is received, the first type of command in the first command group is not read by the second semiconductor storage device, and the second type of command is read by the second semiconductor storage device. Control device. When the control means receives the notification request of the command group from the second semiconductor storage device, the control means notifies the second semiconductor storage device of the second type of command, and the first type of command is the second semiconductor storage. The control device according to claim 1, wherein the device is not notified. The claim characterized in that, when the control means receives a notification request of a command group from the first semiconductor storage device, the second type of command and the first type of command are notified to the second semiconductor storage device. Item 2. The control device according to Item 1 or 2. Further, it has a determination means for determining the type of the command included in the first command group.
The claim means that the determination means reads a command included in the first command group from the holding means, and determines the type of the read command based on the code data included in the read command. The control device according to any one of 1 to 3. One of claims 1 to 4, wherein the control means notifies the first semiconductor storage device and the second semiconductor storage device of a command stored in a queue held by the holding means. The control device described in. The claim is characterized in that when a command stored in a queue held in the holding means is notified to the second semiconductor storage device, the notification is performed except for the queue in which the first type of command is stored. 5. The control device according to 5. The control device according to any one of claims 1 to 6, wherein the first type of command is a read command for reading data from a semiconductor storage device. The control device according to any one of claims 1 to 7, wherein the second type of command is a write command for writing data to a semiconductor storage device. The control device according to any one of claims 1 to 8, wherein the first semiconductor storage device and the second semiconductor storage device are SSDs corresponding to NVMe. A first type of command including a first type command and a second type command received from the host device, communicating with the host device and communicating with the non-volatile first semiconductor storage device and the non-volatile second semiconductor storage device. It is a control method of a control device having a memory for holding a command group and having the first semiconductor storage device and the second semiconductor storage device mirror-controlled.
A step of receiving a command group read request from the first semiconductor storage device and the second semiconductor storage device, and
When the read request of the command group is received from the first semiconductor storage device, the first command group is read by the first semiconductor storage device, and when the read request of the command group is received from the second semiconductor storage device, the first command group is read. It is characterized by having a step of causing the second semiconductor storage device to read the second type of command without causing the second semiconductor storage device to read the first type of command in one command group. Control device to do. A program for causing a computer to execute the control method according to claim 10. A computer-readable storage medium containing the program according to claim 11.

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