JP2021170675A5 - - Google Patents
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- JP2021170675A5 JP2021170675A5 JP2021123462A JP2021123462A JP2021170675A5 JP 2021170675 A5 JP2021170675 A5 JP 2021170675A5 JP 2021123462 A JP2021123462 A JP 2021123462A JP 2021123462 A JP2021123462 A JP 2021123462A JP 2021170675 A5 JP2021170675 A5 JP 2021170675A5
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- plate
- insulating layer
- package
- substrate
- semiconductor device
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Description
本発明の一つの態様の半導体素子用パッケージは、半導体素子の搭載部を含む第１上面と、前記第１上面の反対側に位置した第１下面とを有する基板と、第２上面および前記第２上面の反対側に位置した第２下面を有するとともに前記第１上面に位置した絶縁板と、前記第２上面に位置する第１配線と、を含む入出力端子と、前記基板と間を空けて、前記第２下面に位置した板状体と、を備えており、下面視において、前記板状体の内縁と前記板状体の内縁と向かい合って位置した前記基板の内縁との間の距離は、前記板状体の外縁と前記入出力端子の外縁との間の距離よりも大きい。 The package for a semiconductor element according to one aspect of the present invention includes a substrate having a first upper surface including a mounting portion of the semiconductor element, a first lower surface located on the opposite side of the first upper surface, a second upper surface, and the first surface. 2. A space between an input / output terminal having a second lower surface located on the opposite side of the upper surface and including an insulating plate located on the first upper surface and a first wiring located on the second upper surface, and the substrate. The plate-shaped body located on the second lower surface thereof is provided, and the distance between the inner edge of the plate-shaped body and the inner edge of the substrate located facing the inner edge of the plate-shaped body in the bottom view. Is greater than the distance between the outer edge of the plate-like body and the outer edge of the input / output terminal .
また、本発明の半導体装置は、上記構成の半導体素子用パッケージと、前記基板の前記 搭載部に搭載された半導体素子と、を備える。 Further, the semiconductor device of the present invention includes a semiconductor device package having the above configuration and a semiconductor device mounted on the mounting portion of the substrate.
Claims (7)
第２上面および前記第２上面の反対側に位置した第２下面を有するとともに前記第１上面に位置した絶縁板と、前記第２上面に位置する第１配線と、を含む入出力端子と、
前記基板と間を空けて、前記第２下面に位置した板状体と、を備えており、
下面視において、前記板状体の内縁と前記板状体の内縁と向かい合って位置した前記基板の内縁との間の距離は、前記板状体の外縁と前記入出力端子の外縁との間の距離よりも大きい半導体素子用パッケージ。 A substrate having a first upper surface including a mounting portion of a semiconductor element and a first lower surface located on the opposite side of the first upper surface .
An input / output terminal having a second upper surface and a second lower surface located on the opposite side of the second upper surface, and including an insulating plate located on the first upper surface and a first wiring located on the second upper surface .
It is provided with a plate-shaped body located on the second lower surface with a gap from the substrate .
In bottom view, the distance between the inner edge of the plate-like body and the inner edge of the substrate located facing the inner edge of the plate-like body is between the outer edge of the plate-like body and the outer edge of the input / output terminal. Package for semiconductor devices larger than distance .
前記板状体の角部が曲線部を有している請求項１に記載の半導体素子用パッケージ。 In a plan view, the plate-like body has a rectangular shape.
The package for a semiconductor device according to claim 1 , wherein the corner portion of the plate-shaped body has a curved portion .
前記外方領域の外側の角部は切欠きを有している請求項１～請求項３のいずれか１項に記載の半導体素子用パッケージ。 In a plan view, the insulating plate has a rectangular outer region located outside the first upper surface.
The package for a semiconductor device according to any one of claims 1 to 3, wherein the outer corner portion of the outer region has a notch .
前記第３の絶縁層の外縁は、前記板状体の内縁よりも内側に位置するとともに前記基板の外縁よりも外側に位置している請求項１～請求項４のいずれか１項に記載の半導体素子用パッケージ。 The insulating plate includes a first insulating layer, a second insulating layer laminated on the first insulating layer so as to be located inside the outer end of the first insulating layer, and the first insulating layer. It has a third insulating layer laminated on the second insulating layer so as to be located inside the outer end of the insulating layer 2.
The aspect according to any one of claims 1 to 4 , wherein the outer edge of the third insulating layer is located inside the inner edge of the plate-like body and outside the outer edge of the substrate. Package for semiconductor devices.
前記基板の前記搭載部に搭載された半導体素子と、を備える半導体装置。 The semiconductor device package according to any one of claims 1 to 6.
A semiconductor device including a semiconductor element mounted on the mounting portion of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021123462A JP7196249B2 (en) | 2018-03-23 | 2021-07-28 | Packages for semiconductor devices and semiconductor devices |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018056149A JP6923474B2 (en) | 2018-03-23 | 2018-03-23 | Semiconductor device packages and semiconductor devices |
| JP2021123462A JP7196249B2 (en) | 2018-03-23 | 2021-07-28 | Packages for semiconductor devices and semiconductor devices |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018056149A Division JP6923474B2 (en) | 2018-03-23 | 2018-03-23 | Semiconductor device packages and semiconductor devices |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021170675A JP2021170675A (en) | 2021-10-28 |
| JP2021170675A5 true JP2021170675A5 (en) | 2022-04-13 |
| JP7196249B2 JP7196249B2 (en) | 2022-12-26 |
Family
ID=68106903
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018056149A Active JP6923474B2 (en) | 2018-03-23 | 2018-03-23 | Semiconductor device packages and semiconductor devices |
| JP2021123462A Active JP7196249B2 (en) | 2018-03-23 | 2021-07-28 | Packages for semiconductor devices and semiconductor devices |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018056149A Active JP6923474B2 (en) | 2018-03-23 | 2018-03-23 | Semiconductor device packages and semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (2) | JP6923474B2 (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4480598B2 (en) * | 2004-02-26 | 2010-06-16 | 京セラ株式会社 | Electronic component storage package and electronic device |
| JP2006128267A (en) * | 2004-10-27 | 2006-05-18 | Kyocera Corp | I / O terminal, electronic component storage package and electronic device using the same |
| JP2006128261A (en) * | 2004-10-27 | 2006-05-18 | Kyocera Corp | I / O terminal, electronic component storage package and electronic device using the same |
| JP2007005636A (en) * | 2005-06-24 | 2007-01-11 | Kyocera Corp | Input / output terminal and electronic component storage package and electronic device |
| JP2009158511A (en) * | 2007-12-25 | 2009-07-16 | Sumitomo Metal Electronics Devices Inc | Input/output terminal and package for housing semiconductor device |
| WO2013141013A1 (en) * | 2012-03-22 | 2013-09-26 | 京セラ株式会社 | Element-accommodating package |
| JP6853034B2 (en) * | 2015-12-25 | 2021-03-31 | 京セラ株式会社 | Optical semiconductor device storage package and optical semiconductor device |
-
2018
- 2018-03-23 JP JP2018056149A patent/JP6923474B2/en active Active
-
2021
- 2021-07-28 JP JP2021123462A patent/JP7196249B2/en active Active
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