JP2021166253A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device in which the dielectric breakdown in a passivation film can be prevented even if surge flows in an anode wire of pn-junction diode.SOLUTION: A semiconductor device 1 includes a protection element, a first separation region 3A, and a second separation region 3B. The protection element includes a pn-junction diode. The first separation region 3A electrically divides an active layer 22 into a first active layer region 11 where the pn-junction diode is disposed, and a second active layer region 12 where the pn-junction diode is not disposed. The second separation region 3B divides the second active layer region 12 into a third active layer region 12A that is adjacent to the first active layer region 11 through the first separation region 3A, and a fourth active layer region 12B that is adjacent to the third active layer region 12A without being adjacent to the first active layer region 11. Additionally, the potentials of the first separation region 3A and the third active layer region 12A are made inconstant, and the potentials of a supporting substrate 20 and the fourth active layer region 12B are set to be ground potentials.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device, and more particularly to an effective technique applied to a semiconductor device provided with a protective element.

Patent Document 1 discloses a pn junction diode formed on a p-type SOI (Silicon On Insulator) substrate having a trench separation structure.

The p-type SOI substrate is composed of a support substrate, an embedded oxide film, a p-type active layer, a passivation film that functions as an insulating layer, and a wiring layer in this order from the bottom layer, and a pn junction diode is formed on the p-type active layer. Has been done.

In such a p-type SOI substrate, the support substrate, the trench, and the adjacent region separated by the trench and adjacent to the p-type active layer region where the pn junction is formed are set to the ground potential, and the depletion layer generated on the pn junction surface is set. The withstand voltage of the pn junction diode is improved by controlling the spread of the pn junction diode.

However, when a surge flows into the anode wiring of the pn junction diode located in the wiring layer, the potential difference between the anode wiring laminated via the passivation film and the adjacent region exceeds the insulation breakdown voltage of the passivation film, causing dielectric breakdown of the passivation film. I have something to do.

Japanese Unexamined Patent Publication No. 2020-13902

In consideration of the above facts, the present invention provides a semiconductor device capable of preventing dielectric breakdown in the passivation film even when a surge flows into the anode wiring of the pn junction diode.

The semiconductor device according to the first aspect of the present invention is arranged in an active layer of a substrate in which an active layer is formed on a support substrate via an insulating layer, and includes a pn junction diode between an anode region and a cathode region. The protective element and the pn junction diode are arranged in the active layer so as to be separated, and the active layer is electrically placed in the first active layer region in which the pn junction diode is arranged and the second active layer region in which the pn junction diode is not arranged. The first separation region to be separated, the second active layer region, the third active layer region adjacent to the first active layer region via the first separation region, and the third active layer region not adjacent to the first active layer region. A second separation region that separates into a fourth active layer region adjacent to the active layer region is provided, the potentials of the first separation region and the third active layer region are set to indefinite potentials, and the potentials of the support substrate and the fourth active layer region are set. Let be the ground potential.

According to the semiconductor device according to the first aspect, since the potentials of the first separation region and the third active layer region are set to indefinite potentials, even if a surge flows into the anode wiring connected to the anode region, the electric field effect The potentials of the first separation region and the third active layer region follow the surge voltage. Therefore, the potential difference between the anode wiring and the first separation region and the third active layer region is suppressed to be lower than when the potentials of the first separation region and the third active layer region are set to the ground potential. As a result, it is possible to suppress the occurrence of dielectric breakdown due to the potential difference between the anode wiring and the first separation region and the third active layer region. Further, the potentials of the support substrate and the fourth active layer region are set to the ground potential. Therefore, in a normal state where the surge does not flow into the anode wiring, the potential of the first separation region and the potential of the third active layer region are both induced to be ground potentials by the coupling effect, so that the pn junction diode The electrical properties of the are maintained.

In the semiconductor device of the second aspect, the second separation region is arranged at a position where the anode wiring electrically connected to the anode region does not extend to the upper layer of the fourth active layer region.

According to the semiconductor device according to the second aspect, the second separation region is arranged at a position where the anode wiring is not laminated on the upper layer of the fourth active layer region. Therefore, it is possible to reduce the influence of the surge on the element formed in the fourth active layer region as compared with the case where the surge flows into the anode wiring which is also laminated on the upper layer of the fourth active layer region.

In the semiconductor device of the third aspect, the second separation region is located at a position separated from the anode wiring by 20 μm or more along the stretching direction of the anode wiring extending from the upper layer of the first active layer region to the upper layer of the third active layer region. Deploy.

According to the semiconductor device according to the third aspect, the closer the second separation region is to the anode wiring, the more elements can be formed on one SOI substrate, but the distance from the anode wiring is intentionally 20 μm or more. The second separation region is arranged at the above position. If the second separation region is too close to the anode wiring, when a surge flows into the anode wiring, the potential difference between the third active layer region and the fourth active layer region exceeds the dielectric strength of the second separation region, and the second separation region May cause dielectric breakdown. However, by arranging the second separation region at a position 20 μm or more away from the anode wiring, even if a surge flows into the anode wiring, in addition to the passivation film, dielectric breakdown of the second separation region can be suppressed. Will be able to.

In the semiconductor device of the fourth aspect, the corners of the wiring pattern of the anode wiring are formed so as to be obtuse.

When a surge flows into the anode wiring, the electric field density at the corner of the anode wiring becomes higher than the electric field density of other parts of the anode wiring. That is, by making the angle of the wiring pattern of the anode wiring obtuse, the electric field density generated at the corner of the wiring pattern of the anode wiring becomes lower than the electric field density generated at the corner of the wiring pattern composed of an angle of 90 degrees or less. Therefore, according to the semiconductor device according to the fourth aspect, as compared with the case where the wiring pattern of the anode wiring has an angle formed by an angle of 90 degrees or less, the anode wiring and the anode wiring are directly under the anode wiring due to the inflow of surge. The potential difference from the located third active layer region can be reduced.

According to the present invention, it is possible to provide a semiconductor device capable of preventing dielectric breakdown in the passivation film even when a surge flows into the anode wiring of the pn junction diode.

It is sectional drawing which shows schematic | composition example of the main part of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows an example of the potential distribution in a semiconductor device when a surge voltage is applied to the anode wiring of a semiconductor device. It is a graph which shows the change example of the potential difference between two points in a semiconductor device when a surge voltage is applied to the anode wiring of a semiconductor device. It is a graph which shows the change example of the 2nd potential difference when the distance from the end of the anode wiring is changed.

Hereinafter, the present embodiment will be described with reference to FIGS. 1 to 4. The same components are given the same reference numerals throughout the drawings, and duplicate description will be omitted.

FIG. 1 is a diagram showing an example of a cross-sectional structure diagram when the semiconductor device 1 according to the present embodiment is cut in the X-axis direction (referred to as the thickness direction). The cross-sectional structure diagram shown in FIG. 1 schematically shows a configuration example of a main part of the semiconductor device 1.

The semiconductor device 1 is mainly composed of a substrate (semiconductor pellet or semiconductor chip) 2. An SOI substrate is used for the substrate 2. That is, the substrate 2 has a structure in which a conductive support substrate 20, an insulating layer 21 formed on the support substrate 20, and an active layer 22 formed on the insulating layer 21 are sequentially laminated.

The support substrate 20 is formed of, for example, a silicon single crystal substrate, and is set to a p-type having a low impurity density. The support substrate 20 may be set to a p-type having a medium impurity density or a high impurity density, or may be set to an n-type.

The insulating layer 21 is formed as an embedded oxide film (BOX: Buried Oxide), specifically, is formed of a silicon oxide film. The insulating layer 21 is formed by injecting oxygen into the support substrate 20 by using, for example, an ion implantation method, and partially oxidizing the silicon inside the support substrate 20.

The active layer 22 is formed of a silicon single crystal layer like the support substrate 20, and is set to a p-type having a low impurity density. The active layer 22 is formed by using a part of the surface layer of the support substrate 20, and is electrically separated from the support substrate 20 with the insulating layer 21 as a boundary by forming the insulating layer 21.

A plurality of elements including, for example, a diode are formed in the active layer 22. Specifically, an n-type semiconductor region 4 is formed in the active layer 22, and a pn junction that functions as a protective element by a pn junction between the active layer 22 as an anode region and the n-type semiconductor region 4 as a cathode region. A diode is formed.

The n-type semiconductor region 4 is formed by introducing n-type impurities from the surface of the active layer 22 into the inside using an ion implantation method or a solid-phase diffusion method to activate the n-type impurities. The impurity density of the n-type semiconductor region 4 is set higher than the impurity density of the active layer 22. Further, the pn junction depth with the active layer 22 in the n-type semiconductor region 4 is set to be shallower than the length of the active layer 22 in the thickness direction, that is, the thickness of the active layer 22.

Further, on the surface of the active layer 22 as an anode region, a p-type semiconductor region 5 used as a contact region of the same conductive type as the active layer 22 is formed. The p-type semiconductor region 5 is set to an impurity density higher than the impurity density of the n-type semiconductor region 4. Further, the depth of the p-type semiconductor region 5 is set to be shallower than, for example, the pn junction depth of the n-type semiconductor region 4. By forming the p-type semiconductor region 5 in the active layer 22, the contact resistance between the active layer 22 as an anode region and the wiring electrically connected to the active layer 22 can be reduced. Since the p-type semiconductor region 5 is a region connecting the wiring and the active layer 22 in this way, the p-type semiconductor region 5 will be hereinafter referred to as a “contact region 5” in order to distinguish it from the active layer 22. ..

In this way, a plurality of elements such as diodes are formed on the active layer 22. Therefore, in order to eliminate the electrical influence acting between different elements, a separation region 3 that separates each element is formed in the active layer 22. In the example of the semiconductor device 1 shown in FIG. 1, a first separation region 3A, a second separation region 3B, and a third separation region 3C are formed on the active layer 22. Hereinafter, when each separation region 3 is described separately, it is described as the first separation region 3A, the second separation region 3B, and the third separation region 3C, and each separation region 3 is described without distinction. In this case, it is simply described as "separation region 3".

In the semiconductor device 1 shown in FIG. 1, the active layer 22 surrounded by the first separation region 3A and the third separation region 3C so as to include a diode formed by the pn junction of the active layer 22 and the n-type semiconductor region 4 The region of is referred to as the first active layer region 11.

The second active layer region 12, which is a region of the active layer 22 adjacent to the first active layer region 11 via the first separation region 3A, is further divided into a third active layer region 12A and a fourth active layer by the second separation region 3B. It is separated into regions 12B. That is, the third active layer region 12A is a region of the active layer 22 surrounded by the first separation region 3A and the second separation region 3B, and is adjacent to the first active layer region 11 via the first separation region 3A. doing. Further, the fourth active layer region 12B is a region of the active layer 22 adjacent to the third active layer region 12A via the second separation region 3B without being adjacent to the first active layer region 11.

The separation region 3 includes a trench 30, an insulator 31, and a conductor 32, and has a so-called trench isolation structure. That is, the separation region 3 is formed so as to separate the active layer 22 from the surface of the active layer 22 toward the surface of the insulating layer 21 along the thickness direction of the semiconductor device 1.

The trench 30 is set so that the length in the Y-axis direction (referred to as the width direction) is shorter than the length in the thickness direction of the semiconductor device 1. That is, when the separation region 3 having the trench 30 is adopted, the occupied area of the separation region 3 on the surface of the active layer 22 becomes small, so that the degree of integration of the semiconductor device 1 can be improved. The trench 30 is formed by using anisotropic etching such as reactive ion etching (RIE) in the manufacturing process of the semiconductor device 1.

The insulator 31 is arranged on the side wall of the trench 30. The insulator 31 is formed, for example, by a silicon oxide film, and the silicon oxide film is formed, for example, by using a chemical vapor deposition (CVD) method.

The conductor 32 is embedded in the trench 30 via an insulator 31. As the conductor 32, for example, a silicon polycrystalline film is used. Impurities are introduced into the silicon polycrystalline film, and the silicon polycrystalline film is adjusted to have a low resistance value.

The passivation film 10 is laminated on the active layer 22 configured as described above. The passivation film 10 is formed of, for example, a single layer of a silicon oxide film or a silicon nitride film, or a composite film in which they are laminated.

Further, the wiring layer 7 is laminated on the passivation film 10. As an example, a single-layer wiring structure is used for the wiring layer 7, but a wiring structure having two or more layers may be used. For the wiring layer 7, for example, an aluminum alloy film to which copper (Cu) and silicon (Si) are added is used.

The wiring layer 7 includes, for example, a cathode wiring 7A connected to the n-type semiconductor region 4, an anode wiring 7B connected to the contact region 5, and other elements different from the diode formed in the first active layer region 11. The external wiring 7C, which is the wiring connected to the above, is formed.

One end of the cathode wiring 7A is electrically connected to the n-type semiconductor region 4 through a connection hole 13A formed through the passivation film 10 in the thickness direction. The other end of the cathode wiring 7A extends the upper layer of the first active layer region 11 via the passivation film 10 and is connected to an internal circuit (not shown) across the upper layer of the third separation region 3C. The upper layer of the region is a layer laminated on the region, and the range is limited to the range of the region located in the lower layer.

Further, one end of the anode wiring 7B is electrically connected to the contact region 5 through the connection hole 13B, and is electrically connected to the first active layer region 11 through the contact region 5. The other end K1 of the anode wiring 7B extends the upper layer of the first active layer region 11 via the passivation membrane 10 and reaches the upper layer of the third active layer region 12A across the upper layer of the first separation region 3A. ..

In this way, the first separation region 3A is arranged at a position such that the end K1 of the anode wiring 7B protrudes from the upper layer of the first active layer region 11 and reaches the upper layer of the third active layer region 12A. Further, the second separation region 3B is provided at the boundary between the diode formed in the first active layer region 11 and the external region in which other elements and the like are formed. Specifically, the second separation region 3B is arranged at a position where the end portion K1 of the anode wiring 7B does not extend to the upper layer of the fourth active layer region 12B where other elements are formed. Therefore, neither element is formed in the third active layer region 12A surrounded by the first separation region 3A and the second separation region 3B.

One end of the external wiring 7C is electrically connected to the fourth active layer region 12B through the connection hole 13C.

(Action and effect of this embodiment)
In the semiconductor device 1 having the above-described configuration, the potential of the conductor 32 in the first separation region 3A and the potential of the third active layer region 12A are set to indefinite potentials, and the potentials of the support substrate 20 and the fourth active layer region 12B are set. Is set to the ground potential. The indefinite potential is a potential in a state where it is not forcibly set to any potential. Hereinafter, the potential of the conductor 32 in the first separation region 3A will be simply referred to as the “potential of the first separation region 3A”.

When a surge flows into the anode wiring 7B of the semiconductor device 1 in which the potential is set in this way, a potential difference is generated between the anode wiring 7B and the active layer 22 via the passivation film 10. If this potential difference (referred to as "surge inflow potential difference") exceeds the withstand voltage of the passivation film 10, dielectric breakdown will occur in the passivation film 10. However, since the potential of the first separation region 3A and the potential of the third active layer region 12A that are in contact with the anode wiring 7B via the passivation film 10 are set to indefinite potentials, even if a surge flows into the anode wiring 7B. , Each potential follows the surge voltage due to the electric field effect.

Conventionally, since the second separation region 3B is not arranged in the semiconductor device 1, only the first active layer region 11 and the second active layer region 12 exist in the active layer 22, and the potential of the first separation region 3A, The potential of the second active layer region 12 including the third active layer region 12A was set to the ground potential. Therefore, in the semiconductor device 1 according to the present embodiment, the surge inflow potential difference is suppressed as compared with the case where the potential of the first separation region 3A and the potential of the second active layer region 12 are set to the ground potentials, respectively. Will be.

Since the electric field density generated by the inflow of the surge tends to increase toward the corner of the anode wiring 7B, for example, at the end K1 of the anode wiring 7B located in the upper layer of the third active layer region 12A, another anode wiring 7B is present. A higher voltage is applied than the part. However, since the potential of the third active layer region 12A is an indefinite potential, the potential of the third active layer region 12A also rises with the inflow of the surge. Therefore, the surge inflow potential difference at the end K1 of the anode wiring 7B, which is more likely to cause dielectric breakdown than other parts, is suppressed.

On the other hand, the potentials of the support substrate 20 and the fourth active layer region 12B adjacent to the first separation region 3A and the third active layer region 12A, respectively, are set to the ground potential. Therefore, in a normal state in which the surge does not flow into the anode wiring 7B, the potential of the first separation region 3A and the potential of the third active layer region 12A are induced to be ground potentials by the coupling effect. , The electrical characteristics of the diode will be maintained.

(simulation result)
FIG. 2 is a diagram showing an example of the potential distribution in the semiconductor device 1 when a surge voltage is applied to the anode wiring 7B of the semiconductor device 1 shown in FIG. The potential distribution of the semiconductor device 1 shown in FIG. 2 shows the potential distribution between the points Y1 to Y2 along the width direction of the semiconductor device 1 of FIG.

In FIG. 2, a portion closer to white indicates a higher voltage magnitude, and a portion closer to black indicates a lower voltage magnitude. Since the surge voltage applied to the anode wiring 7B is a negative voltage, a high voltage means that the voltage is high in the negative electrode direction. Further, the distance L is the second from the end K1 of the anode wiring 7B along the width direction of the semiconductor device 1 with reference to the position of the end K1 of the anode wiring 7B located in the upper layer of the third active layer region 12A. It represents the distance to the center of the separation region 3B.

Since the surge voltage is applied to the anode wiring 7B, the region of the highest voltage is distributed around the anode wiring 7B, and as the distance from the anode wiring 7B increases, the applied voltage decreases as the surge voltage flows in. Is shown by FIG.

FIG. 3 is a graph showing an example of a change in the potential difference between two points in the semiconductor device 1 when a surge voltage is applied to the anode wiring 7B of the semiconductor device 1. The horizontal axis of FIG. 3 represents the elapsed time since the surge voltage was applied to the anode wiring 7B, and the vertical axis represents the voltage.

In FIG. 3, the waveform 40 shows the potential difference between the end portion K1 of the anode wiring 7B and the point K2 of the surface portion of the third active layer region 12A located immediately below the end portion K1 of the anode wiring 7B (“first potential difference”). It represents the time change of). The waveform 41 is adjacent to the second separation region 3B and adjacent to the point K3 of the surface portion of the third active layer region 12A and the second separation region 3B, and is adjacent to the surface portion of the fourth active layer region 12B. It represents the time change of the potential difference (referred to as "second potential difference") from the point K4. The waveform 42 represents the time change of the potential difference between the potential of the end K1 of the anode wiring 7B and the ground potential (for example, the potential of the support substrate 20). The threshold value 43 represents the dielectric strength (-1500V) of the passivation film 10, and the threshold value 44 represents the dielectric strength (-1000V) of the insulator 31 in the second separation region 3B.

As described above, conventionally, the second separation region 3B is not arranged in the active layer 22, and the potential of the first separation region 3A and the potential of the second active layer region 12 are both set to the ground potential. Therefore, when a surge voltage is applied to the anode wiring 7B, the potential difference between the anode wiring 7B and the first separation region 3A and the second active layer region 12 shows a change as shown by the waveform 42. In this case, since the peak voltage of the waveform 42 exceeds the threshold value 43, dielectric breakdown of the passivation film 10 occurs.

On the other hand, in the semiconductor device 1 according to the present embodiment, even if a surge voltage is applied to the anode wiring 7B, the peak voltage of the first potential difference is suppressed to the threshold value 43 or less, so that the dielectric breakdown of the passion film 10 is broken. Can be seen that does not occur. Further, since the peak voltage of the second potential difference is also suppressed to the threshold value 44 or less, it can be seen that dielectric breakdown of the insulator 31 in the second separation region 3B does not occur.

That is, a second separation region 3B is provided, a third active layer region 12A having an indefinite potential is provided between the first active layer region 11 and the fourth active layer region 12B, and the first separation region 3A is also set to an indefinite potential. As a result, the semiconductor device 1 in which the dielectric breakdown of the passivation film 10 is unlikely to occur can be obtained.

As described above, since the electric field density generated by the inflow of surge tends to increase toward the corner of the anode wiring 7B, the end K1 of the anode wiring 7B has a higher voltage than the other parts of the anode wiring 7B. It is applied. Further, the electric field density increases as the angle of the anode wiring 7B becomes acute. Therefore, when the anode wiring 7B is formed with a pattern wiring cut so that the angle is obtuse, the first potential difference can be suppressed to be low with respect to a surge voltage of the same magnitude. For the same reason, the corner of the wiring pattern of the anode wiring 7B may be formed by a curve having a radius of curvature as large as possible.

The shorter the distance L in FIG. 2, the more elements can be formed on one SOI substrate. However, if the second separation region 3B is brought too close to the anode wiring 7B, it is conceivable that dielectric breakdown of the insulator 31 in the second separation region 3B will occur when a surge voltage is applied to the anode wiring 7B.

On the other hand, FIG. 4 is a graph showing an example of a change in the peak voltage of the second potential difference when the distance L is changed. According to FIG. 4, when the measured values of adjacent peak voltages are connected by a straight line, the peak voltage exceeds the threshold value 44 when the distance L is less than 20 μm, and the peak voltage is suppressed to the threshold value 44 or less when the distance L is 20 μm or more. It can be confirmed that there is a tendency to be affected. Therefore, 20 μm from the end K1 of the anode wiring 7B along the stretching direction of the anode wiring 7B extending from the upper layer of the first active layer region 11 to the upper layer of the third active layer region 12A, that is, the width direction of the semiconductor device 1. It is preferable to arrange the second separation region 3B at a position separated from the above.

Although the present invention has been described above using the embodiments, the present invention is not limited to the scope described in the embodiments. Various changes or improvements can be made to the embodiments without departing from the gist of the present invention, and the modified or improved forms are also included in the technical scope of the present invention. For example, as shown in FIG. 1, an n-type control semiconductor region 6 is formed between the n-type semiconductor region 4 and the contact region 5, and the control semiconductor region 6 controls the spread of the depletion layer in the diode. The insulation withstand voltage of the semiconductor device 1 may be improved.

1 ... Semiconductor device, 2 ... Substrate, 3 ... Separation area, 3A ... 1st separation area, 3B ... 2nd separation area, 3C ... 3rd separation area, 4 ... -N-type semiconductor region, 5 ... p-type semiconductor region (contact region), 6 ... control semiconductor region, 7 ... wiring layer, 7A ... cathode wiring, 7B ... anode wiring, 7C ... External wiring, 10 ... Passion membrane, 11 ... 1st active layer region, 12 ... 2nd active layer region, 12A ... 3rd active layer region, 12B ... 4th active Layer region, 13A (13B, 13C) ... connection hole, 20 ... support substrate, 21 ... insulating layer, 22 ... active layer, 30 ... trench, 31 ... insulator, 32 ... Conductor, 40 ... First potential difference waveform, 41 ... Second potential difference waveform, 42 ... Potential difference waveform between the potential at the end of the anode wiring and the ground potential, 43 ... Threshold (insulation withstand voltage of passivation film), 44 ... threshold (insulation withstand voltage of insulator), K1 ... end of anode wiring, K2 ... surface of third active layer region just below the end of anode wiring Point, K3 ... Surface point of the third active layer region adjacent to the second separation region, K4 ... Surface point of the fourth active layer region adjacent to the second separation region, L ... Width of the semiconductor device Distance from the end of the anode wiring along the direction to the second separation region

Claims (4)

A protective element arranged on the active layer of the substrate on which the active layer is formed via an insulating layer on the support substrate and including a pn junction diode between an anode region and a cathode region, and a protective element.
The active layer is arranged so as to separate the pn junction diode, and the active layer is electrically placed in a first active layer region in which the pn junction diode is arranged and a second active layer region in which the pn junction diode is not arranged. The first separation region to be separated and
The second active layer region is a third active layer region adjacent to the first active layer region via the first separation region, and the third active layer region is not adjacent to the first active layer region. A second separation region that separates into a fourth active layer region adjacent to
With
A semiconductor device in which the potentials of the first separation region and the third active layer region are indefinite potentials, and the potentials of the support substrate and the fourth active layer region are ground potentials. The semiconductor device according to claim 1, wherein the second separation region is arranged at a position where the anode wiring electrically connected to the anode region does not extend to the upper layer of the fourth active layer region. A claim in which the second separation region is arranged at a position separated from the anode wiring by 20 μm or more along the stretching direction of the anode wiring extending from the upper layer of the first active layer region to the upper layer of the third active layer region. Item 2. The semiconductor device according to item 2. The semiconductor device according to claim 2 or 3, wherein the corners of the wiring pattern of the anode wiring are formed to be obtuse.

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