JP2020088497A - Memory circuit, semiconductor device, and mobile device - Google Patents

Abstract

To provide a semiconductor device, etc. which suppresses increase of an area of a signal output circuit.SOLUTION: A memory circuit 300 includes a memory array, a word line 32, and a bit line 33. The memory array includes a plurality of memories 31 which is arranged in matrix in a first direction and a second direction orthogonal to the first direction. The word line 32 allows reading of a signal included in each of the plurality of memories 31 extended in the first direction and arranged in the first direction. The bit line 33 includes a digit line 331 connected to each of the plurality of memories 31 arranged in the second direction and an output line 332 coupled to the digit line 331 and extended in the first direction. By the word line 32 allowing to read the signal, the signal from each memory 31 corresponding to the word line 32 is transmitted to the output line 332.SELECTED DRAWING: Figure 3

Description

The present invention relates to a memory circuit, a semiconductor device and a mobile device.

2. Description of the Related Art In recent years, as image sensors mounted on mobile devices have become highly integrated, it is expected that the image sensors will be made smaller. One of the effective means is to improve the efficiency of peripheral circuits in order to miniaturize the image sensor.

For example, in Patent Document 1, selection of a bit memory holding a signal of a predetermined bit from a plurality of bit memories is commonly performed in each of the plurality of AD (Analog to Digital) conversion units. An imaging device having a selection unit has been proposed. Further, in Patent Document 2, a latch circuit including a latch unit for holding each bit signal of the digital signal of the digital signal output circuit, and a latch circuit arranged corresponding to each of the latch units and held by the corresponding latch unit. A switch that transfers a digital signal to a corresponding latch unit in an adjacent latch circuit has been proposed.

JP, 2016-103809, A JP, 2013-012966, A

In the techniques described in Patent Document 1 and Patent Document 2, when a signal is read from a memory circuit that latches a signal after AD conversion, word lines are arranged across a plurality of bit lines in the horizontal direction. Then, this word line reads the bit of the same digit among the signals acquired from the plurality of pixel arrays. Therefore, the techniques described in Patent Documents 1 and 2 need to be provided with a circuit for further rearranging and outputting the signals thus read.

The present invention has been made to solve such a problem, and an object thereof is to provide a semiconductor device or the like that suppresses an increase in the area of a signal output circuit.

The memory circuit according to the present invention has a memory array, word lines, and bit lines. The memory array has a plurality of memories arranged in a matrix in a first direction and a second direction orthogonal to the first direction. The word line extends in the first direction and makes it possible to read signals included in a plurality of memories arranged in the first direction. The bit line has a digit line connected to each of the plurality of memories arranged in the second direction and an output line connected to the digit line and extending in the first direction so that the word line can read a signal. Thus, the signal from the memory corresponding to the word line is transmitted to the output line.

With the above configuration, the word line and the bit line can be arranged in parallel in the memory circuit, so that the most significant bit or MSB (Most Significant Bit) to the least significant bit or LSB (Least Significant Bit) are collected as one word. Can be read. Therefore, a circuit for rearranging the data after reading the signals from the memory array becomes unnecessary.

According to the present invention, it is possible to provide a semiconductor device or the like that suppresses an increase in the area of a signal output circuit.

1 is a schematic configuration diagram of a semiconductor device according to a first exemplary embodiment. 3 is a configuration diagram of a memory circuit in the semiconductor device according to the first exemplary embodiment; FIG. It is a figure which shows the flow of the signal of a memory circuit. It is a timing diagram which shows an example of the signal which a memory circuit outputs. It is a timing chart of the signal which an ADC (Analog-to-Digital Converter) circuit and a memory circuit output. It is a timing diagram which shows another example of the signal which a memory circuit outputs. FIG. 6 is a diagram showing a signal output circuit in the semiconductor device according to the second exemplary embodiment. FIG. 6 is a timing chart of signals output by the semiconductor device according to the second exemplary embodiment. FIG. 4 is a configuration diagram of a memory circuit and a signal output circuit in the semiconductor device according to the second exemplary embodiment.

For clarity of explanation, the following description and drawings are appropriately omitted and simplified. In each drawing, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary.

<Embodiment 1>
Hereinafter, Embodiment 1 will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram of a semiconductor device according to the first embodiment. The semiconductor device 1 shown in the figure is an image sensor used as an imaging device together with an optical lens that forms a subject image. The semiconductor device 1 has a pixel array 10, an ADC circuit 20, a memory section 30, and a signal output circuit 40.

In FIG. 1, a two-dimensional Cartesian coordinate system is shown for convenience of understanding. The X axis is parallel to the left-right direction in the figure, and the right direction in the figure coincides with the X-axis plus direction. Further, the Y axis is parallel to the vertical direction of the figure, and the upward direction of the figure matches the Y axis plus direction. The Y-axis direction may be referred to as a first direction and the X-axis direction may be referred to as a second direction.

The pixel array 10 has at least photoelectric conversion elements 11 arranged in a matrix. The plurality of photoelectric conversion elements 11 generate electric signals from the detected light and supply the generated analog electric signals to the ADC circuit 20, respectively.

The ADC circuit 20 receives the analog electric signal from the pixel array 10 and AD-converts the received analog electric signal. The ADC circuit 20 is, for example, a single slope ADC, and the AD-converted digital signal (also referred to as a binary signal) has a preset number of bits (for example, 8 bits, 10 bits, 12 bits, or the like). The ADC circuit 20 supplies the generated binary signal to the memory unit 30.

The memory unit 30 is a storage device that stores the signal received from the ADC circuit 20 bit by bit, and is configured by, for example, SRAM (Static Random Access Memory). The memory unit 30 has a memory array in which memories that store signals in bit units are arranged in a matrix.

In the present embodiment, the memory array has N memories arranged from 1 bit to N bits in the Y-axis direction. Here, N is the number of digits of the binary signal discretized by AD conversion. That is, the ADC circuit 20 converts the analog pixel signal received from the pixel array 10 into an N-bit binary signal. Hereinafter, in the present disclosure, a binary signal obtained by discretizing an analog signal of any photoelectric conversion element 11 by AD conversion is referred to as a binary signal for one word. For example, when the binary signal after AD conversion is 10 bits, the memory unit 30 has 10 memories arranged as a binary signal for one word in the Y-axis direction. That is, in this case, N=10.

In the memory array, memories corresponding to the number of pixels are arranged in the X-axis direction. Therefore, in the memory unit 30, for example, thousands of memories are arranged in the X-axis direction. In the plurality of memories arranged in the X-axis direction in the memory array, the same digit of the binary signal is arranged.

The memory unit 30 temporarily stores the plurality of binary signals received from the ADC circuit 20 in the memory, and receives the instructions from the memory control unit (not shown) and supplies these signals to the signal output circuit 40.

The signal output circuit 40 outputs the signal received from the memory unit 30 to another circuit. At this time, the signal output circuit 40 sequentially outputs the binary signals in the order according to the arrangement of the photoelectric conversion elements so that another circuit can appropriately handle the signal.

The semiconductor device 1 is used for a mobile device such as a smartphone or a digital camera together with, for example, an optical lens. In that case, when the optical lens forms a subject image on the pixel array 10, the semiconductor device 1 converts the formed subject image into an electric signal. Further, the semiconductor device 1 converts the electric signal generated by the photoelectric conversion element into a binary signal, and outputs the converted binary signal to another circuit inside the mobile device.

Next, the memory section 30 will be further described with reference to FIG. FIG. 2 is a configuration diagram of the memory circuit in the semiconductor device according to the first embodiment. The memory unit 30 has a memory circuit 300a and a memory circuit 300b. The two-dimensional orthogonal coordinate system shown in the figure shows the same direction as in FIG.

The configuration of the memory circuit 300a will be described below. The memory circuit 300a has a plurality of memories 31 arranged in a matrix along the X axis and the Y axis, a plurality of word lines 32a, and a plurality of bit lines 33a.

The memory circuit 300a has a plurality of memories 31. The memory 31 is arranged in a matrix of K in the X-axis direction and N in the Y-axis direction. In the figure, the memory 31 shows the coordinates in the Y-axis direction and the coordinates in the X-axis direction. Explaining with a specific example, the upper left memory 31 has coordinates [1, 1]. The value on the right of the coordinate is the coordinate in the X-axis direction, and is sequentially incremented to K in the X-axis positive direction. The value on the left of the coordinate is the coordinate in the Y-axis direction, and is sequentially incremented to N in the Y-axis negative direction. That is, the lower right memory 31 of the memory circuit 300a has coordinates [N, K].

The memory circuit 300a has N memories in the Y-axis direction. The N memories 31 arranged in the Y-axis direction form a signal for one word (N bits) AD-converted by the ADC circuit 20. For example, the coordinate [1,1] is the LSB and the coordinate [N,1] is the MSB. The coordinates [1,1] may be the MSB and the coordinates [N,1] may be the LSB.

In the following description, when the above memory array is shown, it is expressed by using “row” and “column”. Specifically, the memory arranged in a straight line in the direction parallel to the X axis is expressed as one row, and the memory arranged in a straight line in the direction parallel to the Y axis is expressed as one column. For example, the same row as the memory 31 of the coordinates [1,1] is the memory of the coordinates [1,2], [1,3],..., [1,2K]. The memory in the same column as the memory 31 having the coordinates [1, 1] is the memory having the coordinates [2, 1], [3, 1],..., [N, 1]. That is, in the memory unit 30, one column constitutes a memory array for one word, and one row constitutes a memory array having the same digits. Further, when a memory column is shown, it is expressed as the first column to the 2Kth column, starting from the upper left coordinate [1, 1]. Similarly, when a row in the memory is shown, it is expressed as the 1st row to the Nth row starting from the upper left coordinate [1, 1].

The word line 32a can read signals for one word arranged in the Y-axis direction. The word line 32a extends along the column of the memory 31 so as to be adjacent to the memory 31 for one word arranged in the Y-axis direction, and the memory 31 for one word can be read. It has a switch 35. The switch 35 is, for example, a switch circuit including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). When the word line 32a receives an arbitrary read signal (also referred to as a read enable signal) from the memory control unit (not shown), the switch 35 is turned on, and the memory 31 in the on state can read the signal. .. The word line 32a receives read signals rd_en(1) to rd_en(N), which enable the memory 31 in the corresponding column to be read, from the memory control unit.

In the following description, of the plurality of word lines 32a, the word line in the first column is expressed as the word line 32a(1), and the word line 32a in the second column is expressed as the word line 32a(2). Similarly, the word line 32a in the Kth column is expressed as a word line 32a(K).

The bit line 33a transmits a signal of the readable memory 31 among the plurality of connected memories 31 to the signal output circuit 40. The bit line 33a has a digit line 331a and an output line 332a. The digit line 331a extends in the X-axis direction and is connected to each of the plurality of memories 31 arranged in the X-axis direction. For example, in the memory circuit 300a, the digit line 331a located on the uppermost side of the figure is stored in the memory 31 having coordinates [1,1], [1,2],... [1,K] for storing the LSB. Each is connected. Similarly, another digit line 331a adjacent to the Y-axis minus direction has a memory of coordinates [2,1], [2,2],..., [2,K] that stores the signal of the adjacent digit. It is connected to 31. In other words, the digit line 331a is connected to the memories 31 arranged in the same row in the memory circuit 300a.

The output line 332a is connected to the digit line 331a, extends in the Y-axis direction, and transmits the signal output from the connected memory 31 to the signal output circuit 40. The output line 332a is arranged so as to be adjacent to the word line 32a and the memory 31 arranged in the Y-axis direction. The number of output lines 332a connected to one digit line 331a is one. Therefore, the signals respectively stored in the plurality of memories 31 connected to the digit line 331a are transmitted by the common output line 332a. That is, the signals of the same digit among the plurality of binary signals are transmitted through the common single output line 332a.

The output lines 332a respectively output the signals stored in the memory 31 of the corresponding row. Specifically, the output line 332a(1) outputs the signal d_col(1). Similarly, the output line 332a(2) outputs the signal d_col(2), and the output line 332a(N) outputs the signal d_col(N).

In the following description, of the plurality of bit lines 33a, the bit line in the first row is expressed as bit line 33a(1), the bit line 33a in the second row is expressed as bit line 33a(2), Similarly, the bit line 33a in the Nth row is expressed as a bit line 33a(N). Similarly, regarding the digit line 331a and the output line 332a, the numbers corresponding to the respective lines are also shown in parentheses to indicate in which line they are arranged.

As described above, one word line 32a is adjacent to the column of the memory 31 for one word arranged in the Y-axis direction, and one output line 332a is adjacent to the word line 32a and the column of the memory 31. To do.

Although the memory circuit 300a has been described above, the configuration of the adjacent memory circuit 300b is the same as that of the memory circuit 300a. Therefore, although detailed description is omitted, the main configuration of the memory circuit 300b is as follows. The memory circuit 300b has a memory 31, a word line 32b, a bit line 33b, and a switch 35. The memory 31 at the upper left of the memory circuit 300b has coordinates [1, K+1], and the memory 31 at the lower right of the memory circuit 300b has coordinates [N, 2K]. The memory circuit 300b includes N word lines 32b(1) to 32b(N) and K bit lines 33b(K+1) to 33b(2K).

In the memory circuit 300b, the word line 32b receives read signals rd_en(N+1) to rd_en(2N) that enable the memory 31 in the corresponding column to be read from the memory control unit. Further, the output line 332b outputs the signal stored in the memory 31 of the corresponding row, respectively. Specifically, the output line 332b(1) outputs the signal d_col(N+1). Similarly, the output line 332b(2) outputs the signal d_col(N+2), and the output line 332b(N) outputs the signal d_col(2N).

Next, the signal flow of the memory circuit will be described with reference to FIG. FIG. 3 is a diagram showing a signal flow of the memory circuit. FIG. 3 schematically shows the memory circuit 300a of the memory unit 30. In the figure, the word line 32a(1) is a word line corresponding to the memory array in the first column. The digit line 331a(1) is a digit line corresponding to the memory array on the first row. Further, the output line 332a(1) is an output line connected to the digit line 331a(1). Similarly, the digit line 331a(N) is a digit line corresponding to the memory array in the Nth row. Similarly, the output line 332a(K) is an output line connected to the digit line 331a(K). The bold arrows shown in the figure mean the flow of signals output from the memory 31. The example shown in the figure is a situation in which the word line 32a(1) receives the read signal rd_en(1) from the memory control unit.

When the word line 32a(1) receives a read signal rd_en(1) from the memory control section, which enables the corresponding memory 31 in the first column to be read, the corresponding switch 35 is turned on. As a result, the memory 31 in the first column is connected to the corresponding bit line 33a. Then, the signals respectively stored in the memory 31 of the first column are transmitted to the output line 332a via the digit line 331a of the corresponding bit line 33a, and the transmitted signals are respectively supplied to the signal output circuit 40. To be done.

For example, the memory 31 at the coordinates [1, 1] supplies a signal to the digit line 331a(1) in the first row. Then, the output line 332a(1) connected to the digit line 331a(1) outputs the signal of the memory 31 at the coordinate [1,1] as the output signal d_col(1).

Further, the memory 31 at the coordinates [2, 1] supplies a signal to the digit line 331a(2) in the second row. Then, the output line 332a(2) connected to the digit line 331a(2) outputs the signal of the memory 31 at the coordinate [2,1] as the output signal d_col(2).

Similarly, the memory 31 at the coordinates [N, 1] supplies a signal to the digit line 331a(N) in the Nth row. Then, the output line 332a(N) connected to the digit line 331a(N) outputs the signal of the memory 31 at the coordinate [N,1] as the output signal d_col(N).

The memory control unit supplies one read signal to one memory circuit at any time. For example, when the memory circuit 300a receives the read signal rd_en(1), the other word line 32a included in the memory circuit 300a does not receive the read signal. As a result, the digit line 331a connected to the plurality of memories 31 receives a signal from the one memory 31 connected by the read signal. That is, the memory circuit 300a can output the binary signal for one word from the plurality of bit lines 33a by outputting the memory 31 in one column that can be read by the word line 32a.

Next, the relationship between the read signal and the output signal will be further described with reference to FIG. FIG. 4 is a timing diagram showing an example of signals output from the memory circuit. The upper part of the figure shows the read signals received by the word line 32a and the word line 32b from the memory control unit for each word line. For example, the read signal rd_en(1) received by the word line 32a(1) in the first column is shown at the top of the figure, and the read signal rd_en received by the word line 32b(2K) in the 2Kth column in sequence. Parts up to (2K) are omitted.

From time t0 to time t1, the word line 32a(1) in the first column receives the read signal rd_en(1). Thus, the read signal is continuously supplied to the target word line for the preset read period. The preset read period is a period from when the read signal is transmitted to the word line to when the signal of the target memory 31 is output.

The signal rd_en(2) adjacent to the lower side of the read signal rd_en(1) is a read signal received by the word line 32a in the second column. As shown in the drawing, the read signals are supplied for each column and are set so as not to overlap each other. When the supply of the read signal to the predetermined word line is completed, the word line in the next column receives the read signal. Therefore, the subsequent word lines 32a also sequentially receive the read signal for the same period, and finally the word line 32b in the 2Kth column receives the read signal rd_en(2K).

Shown below the read signal are the output signals of the bit lines 33a and 33b. The output signal d_col(1) is a signal corresponding to the bit line 33a(1) in the first row of the memory circuit 300a. The output signal d_col(2) adjacent to the lower side of the output signal d_col(1) is a signal corresponding to the bit line 33a(2) in the second row of the memory circuit 300a. The output signal d_col(N) is a signal corresponding to the bit line 33a(N) in the Nth row of the memory circuit 300a. Similarly, the output signal d_col(N+1) is a signal corresponding to the bit line 33b(1) in the first row of the memory circuit 300b, and the output signal d_col(2N) is the bit line in the Nth row of the memory circuit 300b. This is a signal corresponding to 33b(N).

As shown in the figure, the output signal of the bit line 33a corresponds to the word line 32a, and the output signal of the bit line 33b corresponds to the word line 32b. For example, between time t0 and time t1, the signal corresponding to the word line 32a(1) in the first column is output via the bit lines 33a(1) to 33a(N). At this time, as the output signal d_col(1) of the bit line 33a(1), the signal stored in the memory 31 of the coordinate [1,1] is output from the output line 332a(1). Similarly, as the output signal d_col(2) of the bit line 33a(2) in the second row, the signal stored in the memory 31 at the coordinate [2,1] is output, and the bit line 33a(N in the Nth row is output. ) Output signal d_col(N), the signal stored in the memory 31 at the coordinate [N, 1] is output.

Next, between time t1 and time t2, the signal corresponding to the word line 32a(2) in the second column is output via the bit lines 33a(1) to 33a(N). At this time, as the output signal d_col(1) of the bit line 33a(1), the signal stored in the memory 31 of the coordinates [1, 2] is output from the output line 332a(1). Similarly, the signal stored in the memory 31 at the coordinate [2, 2] is output as the output signal d_col(2) of the bit line 33a(2) of the second row, and the bit line 33a(N of the Nth row is output. ) Output signal d_col(N), the signal stored in the memory 31 at the coordinate [N, 2] is output.

In this way, the memory circuit 300a sequentially outputs the signal for one word stored for each column through the bit line 33a shared by each digit while sequentially switching the word line 32a until time t3.

Next, between time t3 and time t4, the memory circuit 300b outputs a signal via the bit line 33b, as in the case of the memory circuit 300a described above. That is, the memory circuit 300b sequentially receives the read signal rd_en(K+1) to the read signal rd_en(2K) while switching the word line 32b from the K+1th column to the 2Kth column from the time t3 to the time t4. Then, the bit line 33b sequentially outputs signals for one word corresponding to the read signal from the output signal d_col(N+1) to the output signal d_col(2N).

As described above, the semiconductor device 1 according to the first embodiment sequentially outputs the signals stored in the memory section 30 for each word. Therefore, the semiconductor device 1 does not need to rearrange the binary signals sequentially output by the memory unit 30. With such a configuration, the semiconductor device 1 can output a desired signal while suppressing an increase in the circuit scale of the signal output circuit.

Next, the relationship of signal processing of the ADC circuit 20 and the memory unit 30 will be described with reference to FIG. FIG. 5 is a timing chart of signals output from the ADC circuit and the memory circuit. In the figure, the transfer control signal latch and the ramp signal shown in the upper stage are waveforms that control the ADC circuit 20 and the memory unit 30. The binary signal after AD conversion is transferred to the memory unit 30 according to the transfer control signal latch. The power supply noise shown below the ramp signal is a waveform of noise generated in the power supply circuit of the ADC circuit 20. A plurality of rectangular waves shown under the power supply noise are read signals generated in the memory control unit and the memory unit 30.

In the figure, during the period from time t5 to time t7, the memory control unit generates the read signal and sequentially supplies the generated read signal to the memory unit 30. Along with this, the memory section 30 outputs a signal corresponding to the read signal for each word line that has received the read signal, and sequentially supplies the output signal to the signal output circuit 40. Further, the signal output circuit 40 sequentially outputs the signal received from the memory unit 30 to another circuit.

During the period from time t5 to time t7, the power supply noise shown in the figure occurs in the power supply circuit of the ADC circuit 20 due to the above-described processing performed by the memory control unit, the memory unit 30, and the signal output circuit 40. The power supply noise generated here is generated by the fluctuation of the power supply voltage under the influence of the above-described processing. That is, when the voltage fluctuation of the processing due to one read signal increases, the power supply noise tends to increase accordingly. In other words, the amplitude of the power supply noise can be suppressed by suppressing the voltage fluctuation of the processing due to one read signal.

On the other hand, during the period Pc from time t6 to time t7, the ADC circuit 20 generates a ramp signal and performs AD conversion. That is, the semiconductor device 1 performs the AD conversion processing by the ADC circuit 20 and the reading processing of the signal stored in the memory unit 30 in parallel during the period Pc.

If the voltage of the ramp signal fluctuates, the ADC circuit 20 may not be able to correctly perform AD conversion processing. Therefore, when the power supply noise is relatively large enough to cause the ADC circuit 20 to malfunction, it is not preferable that the ADC circuit 20 and the memory circuit 300b perform the parallel processing as described above. However, when the power supply noise is not relatively large enough to cause the ADC circuit 20 to malfunction, the AD conversion process and the process of reading a signal from the memory unit 30 are performed in parallel as shown in FIG. The time can be shortened.

For example, the power supply noise in the case where a signal is read at once from a plurality of memories of the same digit arranged in the X-axis direction of the memory array in the memory unit, the power supply noise is smaller than the power supply noise in the present embodiment. The fluctuation is very large. When the fluctuation of the power supply noise voltage is extremely large, it is not preferable to perform the AD conversion process performed by the ADC circuit and the process of reading a signal from the memory array in parallel. On the other hand, the process performed by the semiconductor device 1 according to the present embodiment with one read signal is to read a very small signal of about 10 bits. Therefore, the semiconductor device 1 can suppress the power supply noise due to the signal reading process of the memory unit 30.

Next, variations of the process of reading the signal of the memory 31 will be described with reference to FIG. FIG. 6 is a timing chart showing another example of signals output from the memory circuit. Unlike the example shown in FIG. 4, in the example shown in FIG. 6, in the semiconductor device 1, the memory circuit 300a and the memory circuit 300b perform the signal reading process in parallel.

That is, from the time t8 to the time t9, the word line 32a(1) in the first column included in the memory circuit 300a receives the read signal rd_en(0). In response to this, the bit line 33a(1) to the bit line 33a(N) output a binary signal from the memory of the coordinates [1, 1] to [N, 1].

Similarly, between time t8 and time t9, the K+1-th column word line 32a(K+1) of the memory circuit 300b receives the read signal rd_en(K+1). In response to this, the bit lines 33b(1) to 33b(N) output binary signals from the memories of the coordinates [1, K+1] to [N, K+1].

Therefore, between time t8 and time t9, the binary signal corresponding to the word line 32a(1) in the first column of the memory circuit 300a and the word line 32b(K+1) in the K+1 column of the memory circuit 300b are associated. And the binary signal to be output are simultaneously output.

By thus supplying the read signals to the word lines of the different memory circuits at the same time, the semiconductor device 1 can read the signals from all the memories 31 between time t8 and time t10. In this case, the reading process can be performed in substantially half the period as compared with the example shown in FIG.

By supplying the read signals to the two word lines at the same time, the binary signals for two words can be read at the same time. Although the case where the number of the memory circuits 300 is two (the memory circuit 300a and the memory circuit 300b) is shown in this embodiment mode, it goes without saying that the number of the memory circuits may be three or more. With such a configuration, it is possible to simultaneously read the binary signals of several words by supplying the read signals to the plurality of word lines at the same time. As a result, it is possible to reduce the time required to read the memory circuit to a fraction.

Even when the read signals are simultaneously supplied to the plurality of word lines, the power supply noise of the ADC circuit 20 at this time does not reach the noise level at which the ADC circuit 20 may malfunction. .. Therefore, as described in FIG. 5, the processing of the ADC circuit 20 and the reading processing of the memory unit 30 can be performed in parallel. Therefore, the semiconductor device 1 having such a configuration can shorten the processing time.

Although the first embodiment has been described above, the configuration of the semiconductor device 1 according to the first embodiment is not limited to the above. For example, the memory unit 30 may have three or more memory circuits. The number of word lines 32 included in one memory circuit 300 does not have to be the same as the number of bit lines 33. That is, in the above description, N and K need not be the same. Further, it is not necessary that the plurality of memory circuits 300 have the same number of word lines 32. Similarly, it is not necessary for the plurality of memory circuits 300 to have the same number of bit lines 33. For example, when the number of word lines 32 included in the memory circuit 300 is larger than the number of bit lines 33, the output lines included in the bit lines are adjacent to the word lines 32 arranged adjacent to the memories arranged in the Y-axis direction. There is a part that is not placed.

Further, in the above description, the memory circuit 300a is configured such that the plurality of word lines are not arranged adjacent to each other and the plurality of bit lines are not arranged adjacent to each other. As a result, the semiconductor device 1 suppresses an increase in circuit area and realizes an efficient circuit. However, even if it does not correspond to the above configuration, as long as the binary signal for one word corresponding to the selected word line is sequentially read, a portion where a plurality of word lines are adjacent to each other may be included. However, a portion where a plurality of bit lines are adjacent to each other may be included.

As described above, according to the first embodiment, it is possible to provide a semiconductor device or the like that suppresses an increase in the area of the signal output circuit.

<Second Embodiment>
Next, a second embodiment will be described. The second embodiment differs from the first embodiment in the configuration of the circuit that transmits the signal output from the memory circuit. Therefore, in the following description, differences from the first embodiment will be mainly described.

FIG. 7 is a diagram illustrating a signal output circuit in the semiconductor device according to the second embodiment. The semiconductor device 2 shown in the figure has three memory circuits 300d, 300e, and 300f in the memory section 30. The memory circuit 300d is provided with N output lines, and the respective output signals are d_col(1) to d_col(N). The memory circuit 300e is also provided with N output lines, and the respective output signals are d_col(N+1) to d_col(2N). Similarly, the memory circuit 300f is also provided with N output lines, and the respective output signals are d_col(2N+1) to d_col(3N).

The signal output circuit 40 receives the signal output from the memory unit 30. The signal output circuit 40 has a plurality of transmission lines 41 corresponding to the output signals. The plurality of transmission lines 41 are labeled as follows according to the corresponding output signals. For example, one connected to the output signal d_col(1) of the memory circuit 300d is referred to as a transmission line 41d(1). Further, one connected to the output signal d_col(N) of the memory circuit 300d is referred to as a transmission line 41d(N). Similarly, the one connected to the output signal d_col(N+1) of the memory circuit 300e is called a transmission line 41e(N+1), and the one connected to the output signal d_col(2N) of the memory circuit 300e is the transmission line 41e. It is called (2N). Similarly, the one connected to the output signal d_col(2N+1) of the memory circuit 300f is called a transmission line 41f(2N+1), and the one connected to the output signal d_col(3N) of the memory circuit 300f is the transmission line 41f( 3N).

Further, the signal output circuit 40 has N logic circuits 400a and N logic circuits 400b. The logic circuits 400a and 400b each have a function of receiving two signals, performing a logical operation on the received signals, and outputting an operation result. The logic circuits 400a and 400b in this embodiment are set to perform a logical sum (OR) operation.

The logic circuit 400a receives one signal transmitted from the memory circuit 300d and one signal transmitted from the memory circuit 300e, respectively, performs a logical operation on the received signal, and outputs the operation result to the transmission line 42. Output. One logic circuit 400a is configured to receive a corresponding digit signal from the memory circuits 300d and 300e. For example, when one logic circuit 400a receives the signal of the first digit of the binary signal (output signal d_col(1)) from the memory circuit 300d as one input, the first digit of the memory circuit 300e also receives as the other input. Signal (output signal d_col(N+1)) is received. Similarly, when one logic circuit 400a receives the Nth digit signal (output signal d_col(N)) of the binary signal from the memory circuit 300d as one input, the Nth digit is also input from the memory circuit 300e as the other input. Receive the eye signal (output signal d_col(2N)). The N logic circuits 400a thus receive the signals of the corresponding digits of the binary signal, and output the results of the logical sum of these to the corresponding transmission lines 42, respectively.

Each of the transmission lines 42 has a number in parentheses corresponding to the number of digits of the binary signal. That is, the logic circuit 400a that outputs the operation result of the first digit of the binary signal is connected to the transmission line 42(1), and the logic circuit 400a that outputs the operation result of the Nth digit of the binary signal is N).

The logic circuit 400a receives either the signal H (High) having a relatively high voltage level or the signal L (Low) having a relatively low voltage level from the memory circuit 300d and the memory circuit 300e. Further, in the present embodiment, all the signals of the circuits which have not received the read signal are set to the voltage level of the signal L. That is, when one of the two signals received by the logic circuit 400 becomes the signal H, the logic circuit 400a and the logic circuit 400b output the signal H. The transmission lines 42(1) to 42(N) are connected to the corresponding logic circuits 400b.

The logic circuit 400b receives the signal of the result of the logical operation transmitted from the transmission line 42 and one signal transmitted from the memory circuit 300f, performs the logical operation on the received signal, and outputs the operation result to the transmission line. Output to 43. The transmission line 43 has a number corresponding to the number of digits corresponding to the binary signal in parentheses. That is, the logic circuit 400b that outputs the calculation result of the first digit of the binary signal is connected to the transmission line 43(1), and the logic circuit 400b that outputs the calculation result of the Nth digit of the binary signal is the transmission line 43(1). N). The signal output from the transmission line 43(N) is the signal ch(N). In this case, the signal ch(N) is the Nth digit signal of the binary signal of the column to which the read signal is supplied.

Like the logic circuit 400a, the logic circuit 400b is configured to receive the signal of the corresponding digit of the binary signal from the logic circuit 400a and the memory circuit 300f. For example, when one logic circuit 400b receives the operation result corresponding to the Nth digit signal of the binary signal as one input via the transmission line 42(N), the other input also receives N from the memory circuit 300f. The signal of the digit (output signal d_col(3N)) is received. In this case, the logic circuit 400b supplies the signal ch(N) as the Nth digit signal to the transmission line 43(N).

As described above, the logic circuit 400a and the logic circuit 400b are connected in a cascade manner and output the logical operation result of the signal of the corresponding digit. For example, as the calculation result of the logic circuit 400a, H is output when the signal H is received from either the memory circuit 300d or the memory circuit 300e. That is, the signal received by the logic circuit 400b from the logic circuit 400a corresponds to the signal output from the memory circuit 300d or the memory circuit 300e. That is, the two signals received by the logic circuits 400b connected in cascade are both the signals of the corresponding digits in the binary signals stored in the memory circuit.

The above configuration can also be described as follows. The logic circuit 400a receives the first signal transmitted from the bit line of the memory circuit 300d and the second signal transmitted from the bit line of the memory circuit 300e, and outputs the result of these logical operations to the first logic. Output as calculation result.

Further, the logic circuit 400b can also be described as follows. The logic circuit 400b receives the first signal, which is the result of the first logic operation, and the second signal, which is transmitted from the bit line of the memory circuit 300f, and outputs the result of these logic operations. The first signal in this case is a signal corresponding to one of the signal transmitted from the bit line of the memory circuit 300d and the signal transmitted from the bit line of the memory circuit 300e.

The signal flow will be described below with reference to the drawings together with a specific example. The following specific example is a case where an arbitrary word line of the memory circuit 300d receives a read signal. That is, as the output signals d_col(1) to d_col(N) of the memory circuit 300d, either the signal H or the signal L is output as a binary signal received from the ADC circuit 20. Therefore, the logic circuit 400a receives the above-mentioned signal from the memory circuit 300d. On the other hand, the memory circuit 300e has not received the read signal at this time. Therefore, in the memory circuit 300e, all output signals are the signals L. Therefore, the logic circuit 400a receives the signal L from the memory circuit 300e. The logic circuit 400a performs an OR operation on these received signals. Therefore, as a result, the same signal as the signal received from the memory circuit 300e is output to the logic circuit 400b.

Next, the logic circuit 400b receiving the operation result from the logic circuit 400a receives the output signal from the memory circuit 300f as the other input signal. Since the memory circuit 300f has not received the read signal at this time, all the output signals are the signals L. Therefore, the logic circuit 400b performs an OR operation on these received signals and, as a result, outputs the same signal as the signal received from the memory circuit 300e to the transmission line 43.

In this way, the signal output circuit 40 of the semiconductor device 2 can suppress an increase in the circuit area by connecting the signals of the corresponding digits of the binary signal in a cascade manner by the logic circuit. In the above example, the semiconductor device 2 has the memory circuit 300d, the memory circuit 300e, and the memory circuit 300f, but the configuration of the present embodiment is not limited to this, and has four or more memory circuits. May be. In this case, even if the number of memory circuits increases, the signal of the digit corresponding to the binary signal is connected to the continuous line via the logic circuit, so that the signal line does not get crowded and the circuit configuration is simple. You can

Next, the signal processing in the signal output circuit 40 will be further described with reference to FIG. FIG. 8 is a timing chart of signals output by the semiconductor device according to the second embodiment. The read signals rd_en(1) to read signal rd_en(3K) received by the memory circuits 300d to 300f are shown in the upper part of the figure. The memory control unit sequentially supplies a read signal from the word line 32(1) in the first column to the word line 32(3K) in the 3Kth column.

The lower part of the figure shows signals output from the transmission lines 43(1) to 43(N) of the signal output circuit 40. The transmission line 43(1) outputs the signal ch(1), the transmission line 43(2) outputs the signal ch(2), and similarly, the transmission line 43(N) outputs the signal ch(N). Is output.

From the time t11 to the time t12, the transmission line 43 stores the coordinates [1, 1], [2, 1],... [N-1 of the memory as a binary signal corresponding to the word line in the first column. , 1] and [N, 1] memory signals are output. Then, by the time t13, the transmission line 43 sequentially outputs the binary signals corresponding to the word lines up to the K-th column included in the memory circuit 300d.

Next, from time t13 to time t14, the transmission line 43 sequentially outputs the binary signals corresponding to the word lines from the (K+1)th column to the 2Kth column of the memory circuit 300e.

Subsequently, from time t14 to time t15, the transmission line 43 sequentially outputs the binary signals corresponding to the word lines from the 2K+1th column to the 3Kth column of the memory circuit 300f.

As described above, the semiconductor device 2 according to the second embodiment can output the signal of the common digit of the binary signal through the common transmission line 43(1) to transmission line 43(N).

The second embodiment has been described above. The semiconductor device 2 according to the second embodiment can output the signal of the memory circuit receiving the read signal to another circuit via the logic circuit connected in cascade. With such a configuration, the semiconductor device 2 can suppress an increase in circuit area. In addition, for example, when a signal is selectively output using a multiplexer, the central portion of the circuit may be congested. However, according to the present embodiment, the circuit is configured in a cascaded manner, so that the wiring density of the circuit is reduced. It is possible to suppress the concentration, suppress the increase in the circuit area, and thus suppress the increase in the power consumption.

The cascade-connected logic circuits described in the present embodiment may perform a logical product (AND) instead of a logical sum (OR). In that case, the output signal of each memory circuit may be inverted from that in the above case, and the signal H may be set to be output when the read signal is not received.

Further, a plurality of structures of this embodiment mode may be provided and a plurality of transmission lines may read the memory circuit and output signals in parallel. As a result, it is possible to provide a semiconductor device that reduces the time for signal output processing while suppressing an increase in area.

Next, another example of the second embodiment will be described with reference to FIG. FIG. 9 is a configuration diagram of the memory circuit and the signal output circuit in the semiconductor device according to the second embodiment. In the configuration shown in the figure, portions necessary for description are extracted from the configurations of the memory unit 30 and the signal output circuit 40 of the semiconductor device 2. Further, the semiconductor device 3 has ten memory circuits. Therefore, in the semiconductor device 3, nine logic circuits 400 are connected in a cascade. The signal output circuit 40 of the semiconductor device 2 has a plurality of flip-flop circuits 410, a flip-flop circuit 420, a flip-flop circuit 431, and a signal control circuit 430.

The flip-flop circuit 410 is interposed between the plurality of bit lines of the memory unit 30 and the plurality of logic circuits 400 of the signal output circuit 40. Further, the flip-flop circuit 420 is connected to the transmission line 43. The flip-flop circuit 431 is connected to the signal control circuit 430. These flip-flop circuits adjust the waveform of the transmitted digital signal and suppress the delay of the signal. The logic circuit 430 is connected to the plurality of transmission lines 43, and outputs a binary signal received via the transmission lines 43 by an appropriately preset method.

With such a configuration, the semiconductor device 3 can suppress the deterioration of the transmitted signal and suppress the increase of the circuit area.

The present invention is not limited to the above-described embodiment, but can be modified as appropriate without departing from the spirit of the present invention.

1, 2 and 3 semiconductor device 10 pixel array 11 photoelectric conversion element 20 ADC circuit 30 memory unit 31 memory 32 word line 33 bit line 35 switch 40 signal output circuit 41, 42, 43 transmission line 300 memory circuit 331a, 331b digit line 332a 332b Output lines 400, 430 Logic circuits 410, 420, 431 Flip-flop circuit

Claims (11)

A memory array having a plurality of memories arranged in a matrix in a first direction and a second direction orthogonal to the first direction;
A word line extending in the first direction and capable of reading signals included in the plurality of memories arranged in the first direction;
The word line has a digit line connected to each of the plurality of memories arranged in the second direction and an output line connected to the digit line and extending in the first direction, and the word line can read the signal. A bit line for transmitting the signal from the memory corresponding to the word line to the output line. The memory circuit according to claim 1, wherein the word line is adjacent to a plurality of corresponding memories arranged in the first direction. 3. The memory circuit according to claim 1, wherein the word line has a read switch for making it possible to read a plurality of corresponding memories. The memory circuit according to claim 1, wherein the bit line is adjacent to the word line and the plurality of memories arranged in the first direction, respectively. A semiconductor device comprising a plurality of the memory circuits according to claim 1. A first memory circuit that is a memory circuit having a first word line that is the first word line and a first bit line that is the bit line corresponding to the first word line;
A second memory, which is a memory circuit different from the first memory circuit, having a second word line which is the second word line and a second bit line which is the bit line corresponding to the second word line. Circuit,
Receiving a first signal based on the output from the first bit line and a second signal based on the output from the second bit line, performing a logical operation based on the first signal and the second signal, and The semiconductor device according to claim 5, further comprising a logic circuit that outputs a result of a logical operation. The semiconductor device according to claim 6, wherein the logic circuit performs a logical sum operation. The semiconductor device according to claim 6, wherein the logic circuit performs a logical product operation. 9. The semiconductor device according to claim 6, further comprising a flip-flop circuit interposed between the bit line and the logic circuit. Further comprising a pixel array having photoelectric conversion elements arranged in a matrix,
The semiconductor device according to claim 5, wherein the memory array stores a pixel signal generated by the pixel array. A semiconductor device according to claim 10,
An optical lens for forming a subject image on the pixel array,
A mobile device having at least.

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